pcihost_fdt.c revision 1.15
1 /* $NetBSD: pcihost_fdt.c,v 1.15 2020/01/07 10:20:07 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pcihost_fdt.c,v 1.15 2020/01/07 10:20:07 skrll Exp $"); 31 32 #include <sys/param.h> 33 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/extent.h> 37 #include <sys/intr.h> 38 #include <sys/kernel.h> 39 #include <sys/kmem.h> 40 #include <sys/lwp.h> 41 #include <sys/mutex.h> 42 #include <sys/queue.h> 43 #include <sys/systm.h> 44 45 #include <machine/cpu.h> 46 47 #include <arm/cpufunc.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pciconf.h> 52 53 #include <dev/fdt/fdtvar.h> 54 55 #include <arm/pci/pci_msi_machdep.h> 56 #include <arm/fdt/pcihost_fdtvar.h> 57 58 #define PCIHOST_DEFAULT_BUS_MIN 0 59 #define PCIHOST_DEFAULT_BUS_MAX 255 60 61 #define PCIHOST_CACHELINE_SIZE arm_dcache_align 62 63 int pcihost_segment = 0; 64 65 static int pcihost_match(device_t, cfdata_t, void *); 66 static void pcihost_attach(device_t, device_t, void *); 67 68 static int pcihost_config(struct pcihost_softc *); 69 70 static void pcihost_attach_hook(device_t, device_t, 71 struct pcibus_attach_args *); 72 static int pcihost_bus_maxdevs(void *, int); 73 static pcitag_t pcihost_make_tag(void *, int, int, int); 74 static void pcihost_decompose_tag(void *, pcitag_t, int *, int *, int *); 75 static u_int pcihost_get_segment(void *); 76 static pcireg_t pcihost_conf_read(void *, pcitag_t, int); 77 static void pcihost_conf_write(void *, pcitag_t, int, pcireg_t); 78 static int pcihost_conf_hook(void *, int, int, int, pcireg_t); 79 static void pcihost_conf_interrupt(void *, int, int, int, int, int *); 80 81 static int pcihost_intr_map(const struct pci_attach_args *, 82 pci_intr_handle_t *); 83 static const char *pcihost_intr_string(void *, pci_intr_handle_t, 84 char *, size_t); 85 static const struct evcnt *pcihost_intr_evcnt(void *, pci_intr_handle_t); 86 static int pcihost_intr_setattr(void *, pci_intr_handle_t *, int, 87 uint64_t); 88 static void * pcihost_intr_establish(void *, pci_intr_handle_t, 89 int, int (*)(void *), void *, 90 const char *); 91 static void pcihost_intr_disestablish(void *, void *); 92 93 static int pcihost_bus_space_map(void *, bus_addr_t, bus_size_t, 94 int, bus_space_handle_t *); 95 96 CFATTACH_DECL_NEW(pcihost_fdt, sizeof(struct pcihost_softc), 97 pcihost_match, pcihost_attach, NULL, NULL); 98 99 static const struct of_compat_data compat_data[] = { 100 { "pci-host-cam-generic", PCIHOST_CAM }, 101 { "pci-host-ecam-generic", PCIHOST_ECAM }, 102 { NULL, 0 } 103 }; 104 105 static int 106 pcihost_match(device_t parent, cfdata_t cf, void *aux) 107 { 108 struct fdt_attach_args * const faa = aux; 109 110 return of_match_compat_data(faa->faa_phandle, compat_data); 111 } 112 113 static void 114 pcihost_attach(device_t parent, device_t self, void *aux) 115 { 116 struct pcihost_softc * const sc = device_private(self); 117 struct fdt_attach_args * const faa = aux; 118 bus_addr_t cs_addr; 119 bus_size_t cs_size; 120 int error; 121 122 if (fdtbus_get_reg(faa->faa_phandle, 0, &cs_addr, &cs_size) != 0) { 123 aprint_error(": couldn't get registers\n"); 124 return; 125 } 126 127 sc->sc_dev = self; 128 sc->sc_dmat = faa->faa_dmat; 129 sc->sc_bst = faa->faa_bst; 130 sc->sc_phandle = faa->faa_phandle; 131 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 132 _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED, &sc->sc_bsh); 133 if (error) { 134 aprint_error(": couldn't map registers: %d\n", error); 135 return; 136 } 137 sc->sc_type = of_search_compatible(sc->sc_phandle, compat_data)->data; 138 139 #ifdef __HAVE_PCI_MSI_MSIX 140 if (sc->sc_type == PCIHOST_ECAM) { 141 sc->sc_pci_flags |= PCI_FLAGS_MSI_OKAY; 142 sc->sc_pci_flags |= PCI_FLAGS_MSIX_OKAY; 143 } 144 #endif 145 146 aprint_naive("\n"); 147 aprint_normal(": Generic PCI host controller\n"); 148 149 pcihost_init(&sc->sc_pc, sc); 150 pcihost_init2(sc); 151 } 152 153 void 154 pcihost_init2(struct pcihost_softc *sc) 155 { 156 struct pcibus_attach_args pba; 157 const u_int *data; 158 int len; 159 160 if ((data = fdtbus_get_prop(sc->sc_phandle, "bus-range", &len)) != NULL) { 161 if (len != 8) { 162 aprint_error_dev(sc->sc_dev, "malformed 'bus-range' property\n"); 163 return; 164 } 165 sc->sc_bus_min = be32toh(data[0]); 166 sc->sc_bus_max = be32toh(data[1]); 167 } else { 168 sc->sc_bus_min = PCIHOST_DEFAULT_BUS_MIN; 169 sc->sc_bus_max = PCIHOST_DEFAULT_BUS_MAX; 170 } 171 172 /* 173 * Assign a fixed PCI segment ("domain") number. If the property is not 174 * present, assign one. The binding spec says if this property is used to 175 * assign static segment numbers, all host bridges should have segments 176 * astatic assigned to prevent overlaps. 177 */ 178 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-domain", &sc->sc_seg)) 179 sc->sc_seg = pcihost_segment++; 180 181 if (pcihost_config(sc) != 0) 182 return; 183 184 memset(&pba, 0, sizeof(pba)); 185 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 186 PCI_FLAGS_MRM_OKAY | 187 PCI_FLAGS_MWI_OKAY | 188 sc->sc_pci_flags; 189 pba.pba_iot = &sc->sc_io.bst; 190 pba.pba_memt = &sc->sc_mem.bst; 191 pba.pba_dmat = sc->sc_dmat; 192 #ifdef _PCI_HAVE_DMA64 193 pba.pba_dmat64 = sc->sc_dmat; 194 #endif 195 pba.pba_pc = &sc->sc_pc; 196 pba.pba_bus = sc->sc_bus_min; 197 198 config_found_ia(sc->sc_dev, "pcibus", &pba, pcibusprint); 199 } 200 201 void 202 pcihost_init(pci_chipset_tag_t pc, void *priv) 203 { 204 pc->pc_conf_v = priv; 205 pc->pc_attach_hook = pcihost_attach_hook; 206 pc->pc_bus_maxdevs = pcihost_bus_maxdevs; 207 pc->pc_make_tag = pcihost_make_tag; 208 pc->pc_decompose_tag = pcihost_decompose_tag; 209 pc->pc_get_segment = pcihost_get_segment; 210 pc->pc_conf_read = pcihost_conf_read; 211 pc->pc_conf_write = pcihost_conf_write; 212 pc->pc_conf_hook = pcihost_conf_hook; 213 pc->pc_conf_interrupt = pcihost_conf_interrupt; 214 215 pc->pc_intr_v = priv; 216 pc->pc_intr_map = pcihost_intr_map; 217 pc->pc_intr_string = pcihost_intr_string; 218 pc->pc_intr_evcnt = pcihost_intr_evcnt; 219 pc->pc_intr_setattr = pcihost_intr_setattr; 220 pc->pc_intr_establish = pcihost_intr_establish; 221 pc->pc_intr_disestablish = pcihost_intr_disestablish; 222 } 223 224 static int 225 pcihost_config(struct pcihost_softc *sc) 226 { 227 struct extent *ioext = NULL, *memext = NULL, *pmemext = NULL; 228 const u_int *ranges; 229 u_int probe_only; 230 int error, len; 231 bool swap; 232 233 struct pcih_bus_space * const pibs = &sc->sc_io; 234 pibs->bst = *sc->sc_bst; 235 pibs->bst.bs_cookie = pibs; 236 pibs->map = pibs->bst.bs_map; 237 pibs->flags = PCI_FLAGS_IO_OKAY; 238 pibs->bst.bs_map = pcihost_bus_space_map; 239 240 struct pcih_bus_space * const pmbs = &sc->sc_mem; 241 pmbs->bst = *sc->sc_bst; 242 pmbs->bst.bs_cookie = pmbs; 243 pmbs->map = pmbs->bst.bs_map; 244 pmbs->flags = PCI_FLAGS_MEM_OKAY; 245 pmbs->bst.bs_map = pcihost_bus_space_map; 246 247 /* 248 * If this flag is set, skip configuration of the PCI bus and use existing config. 249 */ 250 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-probe-only", &probe_only)) 251 probe_only = 0; 252 if (probe_only) 253 return 0; 254 255 if (sc->sc_pci_ranges != NULL) { 256 ranges = sc->sc_pci_ranges; 257 len = sc->sc_pci_ranges_cells * 4; 258 swap = false; 259 } else { 260 ranges = fdtbus_get_prop(sc->sc_phandle, "ranges", &len); 261 if (ranges == NULL) { 262 aprint_error_dev(sc->sc_dev, "missing 'ranges' property\n"); 263 return EINVAL; 264 } 265 swap = true; 266 } 267 268 /* 269 * Each entry in the ranges table contains: 270 * - bus address (3 cells) 271 * - cpu physical address (2 cells) 272 * - size (2 cells) 273 * Total size for each entry is 28 bytes (7 cells). 274 */ 275 while (len >= 28) { 276 #define DECODE32(x,o) (swap ? be32dec(&(x)[o]) : (x)[o]) 277 #define DECODE64(x,o) (swap ? be64dec(&(x)[o]) : (((uint64_t)((x)[(o)+0]) << 32) + (x)[(o)+1])) 278 const uint32_t phys_hi = DECODE32(ranges, 0); 279 const uint64_t bus_phys = DECODE64(ranges, 1); 280 const uint64_t cpu_phys = DECODE64(ranges, 3); 281 const uint64_t size = DECODE64(ranges, 5); 282 #undef DECODE32 283 #undef DECODE64 284 285 len -= 28; 286 ranges += 7; 287 288 const bool is64 = (__SHIFTOUT(phys_hi, PHYS_HI_SPACE) == 289 PHYS_HI_SPACE_MEM64) ? true : false; 290 switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) { 291 case PHYS_HI_SPACE_IO: 292 if (pibs->nranges + 1 >= __arraycount(pibs->ranges)) { 293 aprint_error_dev(sc->sc_dev, "too many IO ranges\n"); 294 continue; 295 } 296 pibs->ranges[pibs->nranges].bpci = bus_phys; 297 pibs->ranges[pibs->nranges].bbus = cpu_phys; 298 pibs->ranges[pibs->nranges].size = size; 299 ++pibs->nranges; 300 if (ioext != NULL) { 301 aprint_error_dev(sc->sc_dev, "ignoring duplicate IO space range\n"); 302 continue; 303 } 304 ioext = extent_create("pciio", bus_phys, bus_phys + size - 1, NULL, 0, EX_NOWAIT); 305 aprint_verbose_dev(sc->sc_dev, 306 "IO: 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 307 bus_phys, size, cpu_phys); 308 /* reserve a PC-like legacy IO ports range, perhaps for access to VGA registers */ 309 if (bus_phys == 0 && size >= 0x10000) 310 extent_alloc_region(ioext, 0, 0x1000, EX_WAITOK); 311 sc->sc_pci_flags |= PCI_FLAGS_IO_OKAY; 312 break; 313 case PHYS_HI_SPACE_MEM64: 314 /* FALLTHROUGH */ 315 case PHYS_HI_SPACE_MEM32: 316 if (pmbs->nranges + 1 >= __arraycount(pmbs->ranges)) { 317 aprint_error_dev(sc->sc_dev, "too many mem ranges\n"); 318 continue; 319 } 320 /* both pmem and mem spaces are in the same tag */ 321 pmbs->ranges[pmbs->nranges].bpci = bus_phys; 322 pmbs->ranges[pmbs->nranges].bbus = cpu_phys; 323 pmbs->ranges[pmbs->nranges].size = size; 324 ++pmbs->nranges; 325 if ((phys_hi & PHYS_HI_PREFETCH) != 0 || 326 __SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64) { 327 if (pmemext != NULL) { 328 aprint_error_dev(sc->sc_dev, "ignoring duplicate mem (prefetchable) range\n"); 329 continue; 330 } 331 pmemext = extent_create("pcipmem", bus_phys, bus_phys + size - 1, NULL, 0, EX_NOWAIT); 332 aprint_verbose_dev(sc->sc_dev, 333 "MMIO (%d-bit prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 334 is64 ? 64 : 32, bus_phys, size, cpu_phys); 335 } else { 336 if (memext != NULL) { 337 aprint_error_dev(sc->sc_dev, "ignoring duplicate mem (non-prefetchable) range\n"); 338 continue; 339 } 340 memext = extent_create("pcimem", bus_phys, bus_phys + size - 1, NULL, 0, EX_NOWAIT); 341 aprint_verbose_dev(sc->sc_dev, 342 "MMIO (%d-bit non-prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 343 is64 ? 64 : 32, bus_phys, size, cpu_phys); 344 } 345 sc->sc_pci_flags |= PCI_FLAGS_MEM_OKAY; 346 break; 347 default: 348 break; 349 } 350 } 351 352 if (memext == NULL && pmemext != NULL) { 353 memext = pmemext; 354 pmemext = NULL; 355 } 356 357 error = pci_configure_bus(&sc->sc_pc, ioext, memext, pmemext, sc->sc_bus_min, PCIHOST_CACHELINE_SIZE); 358 359 if (ioext) 360 extent_destroy(ioext); 361 if (memext) 362 extent_destroy(memext); 363 if (pmemext) 364 extent_destroy(pmemext); 365 366 if (error) { 367 aprint_error_dev(sc->sc_dev, "configuration failed: %d\n", error); 368 return error; 369 } 370 371 return 0; 372 } 373 374 static void 375 pcihost_attach_hook(device_t parent, device_t self, 376 struct pcibus_attach_args *pba) 377 { 378 } 379 380 static int 381 pcihost_bus_maxdevs(void *v, int busno) 382 { 383 return 32; 384 } 385 386 static pcitag_t 387 pcihost_make_tag(void *v, int b, int d, int f) 388 { 389 return (b << 16) | (d << 11) | (f << 8); 390 } 391 392 static void 393 pcihost_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 394 { 395 if (bp) 396 *bp = (tag >> 16) & 0xff; 397 if (dp) 398 *dp = (tag >> 11) & 0x1f; 399 if (fp) 400 *fp = (tag >> 8) & 0x7; 401 } 402 403 static u_int 404 pcihost_get_segment(void *v) 405 { 406 struct pcihost_softc *sc = v; 407 408 return sc->sc_seg; 409 } 410 411 static pcireg_t 412 pcihost_conf_read(void *v, pcitag_t tag, int offset) 413 { 414 struct pcihost_softc *sc = v; 415 int b, d, f; 416 u_int reg; 417 418 pcihost_decompose_tag(v, tag, &b, &d, &f); 419 420 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 421 return (pcireg_t) -1; 422 423 if (sc->sc_type == PCIHOST_CAM) { 424 if (offset & ~0xff) 425 return (pcireg_t) -1; 426 reg = (b << 16) | (d << 11) | (f << 8) | offset; 427 } else if (sc->sc_type == PCIHOST_ECAM) { 428 if (offset & ~0xfff) 429 return (pcireg_t) -1; 430 reg = (b << 20) | (d << 15) | (f << 12) | offset; 431 } else { 432 return (pcireg_t) -1; 433 } 434 435 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg); 436 } 437 438 static void 439 pcihost_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 440 { 441 struct pcihost_softc *sc = v; 442 int b, d, f; 443 u_int reg; 444 445 pcihost_decompose_tag(v, tag, &b, &d, &f); 446 447 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 448 return; 449 450 if (sc->sc_type == PCIHOST_CAM) { 451 if (offset & ~0xff) 452 return; 453 reg = (b << 16) | (d << 11) | (f << 8) | offset; 454 } else if (sc->sc_type == PCIHOST_ECAM) { 455 if (offset & ~0xfff) 456 return; 457 reg = (b << 20) | (d << 15) | (f << 12) | offset; 458 } else { 459 return; 460 } 461 462 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val); 463 } 464 465 static int 466 pcihost_conf_hook(void *v, int b, int d, int f, pcireg_t id) 467 { 468 return PCI_CONF_DEFAULT; 469 } 470 471 static void 472 pcihost_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep) 473 { 474 } 475 476 static int 477 pcihost_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 478 { 479 struct pcihost_softc *sc = pa->pa_pc->pc_intr_v; 480 u_int addr_cells, interrupt_cells; 481 const u_int *imap, *imask; 482 int imaplen, imasklen; 483 u_int match[4]; 484 int index; 485 486 if (pa->pa_intrpin == 0) 487 return EINVAL; 488 489 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 490 imask = fdtbus_get_prop(sc->sc_phandle, "interrupt-map-mask", &imasklen); 491 if (imap == NULL || imask == NULL || imasklen != 16) 492 return EINVAL; 493 494 /* Convert attach args to specifier */ 495 match[0] = htobe32( 496 __SHIFTIN(pa->pa_bus, PHYS_HI_BUS) | 497 __SHIFTIN(pa->pa_device, PHYS_HI_DEVICE) | 498 __SHIFTIN(pa->pa_function, PHYS_HI_FUNCTION) 499 ) & imask[0]; 500 match[1] = htobe32(0) & imask[1]; 501 match[2] = htobe32(0) & imask[2]; 502 match[3] = htobe32(pa->pa_intrpin) & imask[3]; 503 504 index = 0; 505 while (imaplen >= 20) { 506 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 507 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 508 addr_cells = 2; 509 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 510 interrupt_cells = 0; 511 if (imaplen < (addr_cells + interrupt_cells) * 4) 512 return ENXIO; 513 514 if ((imap[0] & imask[0]) == match[0] && 515 (imap[1] & imask[1]) == match[1] && 516 (imap[2] & imask[2]) == match[2] && 517 (imap[3] & imask[3]) == match[3]) { 518 *ih = index; 519 return 0; 520 } 521 522 imap += (5 + addr_cells + interrupt_cells); 523 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 524 index++; 525 } 526 527 return EINVAL; 528 } 529 530 static const u_int * 531 pcihost_find_intr(struct pcihost_softc *sc, pci_intr_handle_t ih, int *pihandle) 532 { 533 u_int addr_cells, interrupt_cells; 534 int imaplen, index; 535 const u_int *imap; 536 537 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 538 KASSERT(imap != NULL); 539 540 index = 0; 541 while (imaplen >= 20) { 542 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 543 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 544 addr_cells = 2; 545 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 546 interrupt_cells = 0; 547 if (imaplen < (addr_cells + interrupt_cells) * 4) 548 return NULL; 549 550 if (index == ih) { 551 *pihandle = map_ihandle; 552 return imap + 5 + addr_cells; 553 } 554 555 imap += (5 + addr_cells + interrupt_cells); 556 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 557 index++; 558 } 559 560 return NULL; 561 } 562 563 static const char * 564 pcihost_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 565 { 566 const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); 567 const int vec = __SHIFTOUT(ih, ARM_PCI_INTR_MSI_VEC); 568 struct pcihost_softc *sc = v; 569 const u_int *specifier; 570 int ihandle; 571 572 if (ih & ARM_PCI_INTR_MSIX) { 573 snprintf(buf, len, "irq %d (MSI-X vec %d)", irq, vec); 574 } else if (ih & ARM_PCI_INTR_MSI) { 575 snprintf(buf, len, "irq %d (MSI vec %d)", irq, vec); 576 } else { 577 specifier = pcihost_find_intr(sc, ih & ARM_PCI_INTR_IRQ, &ihandle); 578 if (specifier == NULL) 579 return NULL; 580 581 if (!fdtbus_intr_str_raw(ihandle, specifier, buf, len)) 582 return NULL; 583 } 584 585 return buf; 586 } 587 588 const struct evcnt * 589 pcihost_intr_evcnt(void *v, pci_intr_handle_t ih) 590 { 591 return NULL; 592 } 593 594 static int 595 pcihost_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 596 { 597 switch (attr) { 598 case PCI_INTR_MPSAFE: 599 if (data) 600 *ih |= ARM_PCI_INTR_MPSAFE; 601 else 602 *ih &= ~ARM_PCI_INTR_MPSAFE; 603 return 0; 604 default: 605 return ENODEV; 606 } 607 } 608 609 static void * 610 pcihost_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 611 int (*callback)(void *), void *arg, const char *xname) 612 { 613 struct pcihost_softc *sc = v; 614 const int flags = (ih & ARM_PCI_INTR_MPSAFE) ? FDT_INTR_MPSAFE : 0; 615 const u_int *specifier; 616 int ihandle; 617 618 if ((ih & (ARM_PCI_INTR_MSI | ARM_PCI_INTR_MSIX)) != 0) 619 return arm_pci_msi_intr_establish(&sc->sc_pc, ih, ipl, callback, arg, xname); 620 621 specifier = pcihost_find_intr(sc, ih & ARM_PCI_INTR_IRQ, &ihandle); 622 if (specifier == NULL) 623 return NULL; 624 625 return fdtbus_intr_establish_raw(ihandle, specifier, ipl, flags, callback, arg); 626 } 627 628 static void 629 pcihost_intr_disestablish(void *v, void *vih) 630 { 631 struct pcihost_softc *sc = v; 632 633 fdtbus_intr_disestablish(sc->sc_phandle, vih); 634 } 635 636 static int 637 pcihost_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 638 bus_space_handle_t *bshp) 639 { 640 struct pcih_bus_space * const pbs = t; 641 642 if ((pbs->flags & PCI_FLAGS_IO_OKAY) != 0) { 643 /* Force strongly ordered mapping for all I/O space */ 644 flag = _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED; 645 } 646 647 for (size_t i = 0; i < pbs->nranges; i++) { 648 const bus_addr_t rmin = pbs->ranges[i].bpci; 649 const bus_addr_t rmax = pbs->ranges[i].bpci - 1 + pbs->ranges[i].size; 650 if ((bpa >= rmin) && ((bpa - 1 + size) <= rmax)) { 651 return pbs->map(t, bpa - pbs->ranges[i].bpci + pbs->ranges[i].bbus, size, flag, bshp); 652 } 653 } 654 655 return ERANGE; 656 } 657
Indexes created Mon Sep 22 10:09:38 GMT 2025