pcihost_fdt.c revision 1.2.2.2
1 /* $NetBSD: pcihost_fdt.c,v 1.2.2.2 2018/09/30 01:45:38 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pcihost_fdt.c,v 1.2.2.2 2018/09/30 01:45:38 pgoyette Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/extent.h> 39 #include <sys/queue.h> 40 #include <sys/mutex.h> 41 #include <sys/kmem.h> 42 43 #include <machine/cpu.h> 44 45 #include <arm/cpufunc.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pciconf.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 #define IH_INDEX_MASK 0x0000ffff 54 #define IH_MPSAFE 0x80000000 55 56 #define PCIHOST_DEFAULT_BUS_MIN 0 57 #define PCIHOST_DEFAULT_BUS_MAX 255 58 59 #define PCIHOST_CACHELINE_SIZE arm_dcache_align 60 61 /* Physical address format bit definitions */ 62 #define PHYS_HI_RELO __BIT(31) 63 #define PHYS_HI_PREFETCH __BIT(30) 64 #define PHYS_HI_ALIASED __BIT(29) 65 #define PHYS_HI_SPACE __BITS(25,24) 66 #define PHYS_HI_SPACE_CFG 0 67 #define PHYS_HI_SPACE_IO 1 68 #define PHYS_HI_SPACE_MEM32 2 69 #define PHYS_HI_SPACE_MEM64 3 70 #define PHYS_HI_BUS __BITS(23,16) 71 #define PHYS_HI_DEVICE __BITS(15,11) 72 #define PHYS_HI_FUNCTION __BITS(10,8) 73 #define PHYS_HI_REGISTER __BITS(7,0) 74 75 enum pcihost_type { 76 PCIHOST_CAM = 1, 77 PCIHOST_ECAM, 78 }; 79 80 struct pcihost_softc { 81 device_t sc_dev; 82 bus_dma_tag_t sc_dmat; 83 bus_space_tag_t sc_bst; 84 bus_space_handle_t sc_bsh; 85 int sc_phandle; 86 87 enum pcihost_type sc_type; 88 89 u_int sc_bus_min; 90 u_int sc_bus_max; 91 92 struct arm32_pci_chipset sc_pc; 93 }; 94 95 static int pcihost_match(device_t, cfdata_t, void *); 96 static void pcihost_attach(device_t, device_t, void *); 97 98 static void pcihost_init(pci_chipset_tag_t, void *); 99 static int pcihost_config(struct pcihost_softc *); 100 101 static void pcihost_attach_hook(device_t, device_t, 102 struct pcibus_attach_args *); 103 static int pcihost_bus_maxdevs(void *, int); 104 static pcitag_t pcihost_make_tag(void *, int, int, int); 105 static void pcihost_decompose_tag(void *, pcitag_t, int *, int *, int *); 106 static pcireg_t pcihost_conf_read(void *, pcitag_t, int); 107 static void pcihost_conf_write(void *, pcitag_t, int, pcireg_t); 108 static int pcihost_conf_hook(void *, int, int, int, pcireg_t); 109 static void pcihost_conf_interrupt(void *, int, int, int, int, int *); 110 111 static int pcihost_intr_map(const struct pci_attach_args *, 112 pci_intr_handle_t *); 113 static const char *pcihost_intr_string(void *, pci_intr_handle_t, 114 char *, size_t); 115 const struct evcnt *pcihost_intr_evcnt(void *, pci_intr_handle_t); 116 static int pcihost_intr_setattr(void *, pci_intr_handle_t *, int, 117 uint64_t); 118 static void * pcihost_intr_establish(void *, pci_intr_handle_t, 119 int, int (*)(void *), void *); 120 static void pcihost_intr_disestablish(void *, void *); 121 122 CFATTACH_DECL_NEW(pcihost_fdt, sizeof(struct pcihost_softc), 123 pcihost_match, pcihost_attach, NULL, NULL); 124 125 static const struct of_compat_data compat_data[] = { 126 { "pci-host-cam-generic", PCIHOST_CAM }, 127 { "pci-host-ecam-generic", PCIHOST_ECAM }, 128 { NULL, 0 } 129 }; 130 131 static int 132 pcihost_match(device_t parent, cfdata_t cf, void *aux) 133 { 134 struct fdt_attach_args * const faa = aux; 135 136 return of_match_compat_data(faa->faa_phandle, compat_data); 137 } 138 139 static void 140 pcihost_attach(device_t parent, device_t self, void *aux) 141 { 142 struct pcihost_softc * const sc = device_private(self); 143 struct fdt_attach_args * const faa = aux; 144 struct pcibus_attach_args pba; 145 bus_addr_t cs_addr; 146 bus_size_t cs_size; 147 const u_int *data; 148 int error, len; 149 150 if (fdtbus_get_reg(faa->faa_phandle, 0, &cs_addr, &cs_size) != 0) { 151 aprint_error(": couldn't get registers\n"); 152 return; 153 } 154 155 sc->sc_dev = self; 156 sc->sc_dmat = faa->faa_dmat; 157 sc->sc_bst = faa->faa_bst; 158 sc->sc_phandle = faa->faa_phandle; 159 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 0, &sc->sc_bsh); 160 if (error) { 161 aprint_error(": couldn't map registers: %d\n", error); 162 return; 163 } 164 sc->sc_type = of_search_compatible(sc->sc_phandle, compat_data)->data; 165 166 aprint_naive("\n"); 167 aprint_normal(": Generic PCI host controller\n"); 168 169 if ((data = fdtbus_get_prop(sc->sc_phandle, "bus-range", &len)) != NULL) { 170 if (len != 8) { 171 aprint_error_dev(self, "malformed 'bus-range' property\n"); 172 return; 173 } 174 sc->sc_bus_min = be32toh(data[0]); 175 sc->sc_bus_max = be32toh(data[1]); 176 } else { 177 sc->sc_bus_min = PCIHOST_DEFAULT_BUS_MIN; 178 sc->sc_bus_max = PCIHOST_DEFAULT_BUS_MAX; 179 } 180 181 pcihost_init(&sc->sc_pc, sc); 182 183 if (pcihost_config(sc) != 0) 184 return; 185 186 memset(&pba, 0, sizeof(pba)); 187 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 188 PCI_FLAGS_MRM_OKAY | 189 PCI_FLAGS_MWI_OKAY | 190 PCI_FLAGS_MEM_OKAY | 191 PCI_FLAGS_IO_OKAY; 192 pba.pba_iot = sc->sc_bst; 193 pba.pba_memt = sc->sc_bst; 194 pba.pba_dmat = sc->sc_dmat; 195 #ifdef _PCI_HAVE_DMA64 196 pba.pba_dmat64 = sc->sc_dmat; 197 #endif 198 pba.pba_pc = &sc->sc_pc; 199 pba.pba_bus = 0; 200 201 config_found_ia(self, "pcibus", &pba, pcibusprint); 202 } 203 204 static void 205 pcihost_init(pci_chipset_tag_t pc, void *priv) 206 { 207 pc->pc_conf_v = priv; 208 pc->pc_attach_hook = pcihost_attach_hook; 209 pc->pc_bus_maxdevs = pcihost_bus_maxdevs; 210 pc->pc_make_tag = pcihost_make_tag; 211 pc->pc_decompose_tag = pcihost_decompose_tag; 212 pc->pc_conf_read = pcihost_conf_read; 213 pc->pc_conf_write = pcihost_conf_write; 214 pc->pc_conf_hook = pcihost_conf_hook; 215 pc->pc_conf_interrupt = pcihost_conf_interrupt; 216 217 pc->pc_intr_v = priv; 218 pc->pc_intr_map = pcihost_intr_map; 219 pc->pc_intr_string = pcihost_intr_string; 220 pc->pc_intr_evcnt = pcihost_intr_evcnt; 221 pc->pc_intr_setattr = pcihost_intr_setattr; 222 pc->pc_intr_establish = pcihost_intr_establish; 223 pc->pc_intr_disestablish = pcihost_intr_disestablish; 224 } 225 226 static int 227 pcihost_config(struct pcihost_softc *sc) 228 { 229 struct extent *ioext = NULL, *memext = NULL, *pmemext = NULL; 230 const u_int *ranges; 231 int error, len; 232 233 ranges = fdtbus_get_prop(sc->sc_phandle, "ranges", &len); 234 if (ranges == NULL) { 235 aprint_error_dev(sc->sc_dev, "missing 'ranges' property\n"); 236 return EINVAL; 237 } 238 239 /* 240 * Each entry in the ranges table contains: 241 * - bus address (3 cells) 242 * - cpu physical address (2 cells) 243 * - size (2 cells) 244 * Total size for each entry is 28 bytes (7 cells). 245 */ 246 while (len >= 28) { 247 const uint32_t phys_hi = be32dec(&ranges[0]); 248 const uint64_t cpu_phys = be64dec(&ranges[3]); 249 const uint64_t size = be64dec(&ranges[5]); 250 251 switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) { 252 case PHYS_HI_SPACE_IO: 253 if (ioext != NULL) { 254 aprint_error_dev(sc->sc_dev, "ignoring duplicate IO space range\n"); 255 continue; 256 } 257 ioext = extent_create("pciio", cpu_phys, cpu_phys + size - 1, NULL, 0, EX_NOWAIT); 258 aprint_verbose_dev(sc->sc_dev, 259 "I/O memory @ 0x%" PRIx64 " size 0x%" PRIx64 "\n", 260 cpu_phys, size); 261 break; 262 case PHYS_HI_SPACE_MEM32: 263 if ((phys_hi & PHYS_HI_PREFETCH) != 0) { 264 if (pmemext != NULL) { 265 aprint_error_dev(sc->sc_dev, "ignoring duplicate mem (prefetchable) range\n"); 266 continue; 267 } 268 pmemext = extent_create("pcipmem", cpu_phys, cpu_phys + size - 1, NULL, 0, EX_NOWAIT); 269 aprint_verbose_dev(sc->sc_dev, 270 "32-bit MMIO (prefetchable) @ 0x%" PRIx64 " size 0x%" PRIx64 "\n", 271 cpu_phys, size); 272 } else { 273 if (memext != NULL) { 274 aprint_error_dev(sc->sc_dev, "ignoring duplicate mem (non-prefetchable) range\n"); 275 continue; 276 } 277 memext = extent_create("pcimem", cpu_phys, cpu_phys + size - 1, NULL, 0, EX_NOWAIT); 278 aprint_verbose_dev(sc->sc_dev, 279 "32-bit MMIO (non-prefetchable) @ 0x%" PRIx64 " size 0x%" PRIx64 "\n", 280 cpu_phys, size); 281 } 282 break; 283 default: 284 break; 285 } 286 287 len -= 28; 288 ranges += 7; 289 } 290 291 error = pci_configure_bus(&sc->sc_pc, ioext, memext, pmemext, sc->sc_bus_min, PCIHOST_CACHELINE_SIZE); 292 293 if (ioext) 294 extent_destroy(ioext); 295 if (memext) 296 extent_destroy(memext); 297 if (pmemext) 298 extent_destroy(pmemext); 299 300 if (error) { 301 aprint_error_dev(sc->sc_dev, "configuration failed: %d\n", error); 302 return error; 303 } 304 305 return 0; 306 } 307 308 static void 309 pcihost_attach_hook(device_t parent, device_t self, 310 struct pcibus_attach_args *pba) 311 { 312 } 313 314 static int 315 pcihost_bus_maxdevs(void *v, int busno) 316 { 317 return 32; 318 } 319 320 static pcitag_t 321 pcihost_make_tag(void *v, int b, int d, int f) 322 { 323 return (b << 16) | (d << 11) | (f << 8); 324 } 325 326 static void 327 pcihost_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 328 { 329 if (bp) 330 *bp = (tag >> 16) & 0xff; 331 if (dp) 332 *dp = (tag >> 11) & 0x1f; 333 if (fp) 334 *fp = (tag >> 8) & 0x7; 335 } 336 337 static pcireg_t 338 pcihost_conf_read(void *v, pcitag_t tag, int offset) 339 { 340 struct pcihost_softc *sc = v; 341 int b, d, f; 342 u_int reg; 343 344 pcihost_decompose_tag(v, tag, &b, &d, &f); 345 346 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 347 return (pcireg_t) -1; 348 349 if (sc->sc_type == PCIHOST_CAM) { 350 if (offset & ~0xff) 351 return (pcireg_t) -1; 352 reg = (b << 16) | (d << 11) | (f << 8) | offset; 353 } else if (sc->sc_type == PCIHOST_ECAM) { 354 if (offset & ~0xfff) 355 return (pcireg_t) -1; 356 reg = (b << 20) | (d << 15) | (f << 12) | offset; 357 } else { 358 return (pcireg_t) -1; 359 } 360 361 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg); 362 } 363 364 static void 365 pcihost_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 366 { 367 struct pcihost_softc *sc = v; 368 int b, d, f; 369 u_int reg; 370 371 pcihost_decompose_tag(v, tag, &b, &d, &f); 372 373 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 374 return; 375 376 if (sc->sc_type == PCIHOST_CAM) { 377 if (offset & ~0xff) 378 return; 379 reg = (b << 16) | (d << 11) | (f << 8) | offset; 380 } else if (sc->sc_type == PCIHOST_ECAM) { 381 if (offset & ~0xfff) 382 return; 383 reg = (b << 20) | (d << 15) | (f << 12) | offset; 384 } else { 385 return; 386 } 387 388 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val); 389 } 390 391 static int 392 pcihost_conf_hook(void *v, int b, int d, int f, pcireg_t id) 393 { 394 return PCI_CONF_DEFAULT; 395 } 396 397 static void 398 pcihost_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep) 399 { 400 } 401 402 static int 403 pcihost_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 404 { 405 struct pcihost_softc *sc = pa->pa_pc->pc_intr_v; 406 u_int addr_cells, interrupt_cells; 407 const u_int *imap, *imask; 408 int imaplen, imasklen; 409 u_int match[4]; 410 int index; 411 412 if (pa->pa_intrpin == 0) 413 return EINVAL; 414 415 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 416 imask = fdtbus_get_prop(sc->sc_phandle, "interrupt-map-mask", &imasklen); 417 if (imap == NULL || imask == NULL || imasklen != 16) 418 return EINVAL; 419 420 /* Convert attach args to specifier */ 421 match[0] = htobe32( 422 __SHIFTIN(pa->pa_bus, PHYS_HI_BUS) | 423 __SHIFTIN(pa->pa_device, PHYS_HI_DEVICE) | 424 __SHIFTIN(pa->pa_function, PHYS_HI_FUNCTION) 425 ) & imask[0]; 426 match[1] = htobe32(0) & imask[1]; 427 match[2] = htobe32(0) & imask[2]; 428 match[3] = htobe32(pa->pa_intrpin) & imask[3]; 429 430 index = 0; 431 while (imaplen >= 20) { 432 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 433 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 434 addr_cells = 2; 435 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 436 interrupt_cells = 0; 437 if (imaplen < (addr_cells + interrupt_cells) * 4) 438 return ENXIO; 439 440 if ((imap[0] & imask[0]) == match[0] && 441 (imap[1] & imask[1]) == match[1] && 442 (imap[2] & imask[2]) == match[2] && 443 (imap[3] & imask[3]) == match[3]) { 444 *ih = index; 445 return 0; 446 } 447 448 imap += (5 + addr_cells + interrupt_cells); 449 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 450 index++; 451 } 452 453 return EINVAL; 454 } 455 456 static const u_int * 457 pcihost_find_intr(struct pcihost_softc *sc, pci_intr_handle_t ih, int *pihandle) 458 { 459 u_int addr_cells, interrupt_cells; 460 int imaplen, index; 461 const u_int *imap; 462 463 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 464 KASSERT(imap != NULL); 465 466 index = 0; 467 while (imaplen >= 20) { 468 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 469 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 470 addr_cells = 2; 471 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 472 interrupt_cells = 0; 473 if (imaplen < (addr_cells + interrupt_cells) * 4) 474 return NULL; 475 476 if (index == ih) { 477 *pihandle = map_ihandle; 478 return imap + 5 + addr_cells; 479 } 480 481 imap += (5 + addr_cells + interrupt_cells); 482 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 483 index++; 484 } 485 486 return NULL; 487 } 488 489 static const char * 490 pcihost_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 491 { 492 struct pcihost_softc *sc = v; 493 const u_int *specifier; 494 int ihandle; 495 496 specifier = pcihost_find_intr(sc, ih & IH_INDEX_MASK, &ihandle); 497 if (specifier == NULL) 498 return NULL; 499 500 if (!fdtbus_intr_str_raw(ihandle, specifier, buf, len)) 501 return NULL; 502 503 return buf; 504 } 505 506 const struct evcnt * 507 pcihost_intr_evcnt(void *v, pci_intr_handle_t ih) 508 { 509 return NULL; 510 } 511 512 static int 513 pcihost_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 514 { 515 switch (attr) { 516 case PCI_INTR_MPSAFE: 517 if (data) 518 *ih |= IH_MPSAFE; 519 else 520 *ih &= ~IH_MPSAFE; 521 return 0; 522 default: 523 return ENODEV; 524 } 525 } 526 527 static void * 528 pcihost_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 529 int (*callback)(void *), void *arg) 530 { 531 struct pcihost_softc *sc = v; 532 const int flags = (ih & IH_MPSAFE) ? FDT_INTR_MPSAFE : 0; 533 const u_int *specifier; 534 int ihandle; 535 536 specifier = pcihost_find_intr(sc, ih & IH_INDEX_MASK, &ihandle); 537 if (specifier == NULL) 538 return NULL; 539 540 return fdtbus_intr_establish_raw(ihandle, specifier, ipl, flags, callback, arg); 541 } 542 543 static void 544 pcihost_intr_disestablish(void *v, void *vih) 545 { 546 struct pcihost_softc *sc = v; 547 548 fdtbus_intr_disestablish(sc->sc_phandle, vih); 549 } 550
Indexes created Thu Oct 02 14:10:14 GMT 2025