pcihost_fdt.c revision 1.26
1 /* $NetBSD: pcihost_fdt.c,v 1.26 2021/08/07 16:18:43 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pcihost_fdt.c,v 1.26 2021/08/07 16:18:43 thorpej Exp $"); 31 32 #include <sys/param.h> 33 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 #include <sys/lwp.h> 40 #include <sys/mutex.h> 41 #include <sys/queue.h> 42 #include <sys/systm.h> 43 44 #include <machine/cpu.h> 45 46 #include <arm/cpufunc.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pciconf.h> 51 52 #include <dev/fdt/fdtvar.h> 53 54 #include <arm/pci/pci_msi_machdep.h> 55 #include <arm/fdt/pcihost_fdtvar.h> 56 57 #define PCIHOST_DEFAULT_BUS_MIN 0 58 #define PCIHOST_DEFAULT_BUS_MAX 255 59 60 #define PCIHOST_CACHELINE_SIZE arm_dcache_align 61 62 int pcihost_segment = 0; 63 64 static int pcihost_match(device_t, cfdata_t, void *); 65 static void pcihost_attach(device_t, device_t, void *); 66 67 static int pcihost_config(struct pcihost_softc *); 68 69 static void pcihost_attach_hook(device_t, device_t, 70 struct pcibus_attach_args *); 71 static int pcihost_bus_maxdevs(void *, int); 72 static pcitag_t pcihost_make_tag(void *, int, int, int); 73 static void pcihost_decompose_tag(void *, pcitag_t, int *, int *, int *); 74 static u_int pcihost_get_segment(void *); 75 static pcireg_t pcihost_conf_read(void *, pcitag_t, int); 76 static void pcihost_conf_write(void *, pcitag_t, int, pcireg_t); 77 static int pcihost_conf_hook(void *, int, int, int, pcireg_t); 78 static void pcihost_conf_interrupt(void *, int, int, int, int, int *); 79 80 static int pcihost_intr_map(const struct pci_attach_args *, 81 pci_intr_handle_t *); 82 static const char *pcihost_intr_string(void *, pci_intr_handle_t, 83 char *, size_t); 84 static const struct evcnt *pcihost_intr_evcnt(void *, pci_intr_handle_t); 85 static int pcihost_intr_setattr(void *, pci_intr_handle_t *, int, 86 uint64_t); 87 static void * pcihost_intr_establish(void *, pci_intr_handle_t, 88 int, int (*)(void *), void *, 89 const char *); 90 static void pcihost_intr_disestablish(void *, void *); 91 92 static int pcihost_bus_space_map(void *, bus_addr_t, bus_size_t, 93 int, bus_space_handle_t *); 94 95 CFATTACH_DECL_NEW(pcihost_fdt, sizeof(struct pcihost_softc), 96 pcihost_match, pcihost_attach, NULL, NULL); 97 98 static const struct device_compatible_entry compat_data[] = { 99 { .compat = "pci-host-cam-generic", .value = PCIHOST_CAM }, 100 { .compat = "pci-host-ecam-generic", .value = PCIHOST_ECAM }, 101 DEVICE_COMPAT_EOL 102 }; 103 104 static int 105 pcihost_match(device_t parent, cfdata_t cf, void *aux) 106 { 107 struct fdt_attach_args * const faa = aux; 108 109 return of_compatible_match(faa->faa_phandle, compat_data); 110 } 111 112 static void 113 pcihost_attach(device_t parent, device_t self, void *aux) 114 { 115 struct pcihost_softc * const sc = device_private(self); 116 struct fdt_attach_args * const faa = aux; 117 bus_addr_t cs_addr; 118 bus_size_t cs_size; 119 int error; 120 121 if (fdtbus_get_reg(faa->faa_phandle, 0, &cs_addr, &cs_size) != 0) { 122 aprint_error(": couldn't get registers\n"); 123 return; 124 } 125 126 sc->sc_dev = self; 127 sc->sc_dmat = faa->faa_dmat; 128 sc->sc_bst = faa->faa_bst; 129 sc->sc_phandle = faa->faa_phandle; 130 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 131 _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED, &sc->sc_bsh); 132 if (error) { 133 aprint_error(": couldn't map registers: %d\n", error); 134 return; 135 } 136 sc->sc_type = of_compatible_lookup(sc->sc_phandle, compat_data)->value; 137 138 #ifdef __HAVE_PCI_MSI_MSIX 139 if (sc->sc_type == PCIHOST_ECAM) { 140 sc->sc_pci_flags |= PCI_FLAGS_MSI_OKAY; 141 sc->sc_pci_flags |= PCI_FLAGS_MSIX_OKAY; 142 } 143 #endif 144 145 aprint_naive("\n"); 146 aprint_normal(": Generic PCI host controller\n"); 147 148 pcihost_init(&sc->sc_pc, sc); 149 pcihost_init2(sc); 150 } 151 152 void 153 pcihost_init2(struct pcihost_softc *sc) 154 { 155 struct pcibus_attach_args pba; 156 const u_int *data; 157 int len; 158 159 if ((data = fdtbus_get_prop(sc->sc_phandle, "bus-range", &len)) != NULL) { 160 if (len != 8) { 161 aprint_error_dev(sc->sc_dev, "malformed 'bus-range' property\n"); 162 return; 163 } 164 sc->sc_bus_min = be32toh(data[0]); 165 sc->sc_bus_max = be32toh(data[1]); 166 } else { 167 sc->sc_bus_min = PCIHOST_DEFAULT_BUS_MIN; 168 sc->sc_bus_max = PCIHOST_DEFAULT_BUS_MAX; 169 } 170 171 /* 172 * Assign a fixed PCI segment ("domain") number. If the property is not 173 * present, assign one. The binding spec says if this property is used to 174 * assign static segment numbers, all host bridges should have segments 175 * astatic assigned to prevent overlaps. 176 */ 177 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-domain", &sc->sc_seg)) 178 sc->sc_seg = pcihost_segment++; 179 180 if (pcihost_config(sc) != 0) 181 return; 182 183 memset(&pba, 0, sizeof(pba)); 184 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 185 PCI_FLAGS_MRM_OKAY | 186 PCI_FLAGS_MWI_OKAY | 187 sc->sc_pci_flags; 188 pba.pba_iot = &sc->sc_io.bst; 189 pba.pba_memt = &sc->sc_mem.bst; 190 pba.pba_dmat = sc->sc_dmat; 191 #ifdef _PCI_HAVE_DMA64 192 pba.pba_dmat64 = sc->sc_dmat; 193 #endif 194 pba.pba_pc = &sc->sc_pc; 195 pba.pba_bus = sc->sc_bus_min; 196 197 config_found(sc->sc_dev, &pba, pcibusprint, 198 CFARGS(.devhandle = device_handle(sc->sc_dev))); 199 } 200 201 void 202 pcihost_init(pci_chipset_tag_t pc, void *priv) 203 { 204 pc->pc_conf_v = priv; 205 pc->pc_attach_hook = pcihost_attach_hook; 206 pc->pc_bus_maxdevs = pcihost_bus_maxdevs; 207 pc->pc_make_tag = pcihost_make_tag; 208 pc->pc_decompose_tag = pcihost_decompose_tag; 209 pc->pc_get_segment = pcihost_get_segment; 210 pc->pc_conf_read = pcihost_conf_read; 211 pc->pc_conf_write = pcihost_conf_write; 212 pc->pc_conf_hook = pcihost_conf_hook; 213 pc->pc_conf_interrupt = pcihost_conf_interrupt; 214 215 pc->pc_intr_v = priv; 216 pc->pc_intr_map = pcihost_intr_map; 217 pc->pc_intr_string = pcihost_intr_string; 218 pc->pc_intr_evcnt = pcihost_intr_evcnt; 219 pc->pc_intr_setattr = pcihost_intr_setattr; 220 pc->pc_intr_establish = pcihost_intr_establish; 221 pc->pc_intr_disestablish = pcihost_intr_disestablish; 222 } 223 224 static int 225 pcihost_config(struct pcihost_softc *sc) 226 { 227 const u_int *ranges; 228 u_int probe_only; 229 int error, len, type; 230 bool swap; 231 232 struct pcih_bus_space * const pibs = &sc->sc_io; 233 pibs->bst = *sc->sc_bst; 234 pibs->bst.bs_cookie = pibs; 235 pibs->map = pibs->bst.bs_map; 236 pibs->flags = PCI_FLAGS_IO_OKAY; 237 pibs->bst.bs_map = pcihost_bus_space_map; 238 239 struct pcih_bus_space * const pmbs = &sc->sc_mem; 240 pmbs->bst = *sc->sc_bst; 241 pmbs->bst.bs_cookie = pmbs; 242 pmbs->map = pmbs->bst.bs_map; 243 pmbs->flags = PCI_FLAGS_MEM_OKAY; 244 pmbs->bst.bs_map = pcihost_bus_space_map; 245 246 /* 247 * If this flag is set, skip configuration of the PCI bus and use existing config. 248 */ 249 const int chosen = OF_finddevice("/chosen"); 250 if (chosen <= 0 || of_getprop_uint32(chosen, "linux,pci-probe-only", &probe_only)) 251 probe_only = 0; 252 if (probe_only) 253 return 0; 254 255 if (sc->sc_pci_ranges != NULL) { 256 ranges = sc->sc_pci_ranges; 257 len = sc->sc_pci_ranges_cells * 4; 258 swap = false; 259 } else { 260 ranges = fdtbus_get_prop(sc->sc_phandle, "ranges", &len); 261 if (ranges == NULL) { 262 aprint_error_dev(sc->sc_dev, "missing 'ranges' property\n"); 263 return EINVAL; 264 } 265 swap = true; 266 } 267 268 struct pciconf_resources *pcires = pciconf_resource_init(); 269 270 /* 271 * Each entry in the ranges table contains: 272 * - bus address (3 cells) 273 * - cpu physical address (2 cells) 274 * - size (2 cells) 275 * Total size for each entry is 28 bytes (7 cells). 276 */ 277 while (len >= 28) { 278 #define DECODE32(x,o) (swap ? be32dec(&(x)[o]) : (x)[o]) 279 #define DECODE64(x,o) (swap ? be64dec(&(x)[o]) : (((uint64_t)((x)[(o)+0]) << 32) + (x)[(o)+1])) 280 const uint32_t phys_hi = DECODE32(ranges, 0); 281 uint64_t bus_phys = DECODE64(ranges, 1); 282 const uint64_t cpu_phys = DECODE64(ranges, 3); 283 uint64_t size = DECODE64(ranges, 5); 284 #undef DECODE32 285 #undef DECODE64 286 287 len -= 28; 288 ranges += 7; 289 290 const bool is64 = (__SHIFTOUT(phys_hi, PHYS_HI_SPACE) == 291 PHYS_HI_SPACE_MEM64) ? true : false; 292 switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) { 293 case PHYS_HI_SPACE_IO: 294 if (pibs->nranges + 1 >= __arraycount(pibs->ranges)) { 295 aprint_error_dev(sc->sc_dev, "too many IO ranges\n"); 296 continue; 297 } 298 pibs->ranges[pibs->nranges].bpci = bus_phys; 299 pibs->ranges[pibs->nranges].bbus = cpu_phys; 300 pibs->ranges[pibs->nranges].size = size; 301 ++pibs->nranges; 302 aprint_verbose_dev(sc->sc_dev, 303 "IO: 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 304 bus_phys, size, cpu_phys); 305 /* 306 * Reserve a PC-like legacy IO ports range, perhaps 307 * for access to VGA registers. 308 */ 309 if (bus_phys == 0 && size >= 0x10000) { 310 bus_phys += 0x1000; 311 size -= 0x1000; 312 } 313 error = pciconf_resource_add(pcires, 314 PCICONF_RESOURCE_IO, bus_phys, size); 315 if (error == 0) 316 sc->sc_pci_flags |= PCI_FLAGS_IO_OKAY; 317 break; 318 case PHYS_HI_SPACE_MEM64: 319 /* FALLTHROUGH */ 320 case PHYS_HI_SPACE_MEM32: 321 if (pmbs->nranges + 1 >= __arraycount(pmbs->ranges)) { 322 aprint_error_dev(sc->sc_dev, "too many mem ranges\n"); 323 continue; 324 } 325 /* both pmem and mem spaces are in the same tag */ 326 pmbs->ranges[pmbs->nranges].bpci = bus_phys; 327 pmbs->ranges[pmbs->nranges].bbus = cpu_phys; 328 pmbs->ranges[pmbs->nranges].size = size; 329 ++pmbs->nranges; 330 if ((phys_hi & PHYS_HI_PREFETCH) != 0 || 331 __SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64) { 332 type = PCICONF_RESOURCE_PREFETCHABLE_MEM; 333 aprint_verbose_dev(sc->sc_dev, 334 "MMIO (%d-bit prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 335 is64 ? 64 : 32, bus_phys, size, cpu_phys); 336 } else { 337 type = PCICONF_RESOURCE_MEM; 338 aprint_verbose_dev(sc->sc_dev, 339 "MMIO (%d-bit non-prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 340 is64 ? 64 : 32, bus_phys, size, cpu_phys); 341 } 342 error = pciconf_resource_add(pcires, type, bus_phys, 343 size); 344 if (error == 0) 345 sc->sc_pci_flags |= PCI_FLAGS_MEM_OKAY; 346 break; 347 default: 348 break; 349 } 350 } 351 352 error = pci_configure_bus(&sc->sc_pc, pcires, sc->sc_bus_min, 353 PCIHOST_CACHELINE_SIZE); 354 355 pciconf_resource_fini(pcires); 356 357 if (error) { 358 aprint_error_dev(sc->sc_dev, "configuration failed: %d\n", error); 359 return error; 360 } 361 362 return 0; 363 } 364 365 static void 366 pcihost_attach_hook(device_t parent, device_t self, 367 struct pcibus_attach_args *pba) 368 { 369 } 370 371 static int 372 pcihost_bus_maxdevs(void *v, int busno) 373 { 374 return 32; 375 } 376 377 static pcitag_t 378 pcihost_make_tag(void *v, int b, int d, int f) 379 { 380 return (b << 16) | (d << 11) | (f << 8); 381 } 382 383 static void 384 pcihost_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 385 { 386 if (bp) 387 *bp = (tag >> 16) & 0xff; 388 if (dp) 389 *dp = (tag >> 11) & 0x1f; 390 if (fp) 391 *fp = (tag >> 8) & 0x7; 392 } 393 394 static u_int 395 pcihost_get_segment(void *v) 396 { 397 struct pcihost_softc *sc = v; 398 399 return sc->sc_seg; 400 } 401 402 static pcireg_t 403 pcihost_conf_read(void *v, pcitag_t tag, int offset) 404 { 405 struct pcihost_softc *sc = v; 406 int b, d, f; 407 u_int reg; 408 409 pcihost_decompose_tag(v, tag, &b, &d, &f); 410 411 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 412 return (pcireg_t) -1; 413 414 if (sc->sc_type == PCIHOST_CAM) { 415 if (offset & ~0xff) 416 return (pcireg_t) -1; 417 reg = (b << 16) | (d << 11) | (f << 8) | offset; 418 } else if (sc->sc_type == PCIHOST_ECAM) { 419 if (offset & ~0xfff) 420 return (pcireg_t) -1; 421 reg = (b << 20) | (d << 15) | (f << 12) | offset; 422 } else { 423 return (pcireg_t) -1; 424 } 425 426 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg); 427 } 428 429 static void 430 pcihost_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 431 { 432 struct pcihost_softc *sc = v; 433 int b, d, f; 434 u_int reg; 435 436 pcihost_decompose_tag(v, tag, &b, &d, &f); 437 438 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 439 return; 440 441 if (sc->sc_type == PCIHOST_CAM) { 442 if (offset & ~0xff) 443 return; 444 reg = (b << 16) | (d << 11) | (f << 8) | offset; 445 } else if (sc->sc_type == PCIHOST_ECAM) { 446 if (offset & ~0xfff) 447 return; 448 reg = (b << 20) | (d << 15) | (f << 12) | offset; 449 } else { 450 return; 451 } 452 453 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val); 454 } 455 456 static int 457 pcihost_conf_hook(void *v, int b, int d, int f, pcireg_t id) 458 { 459 return PCI_CONF_DEFAULT; 460 } 461 462 static void 463 pcihost_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep) 464 { 465 } 466 467 static int 468 pcihost_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 469 { 470 struct pcihost_softc *sc = pa->pa_pc->pc_intr_v; 471 u_int addr_cells, interrupt_cells; 472 const u_int *imap, *imask; 473 int imaplen, imasklen; 474 u_int match[4]; 475 int index; 476 477 if (pa->pa_intrpin == 0) 478 return EINVAL; 479 480 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 481 imask = fdtbus_get_prop(sc->sc_phandle, "interrupt-map-mask", &imasklen); 482 if (imap == NULL || imask == NULL || imasklen != 16) 483 return EINVAL; 484 485 /* Convert attach args to specifier */ 486 match[0] = htobe32( 487 __SHIFTIN(pa->pa_bus, PHYS_HI_BUS) | 488 __SHIFTIN(pa->pa_device, PHYS_HI_DEVICE) | 489 __SHIFTIN(pa->pa_function, PHYS_HI_FUNCTION) 490 ) & imask[0]; 491 match[1] = htobe32(0) & imask[1]; 492 match[2] = htobe32(0) & imask[2]; 493 match[3] = htobe32(pa->pa_intrpin) & imask[3]; 494 495 index = 0; 496 while (imaplen >= 20) { 497 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 498 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 499 addr_cells = 2; 500 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 501 interrupt_cells = 0; 502 if (imaplen < (addr_cells + interrupt_cells) * 4) 503 return ENXIO; 504 505 if ((imap[0] & imask[0]) == match[0] && 506 (imap[1] & imask[1]) == match[1] && 507 (imap[2] & imask[2]) == match[2] && 508 (imap[3] & imask[3]) == match[3]) { 509 *ih = index; 510 return 0; 511 } 512 513 imap += (5 + addr_cells + interrupt_cells); 514 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 515 index++; 516 } 517 518 return EINVAL; 519 } 520 521 static const u_int * 522 pcihost_find_intr(struct pcihost_softc *sc, pci_intr_handle_t ih, int *pihandle) 523 { 524 u_int addr_cells, interrupt_cells; 525 int imaplen, index; 526 const u_int *imap; 527 528 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 529 KASSERT(imap != NULL); 530 531 index = 0; 532 while (imaplen >= 20) { 533 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 534 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 535 addr_cells = 2; 536 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 537 interrupt_cells = 0; 538 if (imaplen < (addr_cells + interrupt_cells) * 4) 539 return NULL; 540 541 if (index == ih) { 542 *pihandle = map_ihandle; 543 return imap + 5 + addr_cells; 544 } 545 546 imap += (5 + addr_cells + interrupt_cells); 547 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 548 index++; 549 } 550 551 return NULL; 552 } 553 554 static const char * 555 pcihost_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 556 { 557 const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); 558 const int vec = __SHIFTOUT(ih, ARM_PCI_INTR_MSI_VEC); 559 struct pcihost_softc *sc = v; 560 const u_int *specifier; 561 int ihandle; 562 563 if (ih & ARM_PCI_INTR_MSIX) { 564 snprintf(buf, len, "irq %d (MSI-X vec %d)", irq, vec); 565 } else if (ih & ARM_PCI_INTR_MSI) { 566 snprintf(buf, len, "irq %d (MSI vec %d)", irq, vec); 567 } else { 568 specifier = pcihost_find_intr(sc, ih & ARM_PCI_INTR_IRQ, &ihandle); 569 if (specifier == NULL) 570 return NULL; 571 572 if (!fdtbus_intr_str_raw(ihandle, specifier, buf, len)) 573 return NULL; 574 } 575 576 return buf; 577 } 578 579 const struct evcnt * 580 pcihost_intr_evcnt(void *v, pci_intr_handle_t ih) 581 { 582 return NULL; 583 } 584 585 static int 586 pcihost_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 587 { 588 switch (attr) { 589 case PCI_INTR_MPSAFE: 590 if (data) 591 *ih |= ARM_PCI_INTR_MPSAFE; 592 else 593 *ih &= ~ARM_PCI_INTR_MPSAFE; 594 return 0; 595 default: 596 return ENODEV; 597 } 598 } 599 600 static void * 601 pcihost_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 602 int (*callback)(void *), void *arg, const char *xname) 603 { 604 struct pcihost_softc *sc = v; 605 const int flags = (ih & ARM_PCI_INTR_MPSAFE) ? FDT_INTR_MPSAFE : 0; 606 const u_int *specifier; 607 int ihandle; 608 609 if ((ih & (ARM_PCI_INTR_MSI | ARM_PCI_INTR_MSIX)) != 0) 610 return arm_pci_msi_intr_establish(&sc->sc_pc, ih, ipl, callback, arg, xname); 611 612 specifier = pcihost_find_intr(sc, ih & ARM_PCI_INTR_IRQ, &ihandle); 613 if (specifier == NULL) 614 return NULL; 615 616 return fdtbus_intr_establish_raw(ihandle, specifier, ipl, flags, 617 callback, arg, xname); 618 } 619 620 static void 621 pcihost_intr_disestablish(void *v, void *vih) 622 { 623 struct pcihost_softc *sc = v; 624 625 fdtbus_intr_disestablish(sc->sc_phandle, vih); 626 } 627 628 static int 629 pcihost_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 630 bus_space_handle_t *bshp) 631 { 632 struct pcih_bus_space * const pbs = t; 633 634 if ((pbs->flags & PCI_FLAGS_IO_OKAY) != 0) { 635 /* Force strongly ordered mapping for all I/O space */ 636 flag = _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED; 637 } 638 639 for (size_t i = 0; i < pbs->nranges; i++) { 640 const bus_addr_t rmin = pbs->ranges[i].bpci; 641 const bus_addr_t rmax = pbs->ranges[i].bpci - 1 + pbs->ranges[i].size; 642 if ((bpa >= rmin) && ((bpa - 1 + size) <= rmax)) { 643 return pbs->map(t, bpa - pbs->ranges[i].bpci + pbs->ranges[i].bbus, size, flag, bshp); 644 } 645 } 646 647 return ERANGE; 648 } 649
Indexes created Wed Sep 24 02:09:48 GMT 2025