pcihost_fdt.c revision 1.27
1 /* $NetBSD: pcihost_fdt.c,v 1.27 2021/09/06 14:03:17 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pcihost_fdt.c,v 1.27 2021/09/06 14:03:17 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 #include <sys/lwp.h> 40 #include <sys/mutex.h> 41 #include <sys/queue.h> 42 #include <sys/systm.h> 43 44 #include <machine/cpu.h> 45 46 #include <arm/cpufunc.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pciconf.h> 51 52 #include <dev/fdt/fdtvar.h> 53 54 #include <arm/pci/pci_msi_machdep.h> 55 #include <arm/fdt/pcihost_fdtvar.h> 56 57 #define PCIHOST_DEFAULT_BUS_MIN 0 58 #define PCIHOST_DEFAULT_BUS_MAX 255 59 60 #define PCIHOST_CACHELINE_SIZE arm_dcache_align 61 62 int pcihost_segment = 0; 63 64 static int pcihost_match(device_t, cfdata_t, void *); 65 static void pcihost_attach(device_t, device_t, void *); 66 67 static int pcihost_config(struct pcihost_softc *); 68 69 static void pcihost_attach_hook(device_t, device_t, 70 struct pcibus_attach_args *); 71 static int pcihost_bus_maxdevs(void *, int); 72 static pcitag_t pcihost_make_tag(void *, int, int, int); 73 static void pcihost_decompose_tag(void *, pcitag_t, int *, int *, int *); 74 static u_int pcihost_get_segment(void *); 75 static pcireg_t pcihost_conf_read(void *, pcitag_t, int); 76 static void pcihost_conf_write(void *, pcitag_t, int, pcireg_t); 77 static int pcihost_conf_hook(void *, int, int, int, pcireg_t); 78 static void pcihost_conf_interrupt(void *, int, int, int, int, int *); 79 80 static int pcihost_intr_map(const struct pci_attach_args *, 81 pci_intr_handle_t *); 82 static const char *pcihost_intr_string(void *, pci_intr_handle_t, 83 char *, size_t); 84 static const struct evcnt *pcihost_intr_evcnt(void *, pci_intr_handle_t); 85 static int pcihost_intr_setattr(void *, pci_intr_handle_t *, int, 86 uint64_t); 87 static void * pcihost_intr_establish(void *, pci_intr_handle_t, 88 int, int (*)(void *), void *, 89 const char *); 90 static void pcihost_intr_disestablish(void *, void *); 91 92 static int pcihost_bus_space_map(void *, bus_addr_t, bus_size_t, 93 int, bus_space_handle_t *); 94 95 CFATTACH_DECL_NEW(pcihost_fdt, sizeof(struct pcihost_softc), 96 pcihost_match, pcihost_attach, NULL, NULL); 97 98 static const struct device_compatible_entry compat_data[] = { 99 { .compat = "pci-host-cam-generic", .value = PCIHOST_CAM }, 100 { .compat = "pci-host-ecam-generic", .value = PCIHOST_ECAM }, 101 DEVICE_COMPAT_EOL 102 }; 103 104 static int 105 pcihost_match(device_t parent, cfdata_t cf, void *aux) 106 { 107 struct fdt_attach_args * const faa = aux; 108 109 return of_compatible_match(faa->faa_phandle, compat_data); 110 } 111 112 static void 113 pcihost_attach(device_t parent, device_t self, void *aux) 114 { 115 struct pcihost_softc * const sc = device_private(self); 116 struct fdt_attach_args * const faa = aux; 117 bus_addr_t cs_addr; 118 bus_size_t cs_size; 119 int error; 120 121 if (fdtbus_get_reg(faa->faa_phandle, 0, &cs_addr, &cs_size) != 0) { 122 aprint_error(": couldn't get registers\n"); 123 return; 124 } 125 126 sc->sc_dev = self; 127 sc->sc_dmat = faa->faa_dmat; 128 sc->sc_bst = faa->faa_bst; 129 sc->sc_pci_bst = faa->faa_bst; 130 sc->sc_phandle = faa->faa_phandle; 131 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 132 _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED, &sc->sc_bsh); 133 if (error) { 134 aprint_error(": couldn't map registers: %d\n", error); 135 return; 136 } 137 sc->sc_type = of_compatible_lookup(sc->sc_phandle, compat_data)->value; 138 139 #ifdef __HAVE_PCI_MSI_MSIX 140 if (sc->sc_type == PCIHOST_ECAM) { 141 sc->sc_pci_flags |= PCI_FLAGS_MSI_OKAY; 142 sc->sc_pci_flags |= PCI_FLAGS_MSIX_OKAY; 143 } 144 #endif 145 146 aprint_naive("\n"); 147 aprint_normal(": Generic PCI host controller\n"); 148 149 pcihost_init(&sc->sc_pc, sc); 150 pcihost_init2(sc); 151 } 152 153 void 154 pcihost_init2(struct pcihost_softc *sc) 155 { 156 struct pcibus_attach_args pba; 157 const u_int *data; 158 int len; 159 160 if ((data = fdtbus_get_prop(sc->sc_phandle, "bus-range", &len)) != NULL) { 161 if (len != 8) { 162 aprint_error_dev(sc->sc_dev, "malformed 'bus-range' property\n"); 163 return; 164 } 165 sc->sc_bus_min = be32toh(data[0]); 166 sc->sc_bus_max = be32toh(data[1]); 167 } else { 168 sc->sc_bus_min = PCIHOST_DEFAULT_BUS_MIN; 169 sc->sc_bus_max = PCIHOST_DEFAULT_BUS_MAX; 170 } 171 172 /* 173 * Assign a fixed PCI segment ("domain") number. If the property is not 174 * present, assign one. The binding spec says if this property is used to 175 * assign static segment numbers, all host bridges should have segments 176 * astatic assigned to prevent overlaps. 177 */ 178 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-domain", &sc->sc_seg)) 179 sc->sc_seg = pcihost_segment++; 180 181 if (pcihost_config(sc) != 0) 182 return; 183 184 memset(&pba, 0, sizeof(pba)); 185 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 186 PCI_FLAGS_MRM_OKAY | 187 PCI_FLAGS_MWI_OKAY | 188 sc->sc_pci_flags; 189 pba.pba_iot = &sc->sc_io.bst; 190 pba.pba_memt = &sc->sc_mem.bst; 191 pba.pba_dmat = sc->sc_dmat; 192 #ifdef _PCI_HAVE_DMA64 193 pba.pba_dmat64 = sc->sc_dmat; 194 #endif 195 pba.pba_pc = &sc->sc_pc; 196 pba.pba_bus = sc->sc_bus_min; 197 198 config_found(sc->sc_dev, &pba, pcibusprint, 199 CFARGS(.devhandle = device_handle(sc->sc_dev))); 200 } 201 202 void 203 pcihost_init(pci_chipset_tag_t pc, void *priv) 204 { 205 pc->pc_conf_v = priv; 206 pc->pc_attach_hook = pcihost_attach_hook; 207 pc->pc_bus_maxdevs = pcihost_bus_maxdevs; 208 pc->pc_make_tag = pcihost_make_tag; 209 pc->pc_decompose_tag = pcihost_decompose_tag; 210 pc->pc_get_segment = pcihost_get_segment; 211 pc->pc_conf_read = pcihost_conf_read; 212 pc->pc_conf_write = pcihost_conf_write; 213 pc->pc_conf_hook = pcihost_conf_hook; 214 pc->pc_conf_interrupt = pcihost_conf_interrupt; 215 216 pc->pc_intr_v = priv; 217 pc->pc_intr_map = pcihost_intr_map; 218 pc->pc_intr_string = pcihost_intr_string; 219 pc->pc_intr_evcnt = pcihost_intr_evcnt; 220 pc->pc_intr_setattr = pcihost_intr_setattr; 221 pc->pc_intr_establish = pcihost_intr_establish; 222 pc->pc_intr_disestablish = pcihost_intr_disestablish; 223 } 224 225 static int 226 pcihost_config(struct pcihost_softc *sc) 227 { 228 const u_int *ranges; 229 u_int probe_only; 230 int error, len, type; 231 bool swap; 232 233 struct pcih_bus_space * const pibs = &sc->sc_io; 234 pibs->bst = *sc->sc_pci_bst; 235 pibs->bst.bs_cookie = pibs; 236 pibs->map = pibs->bst.bs_map; 237 pibs->flags = PCI_FLAGS_IO_OKAY; 238 pibs->bst.bs_map = pcihost_bus_space_map; 239 240 struct pcih_bus_space * const pmbs = &sc->sc_mem; 241 pmbs->bst = *sc->sc_pci_bst; 242 pmbs->bst.bs_cookie = pmbs; 243 pmbs->map = pmbs->bst.bs_map; 244 pmbs->flags = PCI_FLAGS_MEM_OKAY; 245 pmbs->bst.bs_map = pcihost_bus_space_map; 246 247 /* 248 * If this flag is set, skip configuration of the PCI bus and use existing config. 249 */ 250 const int chosen = OF_finddevice("/chosen"); 251 if (chosen <= 0 || of_getprop_uint32(chosen, "linux,pci-probe-only", &probe_only)) 252 probe_only = 0; 253 if (probe_only) 254 return 0; 255 256 if (sc->sc_pci_ranges != NULL) { 257 ranges = sc->sc_pci_ranges; 258 len = sc->sc_pci_ranges_cells * 4; 259 swap = false; 260 } else { 261 ranges = fdtbus_get_prop(sc->sc_phandle, "ranges", &len); 262 if (ranges == NULL) { 263 aprint_error_dev(sc->sc_dev, "missing 'ranges' property\n"); 264 return EINVAL; 265 } 266 swap = true; 267 } 268 269 struct pciconf_resources *pcires = pciconf_resource_init(); 270 271 /* 272 * Each entry in the ranges table contains: 273 * - bus address (3 cells) 274 * - cpu physical address (2 cells) 275 * - size (2 cells) 276 * Total size for each entry is 28 bytes (7 cells). 277 */ 278 while (len >= 28) { 279 #define DECODE32(x,o) (swap ? be32dec(&(x)[o]) : (x)[o]) 280 #define DECODE64(x,o) (swap ? be64dec(&(x)[o]) : (((uint64_t)((x)[(o)+0]) << 32) + (x)[(o)+1])) 281 const uint32_t phys_hi = DECODE32(ranges, 0); 282 uint64_t bus_phys = DECODE64(ranges, 1); 283 const uint64_t cpu_phys = DECODE64(ranges, 3); 284 uint64_t size = DECODE64(ranges, 5); 285 #undef DECODE32 286 #undef DECODE64 287 288 len -= 28; 289 ranges += 7; 290 291 const bool is64 = (__SHIFTOUT(phys_hi, PHYS_HI_SPACE) == 292 PHYS_HI_SPACE_MEM64) ? true : false; 293 switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) { 294 case PHYS_HI_SPACE_IO: 295 if (pibs->nranges + 1 >= __arraycount(pibs->ranges)) { 296 aprint_error_dev(sc->sc_dev, "too many IO ranges\n"); 297 continue; 298 } 299 pibs->ranges[pibs->nranges].bpci = bus_phys; 300 pibs->ranges[pibs->nranges].bbus = cpu_phys; 301 pibs->ranges[pibs->nranges].size = size; 302 ++pibs->nranges; 303 aprint_verbose_dev(sc->sc_dev, 304 "IO: 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 305 bus_phys, size, cpu_phys); 306 /* 307 * Reserve a PC-like legacy IO ports range, perhaps 308 * for access to VGA registers. 309 */ 310 if (bus_phys == 0 && size >= 0x10000) { 311 bus_phys += 0x1000; 312 size -= 0x1000; 313 } 314 error = pciconf_resource_add(pcires, 315 PCICONF_RESOURCE_IO, bus_phys, size); 316 if (error == 0) 317 sc->sc_pci_flags |= PCI_FLAGS_IO_OKAY; 318 break; 319 case PHYS_HI_SPACE_MEM64: 320 /* FALLTHROUGH */ 321 case PHYS_HI_SPACE_MEM32: 322 if (pmbs->nranges + 1 >= __arraycount(pmbs->ranges)) { 323 aprint_error_dev(sc->sc_dev, "too many mem ranges\n"); 324 continue; 325 } 326 /* both pmem and mem spaces are in the same tag */ 327 pmbs->ranges[pmbs->nranges].bpci = bus_phys; 328 pmbs->ranges[pmbs->nranges].bbus = cpu_phys; 329 pmbs->ranges[pmbs->nranges].size = size; 330 ++pmbs->nranges; 331 if ((phys_hi & PHYS_HI_PREFETCH) != 0 || 332 __SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64) { 333 type = PCICONF_RESOURCE_PREFETCHABLE_MEM; 334 aprint_verbose_dev(sc->sc_dev, 335 "MMIO (%d-bit prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 336 is64 ? 64 : 32, bus_phys, size, cpu_phys); 337 } else { 338 type = PCICONF_RESOURCE_MEM; 339 aprint_verbose_dev(sc->sc_dev, 340 "MMIO (%d-bit non-prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 341 is64 ? 64 : 32, bus_phys, size, cpu_phys); 342 } 343 error = pciconf_resource_add(pcires, type, bus_phys, 344 size); 345 if (error == 0) 346 sc->sc_pci_flags |= PCI_FLAGS_MEM_OKAY; 347 break; 348 default: 349 break; 350 } 351 } 352 353 error = pci_configure_bus(&sc->sc_pc, pcires, sc->sc_bus_min, 354 PCIHOST_CACHELINE_SIZE); 355 356 pciconf_resource_fini(pcires); 357 358 if (error) { 359 aprint_error_dev(sc->sc_dev, "configuration failed: %d\n", error); 360 return error; 361 } 362 363 return 0; 364 } 365 366 static void 367 pcihost_attach_hook(device_t parent, device_t self, 368 struct pcibus_attach_args *pba) 369 { 370 } 371 372 static int 373 pcihost_bus_maxdevs(void *v, int busno) 374 { 375 return 32; 376 } 377 378 static pcitag_t 379 pcihost_make_tag(void *v, int b, int d, int f) 380 { 381 return (b << 16) | (d << 11) | (f << 8); 382 } 383 384 static void 385 pcihost_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 386 { 387 if (bp) 388 *bp = (tag >> 16) & 0xff; 389 if (dp) 390 *dp = (tag >> 11) & 0x1f; 391 if (fp) 392 *fp = (tag >> 8) & 0x7; 393 } 394 395 static u_int 396 pcihost_get_segment(void *v) 397 { 398 struct pcihost_softc *sc = v; 399 400 return sc->sc_seg; 401 } 402 403 static pcireg_t 404 pcihost_conf_read(void *v, pcitag_t tag, int offset) 405 { 406 struct pcihost_softc *sc = v; 407 int b, d, f; 408 u_int reg; 409 410 pcihost_decompose_tag(v, tag, &b, &d, &f); 411 412 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 413 return (pcireg_t) -1; 414 415 if (sc->sc_type == PCIHOST_CAM) { 416 if (offset & ~0xff) 417 return (pcireg_t) -1; 418 reg = (b << 16) | (d << 11) | (f << 8) | offset; 419 } else if (sc->sc_type == PCIHOST_ECAM) { 420 if (offset & ~0xfff) 421 return (pcireg_t) -1; 422 reg = (b << 20) | (d << 15) | (f << 12) | offset; 423 } else { 424 return (pcireg_t) -1; 425 } 426 427 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg); 428 } 429 430 static void 431 pcihost_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 432 { 433 struct pcihost_softc *sc = v; 434 int b, d, f; 435 u_int reg; 436 437 pcihost_decompose_tag(v, tag, &b, &d, &f); 438 439 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 440 return; 441 442 if (sc->sc_type == PCIHOST_CAM) { 443 if (offset & ~0xff) 444 return; 445 reg = (b << 16) | (d << 11) | (f << 8) | offset; 446 } else if (sc->sc_type == PCIHOST_ECAM) { 447 if (offset & ~0xfff) 448 return; 449 reg = (b << 20) | (d << 15) | (f << 12) | offset; 450 } else { 451 return; 452 } 453 454 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val); 455 } 456 457 static int 458 pcihost_conf_hook(void *v, int b, int d, int f, pcireg_t id) 459 { 460 return PCI_CONF_DEFAULT; 461 } 462 463 static void 464 pcihost_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep) 465 { 466 } 467 468 static int 469 pcihost_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 470 { 471 struct pcihost_softc *sc = pa->pa_pc->pc_intr_v; 472 u_int addr_cells, interrupt_cells; 473 const u_int *imap, *imask; 474 int imaplen, imasklen; 475 u_int match[4]; 476 int index; 477 478 if (pa->pa_intrpin == 0) 479 return EINVAL; 480 481 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 482 imask = fdtbus_get_prop(sc->sc_phandle, "interrupt-map-mask", &imasklen); 483 if (imap == NULL || imask == NULL || imasklen != 16) 484 return EINVAL; 485 486 /* Convert attach args to specifier */ 487 match[0] = htobe32( 488 __SHIFTIN(pa->pa_bus, PHYS_HI_BUS) | 489 __SHIFTIN(pa->pa_device, PHYS_HI_DEVICE) | 490 __SHIFTIN(pa->pa_function, PHYS_HI_FUNCTION) 491 ) & imask[0]; 492 match[1] = htobe32(0) & imask[1]; 493 match[2] = htobe32(0) & imask[2]; 494 match[3] = htobe32(pa->pa_intrpin) & imask[3]; 495 496 index = 0; 497 while (imaplen >= 20) { 498 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 499 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 500 addr_cells = 2; 501 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 502 interrupt_cells = 0; 503 if (imaplen < (addr_cells + interrupt_cells) * 4) 504 return ENXIO; 505 506 if ((imap[0] & imask[0]) == match[0] && 507 (imap[1] & imask[1]) == match[1] && 508 (imap[2] & imask[2]) == match[2] && 509 (imap[3] & imask[3]) == match[3]) { 510 *ih = index; 511 return 0; 512 } 513 514 imap += (5 + addr_cells + interrupt_cells); 515 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 516 index++; 517 } 518 519 return EINVAL; 520 } 521 522 static const u_int * 523 pcihost_find_intr(struct pcihost_softc *sc, pci_intr_handle_t ih, int *pihandle) 524 { 525 u_int addr_cells, interrupt_cells; 526 int imaplen, index; 527 const u_int *imap; 528 529 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 530 KASSERT(imap != NULL); 531 532 index = 0; 533 while (imaplen >= 20) { 534 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 535 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 536 addr_cells = 2; 537 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 538 interrupt_cells = 0; 539 if (imaplen < (addr_cells + interrupt_cells) * 4) 540 return NULL; 541 542 if (index == ih) { 543 *pihandle = map_ihandle; 544 return imap + 5 + addr_cells; 545 } 546 547 imap += (5 + addr_cells + interrupt_cells); 548 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 549 index++; 550 } 551 552 return NULL; 553 } 554 555 static const char * 556 pcihost_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 557 { 558 const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); 559 const int vec = __SHIFTOUT(ih, ARM_PCI_INTR_MSI_VEC); 560 struct pcihost_softc *sc = v; 561 const u_int *specifier; 562 int ihandle; 563 564 if (ih & ARM_PCI_INTR_MSIX) { 565 snprintf(buf, len, "irq %d (MSI-X vec %d)", irq, vec); 566 } else if (ih & ARM_PCI_INTR_MSI) { 567 snprintf(buf, len, "irq %d (MSI vec %d)", irq, vec); 568 } else { 569 specifier = pcihost_find_intr(sc, ih & ARM_PCI_INTR_IRQ, &ihandle); 570 if (specifier == NULL) 571 return NULL; 572 573 if (!fdtbus_intr_str_raw(ihandle, specifier, buf, len)) 574 return NULL; 575 } 576 577 return buf; 578 } 579 580 const struct evcnt * 581 pcihost_intr_evcnt(void *v, pci_intr_handle_t ih) 582 { 583 return NULL; 584 } 585 586 static int 587 pcihost_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 588 { 589 switch (attr) { 590 case PCI_INTR_MPSAFE: 591 if (data) 592 *ih |= ARM_PCI_INTR_MPSAFE; 593 else 594 *ih &= ~ARM_PCI_INTR_MPSAFE; 595 return 0; 596 default: 597 return ENODEV; 598 } 599 } 600 601 static void * 602 pcihost_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 603 int (*callback)(void *), void *arg, const char *xname) 604 { 605 struct pcihost_softc *sc = v; 606 const int flags = (ih & ARM_PCI_INTR_MPSAFE) ? FDT_INTR_MPSAFE : 0; 607 const u_int *specifier; 608 int ihandle; 609 610 if ((ih & (ARM_PCI_INTR_MSI | ARM_PCI_INTR_MSIX)) != 0) 611 return arm_pci_msi_intr_establish(&sc->sc_pc, ih, ipl, callback, arg, xname); 612 613 specifier = pcihost_find_intr(sc, ih & ARM_PCI_INTR_IRQ, &ihandle); 614 if (specifier == NULL) 615 return NULL; 616 617 return fdtbus_intr_establish_raw(ihandle, specifier, ipl, flags, 618 callback, arg, xname); 619 } 620 621 static void 622 pcihost_intr_disestablish(void *v, void *vih) 623 { 624 struct pcihost_softc *sc = v; 625 626 fdtbus_intr_disestablish(sc->sc_phandle, vih); 627 } 628 629 static int 630 pcihost_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 631 bus_space_handle_t *bshp) 632 { 633 struct pcih_bus_space * const pbs = t; 634 635 if ((pbs->flags & PCI_FLAGS_IO_OKAY) != 0) { 636 /* Force strongly ordered mapping for all I/O space */ 637 flag = _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED; 638 } 639 640 for (size_t i = 0; i < pbs->nranges; i++) { 641 const bus_addr_t rmin = pbs->ranges[i].bpci; 642 const bus_addr_t rmax = pbs->ranges[i].bpci - 1 + pbs->ranges[i].size; 643 if ((bpa >= rmin) && ((bpa - 1 + size) <= rmax)) { 644 return pbs->map(t, bpa - pbs->ranges[i].bpci + pbs->ranges[i].bbus, size, flag, bshp); 645 } 646 } 647 648 return ERANGE; 649 } 650
Indexes created Tue Sep 23 20:09:58 GMT 2025