pcihost_fdt.c revision 1.3
1 /* $NetBSD: pcihost_fdt.c,v 1.3 2018/11/11 21:24:38 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pcihost_fdt.c,v 1.3 2018/11/11 21:24:38 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/extent.h> 39 #include <sys/queue.h> 40 #include <sys/mutex.h> 41 #include <sys/kmem.h> 42 43 #include <machine/cpu.h> 44 45 #include <arm/cpufunc.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pciconf.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 #include <arm/pci/pci_msi_machdep.h> 54 55 #define IH_INDEX_MASK 0x0000ffff 56 #define IH_MPSAFE 0x80000000 57 58 #define PCIHOST_DEFAULT_BUS_MIN 0 59 #define PCIHOST_DEFAULT_BUS_MAX 255 60 61 #define PCIHOST_CACHELINE_SIZE arm_dcache_align 62 63 /* Physical address format bit definitions */ 64 #define PHYS_HI_RELO __BIT(31) 65 #define PHYS_HI_PREFETCH __BIT(30) 66 #define PHYS_HI_ALIASED __BIT(29) 67 #define PHYS_HI_SPACE __BITS(25,24) 68 #define PHYS_HI_SPACE_CFG 0 69 #define PHYS_HI_SPACE_IO 1 70 #define PHYS_HI_SPACE_MEM32 2 71 #define PHYS_HI_SPACE_MEM64 3 72 #define PHYS_HI_BUS __BITS(23,16) 73 #define PHYS_HI_DEVICE __BITS(15,11) 74 #define PHYS_HI_FUNCTION __BITS(10,8) 75 #define PHYS_HI_REGISTER __BITS(7,0) 76 77 static int pcihost_segment = 0; 78 79 enum pcihost_type { 80 PCIHOST_CAM = 1, 81 PCIHOST_ECAM, 82 }; 83 84 struct pcihost_softc { 85 device_t sc_dev; 86 bus_dma_tag_t sc_dmat; 87 bus_space_tag_t sc_bst; 88 bus_space_handle_t sc_bsh; 89 int sc_phandle; 90 91 enum pcihost_type sc_type; 92 93 u_int sc_seg; 94 u_int sc_bus_min; 95 u_int sc_bus_max; 96 97 struct arm32_pci_chipset sc_pc; 98 }; 99 100 static int pcihost_match(device_t, cfdata_t, void *); 101 static void pcihost_attach(device_t, device_t, void *); 102 103 static void pcihost_init(pci_chipset_tag_t, void *); 104 static int pcihost_config(struct pcihost_softc *); 105 106 static void pcihost_attach_hook(device_t, device_t, 107 struct pcibus_attach_args *); 108 static int pcihost_bus_maxdevs(void *, int); 109 static pcitag_t pcihost_make_tag(void *, int, int, int); 110 static void pcihost_decompose_tag(void *, pcitag_t, int *, int *, int *); 111 static u_int pcihost_get_segment(void *); 112 static pcireg_t pcihost_conf_read(void *, pcitag_t, int); 113 static void pcihost_conf_write(void *, pcitag_t, int, pcireg_t); 114 static int pcihost_conf_hook(void *, int, int, int, pcireg_t); 115 static void pcihost_conf_interrupt(void *, int, int, int, int, int *); 116 117 static int pcihost_intr_map(const struct pci_attach_args *, 118 pci_intr_handle_t *); 119 static const char *pcihost_intr_string(void *, pci_intr_handle_t, 120 char *, size_t); 121 const struct evcnt *pcihost_intr_evcnt(void *, pci_intr_handle_t); 122 static int pcihost_intr_setattr(void *, pci_intr_handle_t *, int, 123 uint64_t); 124 static void * pcihost_intr_establish(void *, pci_intr_handle_t, 125 int, int (*)(void *), void *); 126 static void pcihost_intr_disestablish(void *, void *); 127 128 CFATTACH_DECL_NEW(pcihost_fdt, sizeof(struct pcihost_softc), 129 pcihost_match, pcihost_attach, NULL, NULL); 130 131 static const struct of_compat_data compat_data[] = { 132 { "pci-host-cam-generic", PCIHOST_CAM }, 133 { "pci-host-ecam-generic", PCIHOST_ECAM }, 134 { NULL, 0 } 135 }; 136 137 static int 138 pcihost_match(device_t parent, cfdata_t cf, void *aux) 139 { 140 struct fdt_attach_args * const faa = aux; 141 142 return of_match_compat_data(faa->faa_phandle, compat_data); 143 } 144 145 static void 146 pcihost_attach(device_t parent, device_t self, void *aux) 147 { 148 struct pcihost_softc * const sc = device_private(self); 149 struct fdt_attach_args * const faa = aux; 150 struct pcibus_attach_args pba; 151 bus_addr_t cs_addr; 152 bus_size_t cs_size; 153 const u_int *data; 154 int error, len; 155 156 if (fdtbus_get_reg(faa->faa_phandle, 0, &cs_addr, &cs_size) != 0) { 157 aprint_error(": couldn't get registers\n"); 158 return; 159 } 160 161 sc->sc_dev = self; 162 sc->sc_dmat = faa->faa_dmat; 163 sc->sc_bst = faa->faa_bst; 164 sc->sc_phandle = faa->faa_phandle; 165 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 0, &sc->sc_bsh); 166 if (error) { 167 aprint_error(": couldn't map registers: %d\n", error); 168 return; 169 } 170 sc->sc_type = of_search_compatible(sc->sc_phandle, compat_data)->data; 171 172 aprint_naive("\n"); 173 aprint_normal(": Generic PCI host controller\n"); 174 175 if ((data = fdtbus_get_prop(sc->sc_phandle, "bus-range", &len)) != NULL) { 176 if (len != 8) { 177 aprint_error_dev(self, "malformed 'bus-range' property\n"); 178 return; 179 } 180 sc->sc_bus_min = be32toh(data[0]); 181 sc->sc_bus_max = be32toh(data[1]); 182 } else { 183 sc->sc_bus_min = PCIHOST_DEFAULT_BUS_MIN; 184 sc->sc_bus_max = PCIHOST_DEFAULT_BUS_MAX; 185 } 186 187 /* 188 * Assign a fixed PCI segment ("domain") number. If the property is not 189 * present, assign one. The binding spec says if this property is used to 190 * assign static segment numbers, all host bridges should have segments 191 * astatic assigned to prevent overlaps. 192 */ 193 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-domain", &sc->sc_seg)) 194 sc->sc_seg = pcihost_segment++; 195 196 pcihost_init(&sc->sc_pc, sc); 197 198 if (pcihost_config(sc) != 0) 199 return; 200 201 memset(&pba, 0, sizeof(pba)); 202 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 203 PCI_FLAGS_MRM_OKAY | 204 PCI_FLAGS_MWI_OKAY | 205 PCI_FLAGS_MEM_OKAY | 206 PCI_FLAGS_IO_OKAY; 207 #ifdef __HAVE_PCI_MSI_MSIX 208 if (sc->sc_type == PCIHOST_ECAM) { 209 pba.pba_flags |= PCI_FLAGS_MSI_OKAY | 210 PCI_FLAGS_MSIX_OKAY; 211 } 212 #endif 213 pba.pba_iot = sc->sc_bst; 214 pba.pba_memt = sc->sc_bst; 215 pba.pba_dmat = sc->sc_dmat; 216 #ifdef _PCI_HAVE_DMA64 217 pba.pba_dmat64 = sc->sc_dmat; 218 #endif 219 pba.pba_pc = &sc->sc_pc; 220 pba.pba_bus = sc->sc_bus_min; 221 222 config_found_ia(self, "pcibus", &pba, pcibusprint); 223 } 224 225 static void 226 pcihost_init(pci_chipset_tag_t pc, void *priv) 227 { 228 pc->pc_conf_v = priv; 229 pc->pc_attach_hook = pcihost_attach_hook; 230 pc->pc_bus_maxdevs = pcihost_bus_maxdevs; 231 pc->pc_make_tag = pcihost_make_tag; 232 pc->pc_decompose_tag = pcihost_decompose_tag; 233 pc->pc_get_segment = pcihost_get_segment; 234 pc->pc_conf_read = pcihost_conf_read; 235 pc->pc_conf_write = pcihost_conf_write; 236 pc->pc_conf_hook = pcihost_conf_hook; 237 pc->pc_conf_interrupt = pcihost_conf_interrupt; 238 239 pc->pc_intr_v = priv; 240 pc->pc_intr_map = pcihost_intr_map; 241 pc->pc_intr_string = pcihost_intr_string; 242 pc->pc_intr_evcnt = pcihost_intr_evcnt; 243 pc->pc_intr_setattr = pcihost_intr_setattr; 244 pc->pc_intr_establish = pcihost_intr_establish; 245 pc->pc_intr_disestablish = pcihost_intr_disestablish; 246 } 247 248 static int 249 pcihost_config(struct pcihost_softc *sc) 250 { 251 struct extent *ioext = NULL, *memext = NULL, *pmemext = NULL; 252 const u_int *ranges; 253 u_int probe_only; 254 int error, len; 255 256 /* 257 * If this flag is set, skip configuration of the PCI bus and use existing config. 258 */ 259 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-probe-only", &probe_only)) 260 probe_only = 0; 261 if (probe_only) 262 return 0; 263 264 ranges = fdtbus_get_prop(sc->sc_phandle, "ranges", &len); 265 if (ranges == NULL) { 266 aprint_error_dev(sc->sc_dev, "missing 'ranges' property\n"); 267 return EINVAL; 268 } 269 270 /* 271 * Each entry in the ranges table contains: 272 * - bus address (3 cells) 273 * - cpu physical address (2 cells) 274 * - size (2 cells) 275 * Total size for each entry is 28 bytes (7 cells). 276 */ 277 while (len >= 28) { 278 const uint32_t phys_hi = be32dec(&ranges[0]); 279 const uint64_t cpu_phys = be64dec(&ranges[3]); 280 const uint64_t size = be64dec(&ranges[5]); 281 282 switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) { 283 case PHYS_HI_SPACE_IO: 284 if (ioext != NULL) { 285 aprint_error_dev(sc->sc_dev, "ignoring duplicate IO space range\n"); 286 continue; 287 } 288 ioext = extent_create("pciio", cpu_phys, cpu_phys + size - 1, NULL, 0, EX_NOWAIT); 289 aprint_verbose_dev(sc->sc_dev, 290 "I/O memory @ 0x%" PRIx64 " size 0x%" PRIx64 "\n", 291 cpu_phys, size); 292 break; 293 case PHYS_HI_SPACE_MEM32: 294 if ((phys_hi & PHYS_HI_PREFETCH) != 0) { 295 if (pmemext != NULL) { 296 aprint_error_dev(sc->sc_dev, "ignoring duplicate mem (prefetchable) range\n"); 297 continue; 298 } 299 pmemext = extent_create("pcipmem", cpu_phys, cpu_phys + size - 1, NULL, 0, EX_NOWAIT); 300 aprint_verbose_dev(sc->sc_dev, 301 "32-bit MMIO (prefetchable) @ 0x%" PRIx64 " size 0x%" PRIx64 "\n", 302 cpu_phys, size); 303 } else { 304 if (memext != NULL) { 305 aprint_error_dev(sc->sc_dev, "ignoring duplicate mem (non-prefetchable) range\n"); 306 continue; 307 } 308 memext = extent_create("pcimem", cpu_phys, cpu_phys + size - 1, NULL, 0, EX_NOWAIT); 309 aprint_verbose_dev(sc->sc_dev, 310 "32-bit MMIO (non-prefetchable) @ 0x%" PRIx64 " size 0x%" PRIx64 "\n", 311 cpu_phys, size); 312 } 313 break; 314 default: 315 break; 316 } 317 318 len -= 28; 319 ranges += 7; 320 } 321 322 error = pci_configure_bus(&sc->sc_pc, ioext, memext, pmemext, sc->sc_bus_min, PCIHOST_CACHELINE_SIZE); 323 324 if (ioext) 325 extent_destroy(ioext); 326 if (memext) 327 extent_destroy(memext); 328 if (pmemext) 329 extent_destroy(pmemext); 330 331 if (error) { 332 aprint_error_dev(sc->sc_dev, "configuration failed: %d\n", error); 333 return error; 334 } 335 336 return 0; 337 } 338 339 static void 340 pcihost_attach_hook(device_t parent, device_t self, 341 struct pcibus_attach_args *pba) 342 { 343 } 344 345 static int 346 pcihost_bus_maxdevs(void *v, int busno) 347 { 348 return 32; 349 } 350 351 static pcitag_t 352 pcihost_make_tag(void *v, int b, int d, int f) 353 { 354 return (b << 16) | (d << 11) | (f << 8); 355 } 356 357 static void 358 pcihost_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 359 { 360 if (bp) 361 *bp = (tag >> 16) & 0xff; 362 if (dp) 363 *dp = (tag >> 11) & 0x1f; 364 if (fp) 365 *fp = (tag >> 8) & 0x7; 366 } 367 368 static u_int 369 pcihost_get_segment(void *v) 370 { 371 struct pcihost_softc *sc = v; 372 373 return sc->sc_seg; 374 } 375 376 static pcireg_t 377 pcihost_conf_read(void *v, pcitag_t tag, int offset) 378 { 379 struct pcihost_softc *sc = v; 380 int b, d, f; 381 u_int reg; 382 383 pcihost_decompose_tag(v, tag, &b, &d, &f); 384 385 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 386 return (pcireg_t) -1; 387 388 if (sc->sc_type == PCIHOST_CAM) { 389 if (offset & ~0xff) 390 return (pcireg_t) -1; 391 reg = (b << 16) | (d << 11) | (f << 8) | offset; 392 } else if (sc->sc_type == PCIHOST_ECAM) { 393 if (offset & ~0xfff) 394 return (pcireg_t) -1; 395 reg = (b << 20) | (d << 15) | (f << 12) | offset; 396 } else { 397 return (pcireg_t) -1; 398 } 399 400 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg); 401 } 402 403 static void 404 pcihost_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 405 { 406 struct pcihost_softc *sc = v; 407 int b, d, f; 408 u_int reg; 409 410 pcihost_decompose_tag(v, tag, &b, &d, &f); 411 412 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 413 return; 414 415 if (sc->sc_type == PCIHOST_CAM) { 416 if (offset & ~0xff) 417 return; 418 reg = (b << 16) | (d << 11) | (f << 8) | offset; 419 } else if (sc->sc_type == PCIHOST_ECAM) { 420 if (offset & ~0xfff) 421 return; 422 reg = (b << 20) | (d << 15) | (f << 12) | offset; 423 } else { 424 return; 425 } 426 427 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val); 428 } 429 430 static int 431 pcihost_conf_hook(void *v, int b, int d, int f, pcireg_t id) 432 { 433 return PCI_CONF_DEFAULT; 434 } 435 436 static void 437 pcihost_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep) 438 { 439 } 440 441 static int 442 pcihost_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 443 { 444 struct pcihost_softc *sc = pa->pa_pc->pc_intr_v; 445 u_int addr_cells, interrupt_cells; 446 const u_int *imap, *imask; 447 int imaplen, imasklen; 448 u_int match[4]; 449 int index; 450 451 if (pa->pa_intrpin == 0) 452 return EINVAL; 453 454 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 455 imask = fdtbus_get_prop(sc->sc_phandle, "interrupt-map-mask", &imasklen); 456 if (imap == NULL || imask == NULL || imasklen != 16) 457 return EINVAL; 458 459 /* Convert attach args to specifier */ 460 match[0] = htobe32( 461 __SHIFTIN(pa->pa_bus, PHYS_HI_BUS) | 462 __SHIFTIN(pa->pa_device, PHYS_HI_DEVICE) | 463 __SHIFTIN(pa->pa_function, PHYS_HI_FUNCTION) 464 ) & imask[0]; 465 match[1] = htobe32(0) & imask[1]; 466 match[2] = htobe32(0) & imask[2]; 467 match[3] = htobe32(pa->pa_intrpin) & imask[3]; 468 469 index = 0; 470 while (imaplen >= 20) { 471 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 472 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 473 addr_cells = 2; 474 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 475 interrupt_cells = 0; 476 if (imaplen < (addr_cells + interrupt_cells) * 4) 477 return ENXIO; 478 479 if ((imap[0] & imask[0]) == match[0] && 480 (imap[1] & imask[1]) == match[1] && 481 (imap[2] & imask[2]) == match[2] && 482 (imap[3] & imask[3]) == match[3]) { 483 *ih = index; 484 return 0; 485 } 486 487 imap += (5 + addr_cells + interrupt_cells); 488 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 489 index++; 490 } 491 492 return EINVAL; 493 } 494 495 static const u_int * 496 pcihost_find_intr(struct pcihost_softc *sc, pci_intr_handle_t ih, int *pihandle) 497 { 498 u_int addr_cells, interrupt_cells; 499 int imaplen, index; 500 const u_int *imap; 501 502 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 503 KASSERT(imap != NULL); 504 505 index = 0; 506 while (imaplen >= 20) { 507 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 508 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 509 addr_cells = 2; 510 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 511 interrupt_cells = 0; 512 if (imaplen < (addr_cells + interrupt_cells) * 4) 513 return NULL; 514 515 if (index == ih) { 516 *pihandle = map_ihandle; 517 return imap + 5 + addr_cells; 518 } 519 520 imap += (5 + addr_cells + interrupt_cells); 521 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 522 index++; 523 } 524 525 return NULL; 526 } 527 528 static const char * 529 pcihost_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 530 { 531 const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); 532 const int vec = __SHIFTOUT(ih, ARM_PCI_INTR_MSI_VEC); 533 struct pcihost_softc *sc = v; 534 const u_int *specifier; 535 int ihandle; 536 537 if (ih & ARM_PCI_INTR_MSIX) { 538 snprintf(buf, len, "irq %d (MSI-X vec %d)", irq, vec); 539 } else if (ih & ARM_PCI_INTR_MSI) { 540 snprintf(buf, len, "irq %d (MSI vec %d)", irq, vec); 541 } else { 542 specifier = pcihost_find_intr(sc, ih & IH_INDEX_MASK, &ihandle); 543 if (specifier == NULL) 544 return NULL; 545 546 if (!fdtbus_intr_str_raw(ihandle, specifier, buf, len)) 547 return NULL; 548 } 549 550 return buf; 551 } 552 553 const struct evcnt * 554 pcihost_intr_evcnt(void *v, pci_intr_handle_t ih) 555 { 556 return NULL; 557 } 558 559 static int 560 pcihost_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 561 { 562 switch (attr) { 563 case PCI_INTR_MPSAFE: 564 if (data) 565 *ih |= IH_MPSAFE; 566 else 567 *ih &= ~IH_MPSAFE; 568 return 0; 569 default: 570 return ENODEV; 571 } 572 } 573 574 static void * 575 pcihost_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 576 int (*callback)(void *), void *arg) 577 { 578 struct pcihost_softc *sc = v; 579 const int flags = (ih & IH_MPSAFE) ? FDT_INTR_MPSAFE : 0; 580 const u_int *specifier; 581 int ihandle; 582 583 if ((ih & (ARM_PCI_INTR_MSI | ARM_PCI_INTR_MSIX)) != 0) 584 return arm_pci_msi_intr_establish(&sc->sc_pc, ih, ipl, callback, arg); 585 586 specifier = pcihost_find_intr(sc, ih & IH_INDEX_MASK, &ihandle); 587 if (specifier == NULL) 588 return NULL; 589 590 return fdtbus_intr_establish_raw(ihandle, specifier, ipl, flags, callback, arg); 591 } 592 593 static void 594 pcihost_intr_disestablish(void *v, void *vih) 595 { 596 struct pcihost_softc *sc = v; 597 598 fdtbus_intr_disestablish(sc->sc_phandle, vih); 599 } 600
Indexes created Mon Sep 22 13:09:51 GMT 2025