pcihost_fdt.c revision 1.30
1 /* $NetBSD: pcihost_fdt.c,v 1.30 2022/09/04 16:01:25 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pcihost_fdt.c,v 1.30 2022/09/04 16:01:25 skrll Exp $"); 31 32 #include <sys/param.h> 33 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 #include <sys/lwp.h> 40 #include <sys/mutex.h> 41 #include <sys/queue.h> 42 #include <sys/systm.h> 43 44 #include <machine/cpu.h> 45 46 #include <arm/cpufunc.h> 47 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pciconf.h> 51 52 #include <dev/fdt/fdtvar.h> 53 54 #include <arm/pci/pci_msi_machdep.h> 55 #include <arm/fdt/pcihost_fdtvar.h> 56 57 #define PCIHOST_DEFAULT_BUS_MIN 0 58 #define PCIHOST_DEFAULT_BUS_MAX 255 59 60 #define PCIHOST_CACHELINE_SIZE arm_dcache_align 61 62 int pcihost_segment = 0; 63 64 static int pcihost_match(device_t, cfdata_t, void *); 65 static void pcihost_attach(device_t, device_t, void *); 66 67 static int pcihost_config(struct pcihost_softc *); 68 69 static void pcihost_attach_hook(device_t, device_t, 70 struct pcibus_attach_args *); 71 static int pcihost_bus_maxdevs(void *, int); 72 static pcitag_t pcihost_make_tag(void *, int, int, int); 73 static void pcihost_decompose_tag(void *, pcitag_t, int *, int *, int *); 74 static u_int pcihost_get_segment(void *); 75 static pcireg_t pcihost_conf_read(void *, pcitag_t, int); 76 static void pcihost_conf_write(void *, pcitag_t, int, pcireg_t); 77 static int pcihost_conf_hook(void *, int, int, int, pcireg_t); 78 static void pcihost_conf_interrupt(void *, int, int, int, int, int *); 79 80 static int pcihost_intr_map(const struct pci_attach_args *, 81 pci_intr_handle_t *); 82 static const char *pcihost_intr_string(void *, pci_intr_handle_t, 83 char *, size_t); 84 static const struct evcnt *pcihost_intr_evcnt(void *, pci_intr_handle_t); 85 static int pcihost_intr_setattr(void *, pci_intr_handle_t *, int, 86 uint64_t); 87 static void * pcihost_intr_establish(void *, pci_intr_handle_t, 88 int, int (*)(void *), void *, 89 const char *); 90 static void pcihost_intr_disestablish(void *, void *); 91 92 static int pcihost_bus_space_map(void *, bus_addr_t, bus_size_t, 93 int, bus_space_handle_t *); 94 95 CFATTACH_DECL_NEW(pcihost_fdt, sizeof(struct pcihost_softc), 96 pcihost_match, pcihost_attach, NULL, NULL); 97 98 static const struct device_compatible_entry compat_data[] = { 99 { .compat = "pci-host-cam-generic", .value = PCIHOST_CAM }, 100 { .compat = "pci-host-ecam-generic", .value = PCIHOST_ECAM }, 101 DEVICE_COMPAT_EOL 102 }; 103 104 static int 105 pcihost_match(device_t parent, cfdata_t cf, void *aux) 106 { 107 struct fdt_attach_args * const faa = aux; 108 109 return of_compatible_match(faa->faa_phandle, compat_data); 110 } 111 112 static void 113 pcihost_attach(device_t parent, device_t self, void *aux) 114 { 115 struct pcihost_softc * const sc = device_private(self); 116 struct fdt_attach_args * const faa = aux; 117 bus_addr_t cs_addr; 118 bus_size_t cs_size; 119 int error; 120 121 if (fdtbus_get_reg(faa->faa_phandle, 0, &cs_addr, &cs_size) != 0) { 122 aprint_error(": couldn't get registers\n"); 123 return; 124 } 125 126 sc->sc_dev = self; 127 sc->sc_dmat = faa->faa_dmat; 128 sc->sc_bst = faa->faa_bst; 129 sc->sc_pci_bst = faa->faa_bst; 130 sc->sc_phandle = faa->faa_phandle; 131 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 132 _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED, &sc->sc_bsh); 133 if (error) { 134 aprint_error(": couldn't map registers: %d\n", error); 135 return; 136 } 137 sc->sc_type = of_compatible_lookup(sc->sc_phandle, compat_data)->value; 138 139 #ifdef __HAVE_PCI_MSI_MSIX 140 if (sc->sc_type == PCIHOST_ECAM) { 141 sc->sc_pci_flags |= PCI_FLAGS_MSI_OKAY; 142 sc->sc_pci_flags |= PCI_FLAGS_MSIX_OKAY; 143 } 144 #endif 145 146 aprint_naive("\n"); 147 aprint_normal(": Generic PCI host controller\n"); 148 149 pcihost_init(&sc->sc_pc, sc); 150 pcihost_init2(sc); 151 } 152 153 void 154 pcihost_init2(struct pcihost_softc *sc) 155 { 156 struct pcibus_attach_args pba; 157 const u_int *data; 158 int len; 159 160 if ((data = fdtbus_get_prop(sc->sc_phandle, "bus-range", &len)) != NULL) { 161 if (len != 8) { 162 aprint_error_dev(sc->sc_dev, "malformed 'bus-range' property\n"); 163 return; 164 } 165 sc->sc_bus_min = be32toh(data[0]); 166 sc->sc_bus_max = be32toh(data[1]); 167 } else { 168 sc->sc_bus_min = PCIHOST_DEFAULT_BUS_MIN; 169 sc->sc_bus_max = PCIHOST_DEFAULT_BUS_MAX; 170 } 171 172 /* 173 * Assign a fixed PCI segment ("domain") number. If the property is not 174 * present, assign one. The binding spec says if this property is used to 175 * assign static segment numbers, all host bridges should have segments 176 * astatic assigned to prevent overlaps. 177 */ 178 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-domain", &sc->sc_seg)) 179 sc->sc_seg = pcihost_segment++; 180 181 if (pcihost_config(sc) != 0) 182 return; 183 184 memset(&pba, 0, sizeof(pba)); 185 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 186 PCI_FLAGS_MRM_OKAY | 187 PCI_FLAGS_MWI_OKAY | 188 sc->sc_pci_flags; 189 pba.pba_iot = &sc->sc_io.bst; 190 pba.pba_memt = &sc->sc_mem.bst; 191 pba.pba_dmat = sc->sc_dmat; 192 #ifdef _PCI_HAVE_DMA64 193 pba.pba_dmat64 = sc->sc_dmat; 194 #endif 195 pba.pba_pc = &sc->sc_pc; 196 pba.pba_bus = sc->sc_bus_min; 197 198 config_found(sc->sc_dev, &pba, pcibusprint, 199 CFARGS(.devhandle = device_handle(sc->sc_dev))); 200 } 201 202 void 203 pcihost_init(pci_chipset_tag_t pc, void *priv) 204 { 205 pc->pc_conf_v = priv; 206 pc->pc_attach_hook = pcihost_attach_hook; 207 pc->pc_bus_maxdevs = pcihost_bus_maxdevs; 208 pc->pc_make_tag = pcihost_make_tag; 209 pc->pc_decompose_tag = pcihost_decompose_tag; 210 pc->pc_get_segment = pcihost_get_segment; 211 pc->pc_conf_read = pcihost_conf_read; 212 pc->pc_conf_write = pcihost_conf_write; 213 pc->pc_conf_hook = pcihost_conf_hook; 214 pc->pc_conf_interrupt = pcihost_conf_interrupt; 215 216 pc->pc_intr_v = priv; 217 pc->pc_intr_map = pcihost_intr_map; 218 pc->pc_intr_string = pcihost_intr_string; 219 pc->pc_intr_evcnt = pcihost_intr_evcnt; 220 pc->pc_intr_setattr = pcihost_intr_setattr; 221 pc->pc_intr_establish = pcihost_intr_establish; 222 pc->pc_intr_disestablish = pcihost_intr_disestablish; 223 } 224 225 static int 226 pcihost_config(struct pcihost_softc *sc) 227 { 228 const u_int *ranges; 229 u_int probe_only; 230 int error, len, type; 231 bool swap; 232 233 struct pcih_bus_space * const pibs = &sc->sc_io; 234 pibs->bst = *sc->sc_pci_bst; 235 pibs->bst.bs_cookie = pibs; 236 pibs->map = pibs->bst.bs_map; 237 pibs->flags = PCI_FLAGS_IO_OKAY; 238 pibs->bst.bs_map = pcihost_bus_space_map; 239 240 struct pcih_bus_space * const pmbs = &sc->sc_mem; 241 pmbs->bst = *sc->sc_pci_bst; 242 pmbs->bst.bs_cookie = pmbs; 243 pmbs->map = pmbs->bst.bs_map; 244 pmbs->flags = PCI_FLAGS_MEM_OKAY; 245 pmbs->bst.bs_map = pcihost_bus_space_map; 246 247 /* 248 * If this flag is set, skip configuration of the PCI bus and use existing config. 249 */ 250 const int chosen = OF_finddevice("/chosen"); 251 if (chosen <= 0 || of_getprop_uint32(chosen, "linux,pci-probe-only", &probe_only)) 252 probe_only = 0; 253 254 if (sc->sc_pci_ranges != NULL) { 255 ranges = sc->sc_pci_ranges; 256 len = sc->sc_pci_ranges_cells * 4; 257 swap = false; 258 } else { 259 ranges = fdtbus_get_prop(sc->sc_phandle, "ranges", &len); 260 if (ranges == NULL) { 261 aprint_error_dev(sc->sc_dev, "missing 'ranges' property\n"); 262 return EINVAL; 263 } 264 swap = true; 265 } 266 267 struct pciconf_resources *pcires = pciconf_resource_init(); 268 269 /* 270 * Each entry in the ranges table contains: 271 * - bus address (3 cells) 272 * - cpu physical address (2 cells) 273 * - size (2 cells) 274 * Total size for each entry is 28 bytes (7 cells). 275 */ 276 while (len >= 28) { 277 #define DECODE32(x,o) (swap ? be32dec(&(x)[o]) : (x)[o]) 278 #define DECODE64(x,o) (swap ? be64dec(&(x)[o]) : (((uint64_t)((x)[(o)+0]) << 32) + (x)[(o)+1])) 279 const uint32_t phys_hi = DECODE32(ranges, 0); 280 uint64_t bus_phys = DECODE64(ranges, 1); 281 const uint64_t cpu_phys = DECODE64(ranges, 3); 282 uint64_t size = DECODE64(ranges, 5); 283 #undef DECODE32 284 #undef DECODE64 285 286 len -= 28; 287 ranges += 7; 288 289 const bool is64 = (__SHIFTOUT(phys_hi, PHYS_HI_SPACE) == 290 PHYS_HI_SPACE_MEM64) ? true : false; 291 switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) { 292 case PHYS_HI_SPACE_IO: 293 if (pibs->nranges + 1 >= __arraycount(pibs->ranges)) { 294 aprint_error_dev(sc->sc_dev, "too many IO ranges\n"); 295 continue; 296 } 297 pibs->ranges[pibs->nranges].bpci = bus_phys; 298 pibs->ranges[pibs->nranges].bbus = cpu_phys; 299 pibs->ranges[pibs->nranges].size = size; 300 ++pibs->nranges; 301 aprint_verbose_dev(sc->sc_dev, 302 "IO: 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 303 bus_phys, size, cpu_phys); 304 /* 305 * Reserve a PC-like legacy IO ports range, perhaps 306 * for access to VGA registers. 307 */ 308 if (bus_phys == 0 && size >= 0x10000) { 309 bus_phys += 0x1000; 310 size -= 0x1000; 311 } 312 error = pciconf_resource_add(pcires, 313 PCICONF_RESOURCE_IO, bus_phys, size); 314 if (error == 0) 315 sc->sc_pci_flags |= PCI_FLAGS_IO_OKAY; 316 break; 317 case PHYS_HI_SPACE_MEM64: 318 /* FALLTHROUGH */ 319 case PHYS_HI_SPACE_MEM32: 320 if (pmbs->nranges + 1 >= __arraycount(pmbs->ranges)) { 321 aprint_error_dev(sc->sc_dev, "too many mem ranges\n"); 322 continue; 323 } 324 /* both pmem and mem spaces are in the same tag */ 325 pmbs->ranges[pmbs->nranges].bpci = bus_phys; 326 pmbs->ranges[pmbs->nranges].bbus = cpu_phys; 327 pmbs->ranges[pmbs->nranges].size = size; 328 ++pmbs->nranges; 329 if ((phys_hi & PHYS_HI_PREFETCH) != 0 || 330 __SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64) { 331 type = PCICONF_RESOURCE_PREFETCHABLE_MEM; 332 aprint_verbose_dev(sc->sc_dev, 333 "MMIO (%d-bit prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 334 is64 ? 64 : 32, bus_phys, size, cpu_phys); 335 } else { 336 type = PCICONF_RESOURCE_MEM; 337 aprint_verbose_dev(sc->sc_dev, 338 "MMIO (%d-bit non-prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 339 is64 ? 64 : 32, bus_phys, size, cpu_phys); 340 } 341 error = pciconf_resource_add(pcires, type, bus_phys, 342 size); 343 if (error == 0) 344 sc->sc_pci_flags |= PCI_FLAGS_MEM_OKAY; 345 break; 346 default: 347 break; 348 } 349 } 350 351 if (probe_only) { 352 error = 0; 353 } else { 354 error = pci_configure_bus(&sc->sc_pc, pcires, sc->sc_bus_min, 355 PCIHOST_CACHELINE_SIZE); 356 } 357 358 pciconf_resource_fini(pcires); 359 360 if (error) { 361 aprint_error_dev(sc->sc_dev, "configuration failed: %d\n", error); 362 return error; 363 } 364 365 return 0; 366 } 367 368 static void 369 pcihost_attach_hook(device_t parent, device_t self, 370 struct pcibus_attach_args *pba) 371 { 372 } 373 374 static int 375 pcihost_bus_maxdevs(void *v, int busno) 376 { 377 return 32; 378 } 379 380 static pcitag_t 381 pcihost_make_tag(void *v, int b, int d, int f) 382 { 383 return (b << 16) | (d << 11) | (f << 8); 384 } 385 386 static void 387 pcihost_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 388 { 389 if (bp) 390 *bp = (tag >> 16) & 0xff; 391 if (dp) 392 *dp = (tag >> 11) & 0x1f; 393 if (fp) 394 *fp = (tag >> 8) & 0x7; 395 } 396 397 static u_int 398 pcihost_get_segment(void *v) 399 { 400 struct pcihost_softc *sc = v; 401 402 return sc->sc_seg; 403 } 404 405 static pcireg_t 406 pcihost_conf_read(void *v, pcitag_t tag, int offset) 407 { 408 struct pcihost_softc *sc = v; 409 int b, d, f; 410 u_int reg; 411 412 pcihost_decompose_tag(v, tag, &b, &d, &f); 413 414 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 415 return (pcireg_t) -1; 416 417 if (sc->sc_type == PCIHOST_CAM) { 418 if (offset & ~0xff) 419 return (pcireg_t) -1; 420 reg = (b << 16) | (d << 11) | (f << 8) | offset; 421 } else if (sc->sc_type == PCIHOST_ECAM) { 422 if (offset & ~0xfff) 423 return (pcireg_t) -1; 424 reg = (b << 20) | (d << 15) | (f << 12) | offset; 425 } else { 426 return (pcireg_t) -1; 427 } 428 429 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg); 430 } 431 432 static void 433 pcihost_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 434 { 435 struct pcihost_softc *sc = v; 436 int b, d, f; 437 u_int reg; 438 439 pcihost_decompose_tag(v, tag, &b, &d, &f); 440 441 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 442 return; 443 444 if (sc->sc_type == PCIHOST_CAM) { 445 if (offset & ~0xff) 446 return; 447 reg = (b << 16) | (d << 11) | (f << 8) | offset; 448 } else if (sc->sc_type == PCIHOST_ECAM) { 449 if (offset & ~0xfff) 450 return; 451 reg = (b << 20) | (d << 15) | (f << 12) | offset; 452 } else { 453 return; 454 } 455 456 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val); 457 } 458 459 static int 460 pcihost_conf_hook(void *v, int b, int d, int f, pcireg_t id) 461 { 462 return PCI_CONF_DEFAULT; 463 } 464 465 static void 466 pcihost_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep) 467 { 468 } 469 470 static int 471 pcihost_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 472 { 473 struct pcihost_softc *sc = pa->pa_pc->pc_intr_v; 474 u_int addr_cells, interrupt_cells; 475 const u_int *imap, *imask; 476 int imaplen, imasklen; 477 u_int match[4]; 478 int index; 479 480 if (pa->pa_intrpin == 0) 481 return EINVAL; 482 483 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 484 imask = fdtbus_get_prop(sc->sc_phandle, "interrupt-map-mask", &imasklen); 485 if (imap == NULL || imask == NULL || imasklen != 16) 486 return EINVAL; 487 488 /* Convert attach args to specifier */ 489 match[0] = htobe32( 490 __SHIFTIN(pa->pa_bus, PHYS_HI_BUS) | 491 __SHIFTIN(pa->pa_device, PHYS_HI_DEVICE) | 492 __SHIFTIN(pa->pa_function, PHYS_HI_FUNCTION) 493 ) & imask[0]; 494 match[1] = htobe32(0) & imask[1]; 495 match[2] = htobe32(0) & imask[2]; 496 match[3] = htobe32(pa->pa_intrpin) & imask[3]; 497 498 index = 0; 499 while (imaplen >= 20) { 500 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 501 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 502 addr_cells = 2; 503 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 504 interrupt_cells = 0; 505 if (imaplen < (addr_cells + interrupt_cells) * 4) 506 return ENXIO; 507 508 if ((imap[0] & imask[0]) == match[0] && 509 (imap[1] & imask[1]) == match[1] && 510 (imap[2] & imask[2]) == match[2] && 511 (imap[3] & imask[3]) == match[3]) { 512 *ih = index; 513 return 0; 514 } 515 516 imap += (5 + addr_cells + interrupt_cells); 517 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 518 index++; 519 } 520 521 return EINVAL; 522 } 523 524 static const u_int * 525 pcihost_find_intr(struct pcihost_softc *sc, pci_intr_handle_t ih, int *pihandle) 526 { 527 u_int addr_cells, interrupt_cells; 528 int imaplen, index; 529 const u_int *imap; 530 531 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 532 KASSERT(imap != NULL); 533 534 index = 0; 535 while (imaplen >= 20) { 536 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 537 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 538 addr_cells = 2; 539 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 540 interrupt_cells = 0; 541 if (imaplen < (addr_cells + interrupt_cells) * 4) 542 return NULL; 543 544 if (index == ih) { 545 *pihandle = map_ihandle; 546 return imap + 5 + addr_cells; 547 } 548 549 imap += (5 + addr_cells + interrupt_cells); 550 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 551 index++; 552 } 553 554 return NULL; 555 } 556 557 static const char * 558 pcihost_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 559 { 560 const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); 561 const int vec = __SHIFTOUT(ih, ARM_PCI_INTR_MSI_VEC); 562 struct pcihost_softc *sc = v; 563 const u_int *specifier; 564 int ihandle; 565 566 if (ih & ARM_PCI_INTR_MSIX) { 567 snprintf(buf, len, "irq %d (MSI-X vec %d)", irq, vec); 568 } else if (ih & ARM_PCI_INTR_MSI) { 569 snprintf(buf, len, "irq %d (MSI vec %d)", irq, vec); 570 } else { 571 specifier = pcihost_find_intr(sc, ih & ARM_PCI_INTR_IRQ, &ihandle); 572 if (specifier == NULL) 573 return NULL; 574 575 if (!fdtbus_intr_str_raw(ihandle, specifier, buf, len)) 576 return NULL; 577 } 578 579 return buf; 580 } 581 582 const struct evcnt * 583 pcihost_intr_evcnt(void *v, pci_intr_handle_t ih) 584 { 585 return NULL; 586 } 587 588 static int 589 pcihost_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 590 { 591 switch (attr) { 592 case PCI_INTR_MPSAFE: 593 if (data) 594 *ih |= ARM_PCI_INTR_MPSAFE; 595 else 596 *ih &= ~ARM_PCI_INTR_MPSAFE; 597 return 0; 598 default: 599 return ENODEV; 600 } 601 } 602 603 static void * 604 pcihost_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 605 int (*callback)(void *), void *arg, const char *xname) 606 { 607 struct pcihost_softc *sc = v; 608 const int flags = (ih & ARM_PCI_INTR_MPSAFE) ? FDT_INTR_MPSAFE : 0; 609 const u_int *specifier; 610 int ihandle; 611 612 if ((ih & (ARM_PCI_INTR_MSI | ARM_PCI_INTR_MSIX)) != 0) 613 return arm_pci_msi_intr_establish(&sc->sc_pc, ih, ipl, callback, arg, xname); 614 615 specifier = pcihost_find_intr(sc, ih & ARM_PCI_INTR_IRQ, &ihandle); 616 if (specifier == NULL) 617 return NULL; 618 619 return fdtbus_intr_establish_raw(ihandle, specifier, ipl, flags, 620 callback, arg, xname); 621 } 622 623 static void 624 pcihost_intr_disestablish(void *v, void *vih) 625 { 626 struct pcihost_softc *sc = v; 627 628 fdtbus_intr_disestablish(sc->sc_phandle, vih); 629 } 630 631 static int 632 pcihost_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 633 bus_space_handle_t *bshp) 634 { 635 struct pcih_bus_space * const pbs = t; 636 637 if ((pbs->flags & PCI_FLAGS_IO_OKAY) != 0) { 638 /* Force strongly ordered mapping for all I/O space */ 639 flag = _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED; 640 } 641 642 for (size_t i = 0; i < pbs->nranges; i++) { 643 const bus_addr_t rmin = pbs->ranges[i].bpci; 644 const bus_addr_t rmax = pbs->ranges[i].bpci - 1 + pbs->ranges[i].size; 645 if ((bpa >= rmin) && ((bpa - 1 + size) <= rmax)) { 646 return pbs->map(t, bpa - pbs->ranges[i].bpci + pbs->ranges[i].bbus, size, flag, bshp); 647 } 648 } 649 650 return ERANGE; 651 } 652
Indexes created Tue Sep 23 23:09:58 GMT 2025