pcihost_fdt.c revision 1.5
1 /* $NetBSD: pcihost_fdt.c,v 1.5 2018/11/16 19:32:01 jakllsch Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pcihost_fdt.c,v 1.5 2018/11/16 19:32:01 jakllsch Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/extent.h> 39 #include <sys/queue.h> 40 #include <sys/mutex.h> 41 #include <sys/kmem.h> 42 43 #include <machine/cpu.h> 44 45 #include <arm/cpufunc.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pciconf.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 #include <arm/pci/pci_msi_machdep.h> 54 55 #define IH_INDEX_MASK 0x0000ffff 56 #define IH_MPSAFE 0x80000000 57 58 #define PCIHOST_DEFAULT_BUS_MIN 0 59 #define PCIHOST_DEFAULT_BUS_MAX 255 60 61 #define PCIHOST_CACHELINE_SIZE arm_dcache_align 62 63 /* Physical address format bit definitions */ 64 #define PHYS_HI_RELO __BIT(31) 65 #define PHYS_HI_PREFETCH __BIT(30) 66 #define PHYS_HI_ALIASED __BIT(29) 67 #define PHYS_HI_SPACE __BITS(25,24) 68 #define PHYS_HI_SPACE_CFG 0 69 #define PHYS_HI_SPACE_IO 1 70 #define PHYS_HI_SPACE_MEM32 2 71 #define PHYS_HI_SPACE_MEM64 3 72 #define PHYS_HI_BUS __BITS(23,16) 73 #define PHYS_HI_DEVICE __BITS(15,11) 74 #define PHYS_HI_FUNCTION __BITS(10,8) 75 #define PHYS_HI_REGISTER __BITS(7,0) 76 77 static int pcihost_segment = 0; 78 79 enum pcihost_type { 80 PCIHOST_CAM = 1, 81 PCIHOST_ECAM, 82 }; 83 84 struct pcihost_softc { 85 device_t sc_dev; 86 bus_dma_tag_t sc_dmat; 87 bus_space_tag_t sc_bst; 88 bus_space_handle_t sc_bsh; 89 int sc_phandle; 90 91 enum pcihost_type sc_type; 92 93 u_int sc_seg; 94 u_int sc_bus_min; 95 u_int sc_bus_max; 96 97 struct arm32_pci_chipset sc_pc; 98 }; 99 100 static int pcihost_match(device_t, cfdata_t, void *); 101 static void pcihost_attach(device_t, device_t, void *); 102 103 static void pcihost_init(pci_chipset_tag_t, void *); 104 static int pcihost_config(struct pcihost_softc *); 105 106 static void pcihost_attach_hook(device_t, device_t, 107 struct pcibus_attach_args *); 108 static int pcihost_bus_maxdevs(void *, int); 109 static pcitag_t pcihost_make_tag(void *, int, int, int); 110 static void pcihost_decompose_tag(void *, pcitag_t, int *, int *, int *); 111 static u_int pcihost_get_segment(void *); 112 static pcireg_t pcihost_conf_read(void *, pcitag_t, int); 113 static void pcihost_conf_write(void *, pcitag_t, int, pcireg_t); 114 static int pcihost_conf_hook(void *, int, int, int, pcireg_t); 115 static void pcihost_conf_interrupt(void *, int, int, int, int, int *); 116 117 static int pcihost_intr_map(const struct pci_attach_args *, 118 pci_intr_handle_t *); 119 static const char *pcihost_intr_string(void *, pci_intr_handle_t, 120 char *, size_t); 121 static const struct evcnt *pcihost_intr_evcnt(void *, pci_intr_handle_t); 122 static int pcihost_intr_setattr(void *, pci_intr_handle_t *, int, 123 uint64_t); 124 static void * pcihost_intr_establish(void *, pci_intr_handle_t, 125 int, int (*)(void *), void *, 126 const char *); 127 static void pcihost_intr_disestablish(void *, void *); 128 129 CFATTACH_DECL_NEW(pcihost_fdt, sizeof(struct pcihost_softc), 130 pcihost_match, pcihost_attach, NULL, NULL); 131 132 static const struct of_compat_data compat_data[] = { 133 { "pci-host-cam-generic", PCIHOST_CAM }, 134 { "pci-host-ecam-generic", PCIHOST_ECAM }, 135 { NULL, 0 } 136 }; 137 138 static int 139 pcihost_match(device_t parent, cfdata_t cf, void *aux) 140 { 141 struct fdt_attach_args * const faa = aux; 142 143 return of_match_compat_data(faa->faa_phandle, compat_data); 144 } 145 146 static void 147 pcihost_attach(device_t parent, device_t self, void *aux) 148 { 149 struct pcihost_softc * const sc = device_private(self); 150 struct fdt_attach_args * const faa = aux; 151 struct pcibus_attach_args pba; 152 bus_addr_t cs_addr; 153 bus_size_t cs_size; 154 const u_int *data; 155 int error, len; 156 157 if (fdtbus_get_reg(faa->faa_phandle, 0, &cs_addr, &cs_size) != 0) { 158 aprint_error(": couldn't get registers\n"); 159 return; 160 } 161 162 sc->sc_dev = self; 163 sc->sc_dmat = faa->faa_dmat; 164 sc->sc_bst = faa->faa_bst; 165 sc->sc_phandle = faa->faa_phandle; 166 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 0, &sc->sc_bsh); 167 if (error) { 168 aprint_error(": couldn't map registers: %d\n", error); 169 return; 170 } 171 sc->sc_type = of_search_compatible(sc->sc_phandle, compat_data)->data; 172 173 aprint_naive("\n"); 174 aprint_normal(": Generic PCI host controller\n"); 175 176 if ((data = fdtbus_get_prop(sc->sc_phandle, "bus-range", &len)) != NULL) { 177 if (len != 8) { 178 aprint_error_dev(self, "malformed 'bus-range' property\n"); 179 return; 180 } 181 sc->sc_bus_min = be32toh(data[0]); 182 sc->sc_bus_max = be32toh(data[1]); 183 } else { 184 sc->sc_bus_min = PCIHOST_DEFAULT_BUS_MIN; 185 sc->sc_bus_max = PCIHOST_DEFAULT_BUS_MAX; 186 } 187 188 /* 189 * Assign a fixed PCI segment ("domain") number. If the property is not 190 * present, assign one. The binding spec says if this property is used to 191 * assign static segment numbers, all host bridges should have segments 192 * astatic assigned to prevent overlaps. 193 */ 194 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-domain", &sc->sc_seg)) 195 sc->sc_seg = pcihost_segment++; 196 197 pcihost_init(&sc->sc_pc, sc); 198 199 if (pcihost_config(sc) != 0) 200 return; 201 202 memset(&pba, 0, sizeof(pba)); 203 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 204 PCI_FLAGS_MRM_OKAY | 205 PCI_FLAGS_MWI_OKAY | 206 PCI_FLAGS_MEM_OKAY | 207 PCI_FLAGS_IO_OKAY; 208 #ifdef __HAVE_PCI_MSI_MSIX 209 if (sc->sc_type == PCIHOST_ECAM) { 210 pba.pba_flags |= PCI_FLAGS_MSI_OKAY | 211 PCI_FLAGS_MSIX_OKAY; 212 } 213 #endif 214 pba.pba_iot = sc->sc_bst; 215 pba.pba_memt = sc->sc_bst; 216 pba.pba_dmat = sc->sc_dmat; 217 #ifdef _PCI_HAVE_DMA64 218 pba.pba_dmat64 = sc->sc_dmat; 219 #endif 220 pba.pba_pc = &sc->sc_pc; 221 pba.pba_bus = sc->sc_bus_min; 222 223 config_found_ia(self, "pcibus", &pba, pcibusprint); 224 } 225 226 static void 227 pcihost_init(pci_chipset_tag_t pc, void *priv) 228 { 229 pc->pc_conf_v = priv; 230 pc->pc_attach_hook = pcihost_attach_hook; 231 pc->pc_bus_maxdevs = pcihost_bus_maxdevs; 232 pc->pc_make_tag = pcihost_make_tag; 233 pc->pc_decompose_tag = pcihost_decompose_tag; 234 pc->pc_get_segment = pcihost_get_segment; 235 pc->pc_conf_read = pcihost_conf_read; 236 pc->pc_conf_write = pcihost_conf_write; 237 pc->pc_conf_hook = pcihost_conf_hook; 238 pc->pc_conf_interrupt = pcihost_conf_interrupt; 239 240 pc->pc_intr_v = priv; 241 pc->pc_intr_map = pcihost_intr_map; 242 pc->pc_intr_string = pcihost_intr_string; 243 pc->pc_intr_evcnt = pcihost_intr_evcnt; 244 pc->pc_intr_setattr = pcihost_intr_setattr; 245 pc->pc_intr_establish = pcihost_intr_establish; 246 pc->pc_intr_disestablish = pcihost_intr_disestablish; 247 } 248 249 static int 250 pcihost_config(struct pcihost_softc *sc) 251 { 252 struct extent *ioext = NULL, *memext = NULL, *pmemext = NULL; 253 const u_int *ranges; 254 u_int probe_only; 255 int error, len; 256 257 /* 258 * If this flag is set, skip configuration of the PCI bus and use existing config. 259 */ 260 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-probe-only", &probe_only)) 261 probe_only = 0; 262 if (probe_only) 263 return 0; 264 265 ranges = fdtbus_get_prop(sc->sc_phandle, "ranges", &len); 266 if (ranges == NULL) { 267 aprint_error_dev(sc->sc_dev, "missing 'ranges' property\n"); 268 return EINVAL; 269 } 270 271 /* 272 * Each entry in the ranges table contains: 273 * - bus address (3 cells) 274 * - cpu physical address (2 cells) 275 * - size (2 cells) 276 * Total size for each entry is 28 bytes (7 cells). 277 */ 278 while (len >= 28) { 279 const uint32_t phys_hi = be32dec(&ranges[0]); 280 const uint64_t cpu_phys = be64dec(&ranges[3]); 281 const uint64_t size = be64dec(&ranges[5]); 282 283 switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) { 284 case PHYS_HI_SPACE_IO: 285 if (ioext != NULL) { 286 aprint_error_dev(sc->sc_dev, "ignoring duplicate IO space range\n"); 287 continue; 288 } 289 ioext = extent_create("pciio", cpu_phys, cpu_phys + size - 1, NULL, 0, EX_NOWAIT); 290 aprint_verbose_dev(sc->sc_dev, 291 "I/O memory @ 0x%" PRIx64 " size 0x%" PRIx64 "\n", 292 cpu_phys, size); 293 break; 294 case PHYS_HI_SPACE_MEM32: 295 if ((phys_hi & PHYS_HI_PREFETCH) != 0) { 296 if (pmemext != NULL) { 297 aprint_error_dev(sc->sc_dev, "ignoring duplicate mem (prefetchable) range\n"); 298 continue; 299 } 300 pmemext = extent_create("pcipmem", cpu_phys, cpu_phys + size - 1, NULL, 0, EX_NOWAIT); 301 aprint_verbose_dev(sc->sc_dev, 302 "32-bit MMIO (prefetchable) @ 0x%" PRIx64 " size 0x%" PRIx64 "\n", 303 cpu_phys, size); 304 } else { 305 if (memext != NULL) { 306 aprint_error_dev(sc->sc_dev, "ignoring duplicate mem (non-prefetchable) range\n"); 307 continue; 308 } 309 memext = extent_create("pcimem", cpu_phys, cpu_phys + size - 1, NULL, 0, EX_NOWAIT); 310 aprint_verbose_dev(sc->sc_dev, 311 "32-bit MMIO (non-prefetchable) @ 0x%" PRIx64 " size 0x%" PRIx64 "\n", 312 cpu_phys, size); 313 } 314 break; 315 default: 316 break; 317 } 318 319 len -= 28; 320 ranges += 7; 321 } 322 323 error = pci_configure_bus(&sc->sc_pc, ioext, memext, pmemext, sc->sc_bus_min, PCIHOST_CACHELINE_SIZE); 324 325 if (ioext) 326 extent_destroy(ioext); 327 if (memext) 328 extent_destroy(memext); 329 if (pmemext) 330 extent_destroy(pmemext); 331 332 if (error) { 333 aprint_error_dev(sc->sc_dev, "configuration failed: %d\n", error); 334 return error; 335 } 336 337 return 0; 338 } 339 340 static void 341 pcihost_attach_hook(device_t parent, device_t self, 342 struct pcibus_attach_args *pba) 343 { 344 } 345 346 static int 347 pcihost_bus_maxdevs(void *v, int busno) 348 { 349 return 32; 350 } 351 352 static pcitag_t 353 pcihost_make_tag(void *v, int b, int d, int f) 354 { 355 return (b << 16) | (d << 11) | (f << 8); 356 } 357 358 static void 359 pcihost_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 360 { 361 if (bp) 362 *bp = (tag >> 16) & 0xff; 363 if (dp) 364 *dp = (tag >> 11) & 0x1f; 365 if (fp) 366 *fp = (tag >> 8) & 0x7; 367 } 368 369 static u_int 370 pcihost_get_segment(void *v) 371 { 372 struct pcihost_softc *sc = v; 373 374 return sc->sc_seg; 375 } 376 377 static pcireg_t 378 pcihost_conf_read(void *v, pcitag_t tag, int offset) 379 { 380 struct pcihost_softc *sc = v; 381 int b, d, f; 382 u_int reg; 383 384 pcihost_decompose_tag(v, tag, &b, &d, &f); 385 386 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 387 return (pcireg_t) -1; 388 389 if (sc->sc_type == PCIHOST_CAM) { 390 if (offset & ~0xff) 391 return (pcireg_t) -1; 392 reg = (b << 16) | (d << 11) | (f << 8) | offset; 393 } else if (sc->sc_type == PCIHOST_ECAM) { 394 if (offset & ~0xfff) 395 return (pcireg_t) -1; 396 reg = (b << 20) | (d << 15) | (f << 12) | offset; 397 } else { 398 return (pcireg_t) -1; 399 } 400 401 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg); 402 } 403 404 static void 405 pcihost_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 406 { 407 struct pcihost_softc *sc = v; 408 int b, d, f; 409 u_int reg; 410 411 pcihost_decompose_tag(v, tag, &b, &d, &f); 412 413 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 414 return; 415 416 if (sc->sc_type == PCIHOST_CAM) { 417 if (offset & ~0xff) 418 return; 419 reg = (b << 16) | (d << 11) | (f << 8) | offset; 420 } else if (sc->sc_type == PCIHOST_ECAM) { 421 if (offset & ~0xfff) 422 return; 423 reg = (b << 20) | (d << 15) | (f << 12) | offset; 424 } else { 425 return; 426 } 427 428 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val); 429 } 430 431 static int 432 pcihost_conf_hook(void *v, int b, int d, int f, pcireg_t id) 433 { 434 return PCI_CONF_DEFAULT; 435 } 436 437 static void 438 pcihost_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep) 439 { 440 } 441 442 static int 443 pcihost_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 444 { 445 struct pcihost_softc *sc = pa->pa_pc->pc_intr_v; 446 u_int addr_cells, interrupt_cells; 447 const u_int *imap, *imask; 448 int imaplen, imasklen; 449 u_int match[4]; 450 int index; 451 452 if (pa->pa_intrpin == 0) 453 return EINVAL; 454 455 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 456 imask = fdtbus_get_prop(sc->sc_phandle, "interrupt-map-mask", &imasklen); 457 if (imap == NULL || imask == NULL || imasklen != 16) 458 return EINVAL; 459 460 /* Convert attach args to specifier */ 461 match[0] = htobe32( 462 __SHIFTIN(pa->pa_bus, PHYS_HI_BUS) | 463 __SHIFTIN(pa->pa_device, PHYS_HI_DEVICE) | 464 __SHIFTIN(pa->pa_function, PHYS_HI_FUNCTION) 465 ) & imask[0]; 466 match[1] = htobe32(0) & imask[1]; 467 match[2] = htobe32(0) & imask[2]; 468 match[3] = htobe32(pa->pa_intrpin) & imask[3]; 469 470 index = 0; 471 while (imaplen >= 20) { 472 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 473 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 474 addr_cells = 2; 475 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 476 interrupt_cells = 0; 477 if (imaplen < (addr_cells + interrupt_cells) * 4) 478 return ENXIO; 479 480 if ((imap[0] & imask[0]) == match[0] && 481 (imap[1] & imask[1]) == match[1] && 482 (imap[2] & imask[2]) == match[2] && 483 (imap[3] & imask[3]) == match[3]) { 484 *ih = index; 485 return 0; 486 } 487 488 imap += (5 + addr_cells + interrupt_cells); 489 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 490 index++; 491 } 492 493 return EINVAL; 494 } 495 496 static const u_int * 497 pcihost_find_intr(struct pcihost_softc *sc, pci_intr_handle_t ih, int *pihandle) 498 { 499 u_int addr_cells, interrupt_cells; 500 int imaplen, index; 501 const u_int *imap; 502 503 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 504 KASSERT(imap != NULL); 505 506 index = 0; 507 while (imaplen >= 20) { 508 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 509 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 510 addr_cells = 2; 511 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 512 interrupt_cells = 0; 513 if (imaplen < (addr_cells + interrupt_cells) * 4) 514 return NULL; 515 516 if (index == ih) { 517 *pihandle = map_ihandle; 518 return imap + 5 + addr_cells; 519 } 520 521 imap += (5 + addr_cells + interrupt_cells); 522 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 523 index++; 524 } 525 526 return NULL; 527 } 528 529 static const char * 530 pcihost_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 531 { 532 const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); 533 const int vec = __SHIFTOUT(ih, ARM_PCI_INTR_MSI_VEC); 534 struct pcihost_softc *sc = v; 535 const u_int *specifier; 536 int ihandle; 537 538 if (ih & ARM_PCI_INTR_MSIX) { 539 snprintf(buf, len, "irq %d (MSI-X vec %d)", irq, vec); 540 } else if (ih & ARM_PCI_INTR_MSI) { 541 snprintf(buf, len, "irq %d (MSI vec %d)", irq, vec); 542 } else { 543 specifier = pcihost_find_intr(sc, ih & IH_INDEX_MASK, &ihandle); 544 if (specifier == NULL) 545 return NULL; 546 547 if (!fdtbus_intr_str_raw(ihandle, specifier, buf, len)) 548 return NULL; 549 } 550 551 return buf; 552 } 553 554 const struct evcnt * 555 pcihost_intr_evcnt(void *v, pci_intr_handle_t ih) 556 { 557 return NULL; 558 } 559 560 static int 561 pcihost_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 562 { 563 switch (attr) { 564 case PCI_INTR_MPSAFE: 565 if (data) 566 *ih |= IH_MPSAFE; 567 else 568 *ih &= ~IH_MPSAFE; 569 return 0; 570 default: 571 return ENODEV; 572 } 573 } 574 575 static void * 576 pcihost_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 577 int (*callback)(void *), void *arg, const char *xname) 578 { 579 struct pcihost_softc *sc = v; 580 const int flags = (ih & IH_MPSAFE) ? FDT_INTR_MPSAFE : 0; 581 const u_int *specifier; 582 int ihandle; 583 584 if ((ih & (ARM_PCI_INTR_MSI | ARM_PCI_INTR_MSIX)) != 0) 585 return arm_pci_msi_intr_establish(&sc->sc_pc, ih, ipl, callback, arg, xname); 586 587 specifier = pcihost_find_intr(sc, ih & IH_INDEX_MASK, &ihandle); 588 if (specifier == NULL) 589 return NULL; 590 591 return fdtbus_intr_establish_raw(ihandle, specifier, ipl, flags, callback, arg); 592 } 593 594 static void 595 pcihost_intr_disestablish(void *v, void *vih) 596 { 597 struct pcihost_softc *sc = v; 598 599 fdtbus_intr_disestablish(sc->sc_phandle, vih); 600 } 601
Indexes created Tue Sep 23 14:10:03 GMT 2025