pcihost_fdt.c revision 1.8.4.3
1 /* $NetBSD: pcihost_fdt.c,v 1.8.4.3 2020/04/08 14:07:29 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pcihost_fdt.c,v 1.8.4.3 2020/04/08 14:07:29 martin Exp $"); 31 32 #include <sys/param.h> 33 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/extent.h> 37 #include <sys/intr.h> 38 #include <sys/kernel.h> 39 #include <sys/kmem.h> 40 #include <sys/lwp.h> 41 #include <sys/mutex.h> 42 #include <sys/queue.h> 43 #include <sys/systm.h> 44 45 #include <machine/cpu.h> 46 47 #include <arm/cpufunc.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pciconf.h> 52 53 #include <dev/fdt/fdtvar.h> 54 55 #include <arm/pci/pci_msi_machdep.h> 56 #include <arm/fdt/pcihost_fdtvar.h> 57 58 #define IH_INDEX_MASK 0x0000ffff 59 #define IH_MPSAFE 0x80000000 60 61 #define PCIHOST_DEFAULT_BUS_MIN 0 62 #define PCIHOST_DEFAULT_BUS_MAX 255 63 64 #define PCIHOST_CACHELINE_SIZE arm_dcache_align 65 66 int pcihost_segment = 0; 67 68 static int pcihost_match(device_t, cfdata_t, void *); 69 static void pcihost_attach(device_t, device_t, void *); 70 71 static int pcihost_config(struct pcihost_softc *); 72 73 static void pcihost_attach_hook(device_t, device_t, 74 struct pcibus_attach_args *); 75 static int pcihost_bus_maxdevs(void *, int); 76 static pcitag_t pcihost_make_tag(void *, int, int, int); 77 static void pcihost_decompose_tag(void *, pcitag_t, int *, int *, int *); 78 static u_int pcihost_get_segment(void *); 79 static pcireg_t pcihost_conf_read(void *, pcitag_t, int); 80 static void pcihost_conf_write(void *, pcitag_t, int, pcireg_t); 81 static int pcihost_conf_hook(void *, int, int, int, pcireg_t); 82 static void pcihost_conf_interrupt(void *, int, int, int, int, int *); 83 84 static int pcihost_intr_map(const struct pci_attach_args *, 85 pci_intr_handle_t *); 86 static const char *pcihost_intr_string(void *, pci_intr_handle_t, 87 char *, size_t); 88 static const struct evcnt *pcihost_intr_evcnt(void *, pci_intr_handle_t); 89 static int pcihost_intr_setattr(void *, pci_intr_handle_t *, int, 90 uint64_t); 91 static void * pcihost_intr_establish(void *, pci_intr_handle_t, 92 int, int (*)(void *), void *, 93 const char *); 94 static void pcihost_intr_disestablish(void *, void *); 95 96 static int pcihost_bus_space_map(void *, bus_addr_t, bus_size_t, 97 int, bus_space_handle_t *); 98 99 CFATTACH_DECL_NEW(pcihost_fdt, sizeof(struct pcihost_softc), 100 pcihost_match, pcihost_attach, NULL, NULL); 101 102 static const struct of_compat_data compat_data[] = { 103 { "pci-host-cam-generic", PCIHOST_CAM }, 104 { "pci-host-ecam-generic", PCIHOST_ECAM }, 105 { NULL, 0 } 106 }; 107 108 static int 109 pcihost_match(device_t parent, cfdata_t cf, void *aux) 110 { 111 struct fdt_attach_args * const faa = aux; 112 113 return of_match_compat_data(faa->faa_phandle, compat_data); 114 } 115 116 static void 117 pcihost_attach(device_t parent, device_t self, void *aux) 118 { 119 struct pcihost_softc * const sc = device_private(self); 120 struct fdt_attach_args * const faa = aux; 121 bus_addr_t cs_addr; 122 bus_size_t cs_size; 123 int error; 124 125 if (fdtbus_get_reg(faa->faa_phandle, 0, &cs_addr, &cs_size) != 0) { 126 aprint_error(": couldn't get registers\n"); 127 return; 128 } 129 130 sc->sc_dev = self; 131 sc->sc_dmat = faa->faa_dmat; 132 sc->sc_bst = faa->faa_bst; 133 sc->sc_phandle = faa->faa_phandle; 134 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 135 _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED, &sc->sc_bsh); 136 if (error) { 137 aprint_error(": couldn't map registers: %d\n", error); 138 return; 139 } 140 sc->sc_type = of_search_compatible(sc->sc_phandle, compat_data)->data; 141 142 aprint_naive("\n"); 143 aprint_normal(": Generic PCI host controller\n"); 144 145 pcihost_init(&sc->sc_pc, sc); 146 pcihost_init2(sc); 147 } 148 149 void 150 pcihost_init2(struct pcihost_softc *sc) 151 { 152 struct pcibus_attach_args pba; 153 const u_int *data; 154 int len; 155 156 if ((data = fdtbus_get_prop(sc->sc_phandle, "bus-range", &len)) != NULL) { 157 if (len != 8) { 158 aprint_error_dev(sc->sc_dev, "malformed 'bus-range' property\n"); 159 return; 160 } 161 sc->sc_bus_min = be32toh(data[0]); 162 sc->sc_bus_max = be32toh(data[1]); 163 } else { 164 sc->sc_bus_min = PCIHOST_DEFAULT_BUS_MIN; 165 sc->sc_bus_max = PCIHOST_DEFAULT_BUS_MAX; 166 } 167 168 /* 169 * Assign a fixed PCI segment ("domain") number. If the property is not 170 * present, assign one. The binding spec says if this property is used to 171 * assign static segment numbers, all host bridges should have segments 172 * astatic assigned to prevent overlaps. 173 */ 174 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-domain", &sc->sc_seg)) 175 sc->sc_seg = pcihost_segment++; 176 177 if (pcihost_config(sc) != 0) 178 return; 179 180 memset(&pba, 0, sizeof(pba)); 181 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 182 PCI_FLAGS_MRM_OKAY | 183 PCI_FLAGS_MWI_OKAY | 184 PCI_FLAGS_IO_OKAY | 185 PCI_FLAGS_MEM_OKAY; 186 #ifdef __HAVE_PCI_MSI_MSIX 187 if (sc->sc_type == PCIHOST_ECAM) { 188 pba.pba_flags |= PCI_FLAGS_MSI_OKAY | 189 PCI_FLAGS_MSIX_OKAY; 190 } 191 #endif 192 pba.pba_iot = &sc->sc_io.bst; 193 pba.pba_memt = &sc->sc_mem.bst; 194 pba.pba_dmat = sc->sc_dmat; 195 #ifdef _PCI_HAVE_DMA64 196 pba.pba_dmat64 = sc->sc_dmat; 197 #endif 198 pba.pba_pc = &sc->sc_pc; 199 pba.pba_bus = sc->sc_bus_min; 200 201 config_found_ia(sc->sc_dev, "pcibus", &pba, pcibusprint); 202 } 203 204 void 205 pcihost_init(pci_chipset_tag_t pc, void *priv) 206 { 207 pc->pc_conf_v = priv; 208 pc->pc_attach_hook = pcihost_attach_hook; 209 pc->pc_bus_maxdevs = pcihost_bus_maxdevs; 210 pc->pc_make_tag = pcihost_make_tag; 211 pc->pc_decompose_tag = pcihost_decompose_tag; 212 pc->pc_get_segment = pcihost_get_segment; 213 pc->pc_conf_read = pcihost_conf_read; 214 pc->pc_conf_write = pcihost_conf_write; 215 pc->pc_conf_hook = pcihost_conf_hook; 216 pc->pc_conf_interrupt = pcihost_conf_interrupt; 217 218 pc->pc_intr_v = priv; 219 pc->pc_intr_map = pcihost_intr_map; 220 pc->pc_intr_string = pcihost_intr_string; 221 pc->pc_intr_evcnt = pcihost_intr_evcnt; 222 pc->pc_intr_setattr = pcihost_intr_setattr; 223 pc->pc_intr_establish = pcihost_intr_establish; 224 pc->pc_intr_disestablish = pcihost_intr_disestablish; 225 } 226 227 static int 228 pcihost_config(struct pcihost_softc *sc) 229 { 230 struct extent *ioext = NULL, *memext = NULL, *pmemext = NULL; 231 const u_int *ranges; 232 u_int probe_only; 233 int error, len; 234 235 struct pcih_bus_space * const pibs = &sc->sc_io; 236 pibs->bst = *sc->sc_bst; 237 pibs->bst.bs_cookie = pibs; 238 pibs->map = pibs->bst.bs_map; 239 pibs->flags = PCI_FLAGS_IO_OKAY; 240 pibs->bst.bs_map = pcihost_bus_space_map; 241 242 struct pcih_bus_space * const pmbs = &sc->sc_mem; 243 pmbs->bst = *sc->sc_bst; 244 pmbs->bst.bs_cookie = pmbs; 245 pmbs->map = pmbs->bst.bs_map; 246 pmbs->flags = PCI_FLAGS_MEM_OKAY; 247 pmbs->bst.bs_map = pcihost_bus_space_map; 248 249 /* 250 * If this flag is set, skip configuration of the PCI bus and use existing config. 251 */ 252 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-probe-only", &probe_only)) 253 probe_only = 0; 254 if (probe_only) 255 return 0; 256 257 ranges = fdtbus_get_prop(sc->sc_phandle, "ranges", &len); 258 if (ranges == NULL) { 259 aprint_error_dev(sc->sc_dev, "missing 'ranges' property\n"); 260 return EINVAL; 261 } 262 263 /* 264 * Each entry in the ranges table contains: 265 * - bus address (3 cells) 266 * - cpu physical address (2 cells) 267 * - size (2 cells) 268 * Total size for each entry is 28 bytes (7 cells). 269 */ 270 while (len >= 28) { 271 const uint32_t phys_hi = be32dec(&ranges[0]); 272 const uint64_t bus_phys = be64dec(&ranges[1]); 273 const uint64_t cpu_phys = be64dec(&ranges[3]); 274 const uint64_t size = be64dec(&ranges[5]); 275 276 len -= 28; 277 ranges += 7; 278 279 const bool is64 = (__SHIFTOUT(phys_hi, PHYS_HI_SPACE) == 280 PHYS_HI_SPACE_MEM64) ? true : false; 281 switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) { 282 case PHYS_HI_SPACE_IO: 283 if (pibs->nranges + 1 >= __arraycount(pibs->ranges)) { 284 aprint_error_dev(sc->sc_dev, "too many IO ranges\n"); 285 continue; 286 } 287 pibs->ranges[pibs->nranges].bpci = bus_phys; 288 pibs->ranges[pibs->nranges].bbus = cpu_phys; 289 pibs->ranges[pibs->nranges].size = size; 290 ++pibs->nranges; 291 if (ioext != NULL) { 292 aprint_error_dev(sc->sc_dev, "ignoring duplicate IO space range\n"); 293 continue; 294 } 295 ioext = extent_create("pciio", bus_phys, bus_phys + size - 1, NULL, 0, EX_NOWAIT); 296 aprint_verbose_dev(sc->sc_dev, 297 "IO: 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 298 bus_phys, size, cpu_phys); 299 /* reserve a PC-like legacy IO ports range, perhaps for access to VGA registers */ 300 if (bus_phys == 0 && size >= 0x10000) 301 extent_alloc_region(ioext, 0, 0x1000, EX_WAITOK); 302 break; 303 case PHYS_HI_SPACE_MEM64: 304 /* FALLTHROUGH */ 305 case PHYS_HI_SPACE_MEM32: 306 if (pmbs->nranges + 1 >= __arraycount(pmbs->ranges)) { 307 aprint_error_dev(sc->sc_dev, "too many mem ranges\n"); 308 continue; 309 } 310 /* both pmem and mem spaces are in the same tag */ 311 pmbs->ranges[pmbs->nranges].bpci = bus_phys; 312 pmbs->ranges[pmbs->nranges].bbus = cpu_phys; 313 pmbs->ranges[pmbs->nranges].size = size; 314 ++pmbs->nranges; 315 if ((phys_hi & PHYS_HI_PREFETCH) != 0 || 316 __SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64) { 317 if (pmemext != NULL) { 318 aprint_error_dev(sc->sc_dev, "ignoring duplicate mem (prefetchable) range\n"); 319 continue; 320 } 321 pmemext = extent_create("pcipmem", bus_phys, bus_phys + size - 1, NULL, 0, EX_NOWAIT); 322 aprint_verbose_dev(sc->sc_dev, 323 "MMIO (%d-bit prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 324 is64 ? 64 : 32, bus_phys, size, cpu_phys); 325 } else { 326 if (memext != NULL) { 327 aprint_error_dev(sc->sc_dev, "ignoring duplicate mem (non-prefetchable) range\n"); 328 continue; 329 } 330 memext = extent_create("pcimem", bus_phys, bus_phys + size - 1, NULL, 0, EX_NOWAIT); 331 aprint_verbose_dev(sc->sc_dev, 332 "MMIO (%d-bit non-prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 333 is64 ? 64 : 32, bus_phys, size, cpu_phys); 334 } 335 break; 336 default: 337 break; 338 } 339 } 340 341 error = pci_configure_bus(&sc->sc_pc, ioext, memext, pmemext, sc->sc_bus_min, PCIHOST_CACHELINE_SIZE); 342 343 if (ioext) 344 extent_destroy(ioext); 345 if (memext) 346 extent_destroy(memext); 347 if (pmemext) 348 extent_destroy(pmemext); 349 350 if (error) { 351 aprint_error_dev(sc->sc_dev, "configuration failed: %d\n", error); 352 return error; 353 } 354 355 return 0; 356 } 357 358 static void 359 pcihost_attach_hook(device_t parent, device_t self, 360 struct pcibus_attach_args *pba) 361 { 362 } 363 364 static int 365 pcihost_bus_maxdevs(void *v, int busno) 366 { 367 return 32; 368 } 369 370 static pcitag_t 371 pcihost_make_tag(void *v, int b, int d, int f) 372 { 373 return (b << 16) | (d << 11) | (f << 8); 374 } 375 376 static void 377 pcihost_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 378 { 379 if (bp) 380 *bp = (tag >> 16) & 0xff; 381 if (dp) 382 *dp = (tag >> 11) & 0x1f; 383 if (fp) 384 *fp = (tag >> 8) & 0x7; 385 } 386 387 static u_int 388 pcihost_get_segment(void *v) 389 { 390 struct pcihost_softc *sc = v; 391 392 return sc->sc_seg; 393 } 394 395 static pcireg_t 396 pcihost_conf_read(void *v, pcitag_t tag, int offset) 397 { 398 struct pcihost_softc *sc = v; 399 int b, d, f; 400 u_int reg; 401 402 pcihost_decompose_tag(v, tag, &b, &d, &f); 403 404 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 405 return (pcireg_t) -1; 406 407 if (sc->sc_type == PCIHOST_CAM) { 408 if (offset & ~0xff) 409 return (pcireg_t) -1; 410 reg = (b << 16) | (d << 11) | (f << 8) | offset; 411 } else if (sc->sc_type == PCIHOST_ECAM) { 412 if (offset & ~0xfff) 413 return (pcireg_t) -1; 414 reg = (b << 20) | (d << 15) | (f << 12) | offset; 415 } else { 416 return (pcireg_t) -1; 417 } 418 419 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg); 420 } 421 422 static void 423 pcihost_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 424 { 425 struct pcihost_softc *sc = v; 426 int b, d, f; 427 u_int reg; 428 429 pcihost_decompose_tag(v, tag, &b, &d, &f); 430 431 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 432 return; 433 434 if (sc->sc_type == PCIHOST_CAM) { 435 if (offset & ~0xff) 436 return; 437 reg = (b << 16) | (d << 11) | (f << 8) | offset; 438 } else if (sc->sc_type == PCIHOST_ECAM) { 439 if (offset & ~0xfff) 440 return; 441 reg = (b << 20) | (d << 15) | (f << 12) | offset; 442 } else { 443 return; 444 } 445 446 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val); 447 } 448 449 static int 450 pcihost_conf_hook(void *v, int b, int d, int f, pcireg_t id) 451 { 452 return PCI_CONF_DEFAULT; 453 } 454 455 static void 456 pcihost_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep) 457 { 458 } 459 460 static int 461 pcihost_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 462 { 463 struct pcihost_softc *sc = pa->pa_pc->pc_intr_v; 464 u_int addr_cells, interrupt_cells; 465 const u_int *imap, *imask; 466 int imaplen, imasklen; 467 u_int match[4]; 468 int index; 469 470 if (pa->pa_intrpin == 0) 471 return EINVAL; 472 473 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 474 imask = fdtbus_get_prop(sc->sc_phandle, "interrupt-map-mask", &imasklen); 475 if (imap == NULL || imask == NULL || imasklen != 16) 476 return EINVAL; 477 478 /* Convert attach args to specifier */ 479 match[0] = htobe32( 480 __SHIFTIN(pa->pa_bus, PHYS_HI_BUS) | 481 __SHIFTIN(pa->pa_device, PHYS_HI_DEVICE) | 482 __SHIFTIN(pa->pa_function, PHYS_HI_FUNCTION) 483 ) & imask[0]; 484 match[1] = htobe32(0) & imask[1]; 485 match[2] = htobe32(0) & imask[2]; 486 match[3] = htobe32(pa->pa_intrpin) & imask[3]; 487 488 index = 0; 489 while (imaplen >= 20) { 490 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 491 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 492 addr_cells = 2; 493 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 494 interrupt_cells = 0; 495 if (imaplen < (addr_cells + interrupt_cells) * 4) 496 return ENXIO; 497 498 if ((imap[0] & imask[0]) == match[0] && 499 (imap[1] & imask[1]) == match[1] && 500 (imap[2] & imask[2]) == match[2] && 501 (imap[3] & imask[3]) == match[3]) { 502 *ih = index; 503 return 0; 504 } 505 506 imap += (5 + addr_cells + interrupt_cells); 507 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 508 index++; 509 } 510 511 return EINVAL; 512 } 513 514 static const u_int * 515 pcihost_find_intr(struct pcihost_softc *sc, pci_intr_handle_t ih, int *pihandle) 516 { 517 u_int addr_cells, interrupt_cells; 518 int imaplen, index; 519 const u_int *imap; 520 521 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 522 KASSERT(imap != NULL); 523 524 index = 0; 525 while (imaplen >= 20) { 526 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 527 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 528 addr_cells = 2; 529 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 530 interrupt_cells = 0; 531 if (imaplen < (addr_cells + interrupt_cells) * 4) 532 return NULL; 533 534 if (index == ih) { 535 *pihandle = map_ihandle; 536 return imap + 5 + addr_cells; 537 } 538 539 imap += (5 + addr_cells + interrupt_cells); 540 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 541 index++; 542 } 543 544 return NULL; 545 } 546 547 static const char * 548 pcihost_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 549 { 550 const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); 551 const int vec = __SHIFTOUT(ih, ARM_PCI_INTR_MSI_VEC); 552 struct pcihost_softc *sc = v; 553 const u_int *specifier; 554 int ihandle; 555 556 if (ih & ARM_PCI_INTR_MSIX) { 557 snprintf(buf, len, "irq %d (MSI-X vec %d)", irq, vec); 558 } else if (ih & ARM_PCI_INTR_MSI) { 559 snprintf(buf, len, "irq %d (MSI vec %d)", irq, vec); 560 } else { 561 specifier = pcihost_find_intr(sc, ih & IH_INDEX_MASK, &ihandle); 562 if (specifier == NULL) 563 return NULL; 564 565 if (!fdtbus_intr_str_raw(ihandle, specifier, buf, len)) 566 return NULL; 567 } 568 569 return buf; 570 } 571 572 const struct evcnt * 573 pcihost_intr_evcnt(void *v, pci_intr_handle_t ih) 574 { 575 return NULL; 576 } 577 578 static int 579 pcihost_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 580 { 581 switch (attr) { 582 case PCI_INTR_MPSAFE: 583 if (data) 584 *ih |= IH_MPSAFE; 585 else 586 *ih &= ~IH_MPSAFE; 587 return 0; 588 default: 589 return ENODEV; 590 } 591 } 592 593 static void * 594 pcihost_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 595 int (*callback)(void *), void *arg, const char *xname) 596 { 597 struct pcihost_softc *sc = v; 598 const int flags = (ih & IH_MPSAFE) ? FDT_INTR_MPSAFE : 0; 599 const u_int *specifier; 600 int ihandle; 601 602 if ((ih & (ARM_PCI_INTR_MSI | ARM_PCI_INTR_MSIX)) != 0) 603 return arm_pci_msi_intr_establish(&sc->sc_pc, ih, ipl, callback, arg, xname); 604 605 specifier = pcihost_find_intr(sc, ih & IH_INDEX_MASK, &ihandle); 606 if (specifier == NULL) 607 return NULL; 608 609 return fdtbus_intr_establish_raw(ihandle, specifier, ipl, flags, callback, arg); 610 } 611 612 static void 613 pcihost_intr_disestablish(void *v, void *vih) 614 { 615 struct pcihost_softc *sc = v; 616 617 fdtbus_intr_disestablish(sc->sc_phandle, vih); 618 } 619 620 static int 621 pcihost_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 622 bus_space_handle_t *bshp) 623 { 624 struct pcih_bus_space * const pbs = t; 625 626 if ((pbs->flags & PCI_FLAGS_IO_OKAY) != 0) { 627 /* Force strongly ordered mapping for all I/O space */ 628 flag = _ARM_BUS_SPACE_MAP_STRONGLY_ORDERED; 629 } 630 631 for (size_t i = 0; i < pbs->nranges; i++) { 632 const bus_addr_t rmin = pbs->ranges[i].bpci; 633 const bus_addr_t rmax = pbs->ranges[i].bpci - 1 + pbs->ranges[i].size; 634 if ((bpa >= rmin) && ((bpa - 1 + size) <= rmax)) { 635 return pbs->map(t, bpa - pbs->ranges[i].bpci + pbs->ranges[i].bbus, size, flag, bshp); 636 } 637 } 638 639 return ERANGE; 640 } 641
Indexes created Thu Oct 02 14:10:14 GMT 2025