pcihost_fdt.c revision 1.9
1 /* $NetBSD: pcihost_fdt.c,v 1.9 2019/06/12 10:13:44 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pcihost_fdt.c,v 1.9 2019/06/12 10:13:44 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/extent.h> 39 #include <sys/queue.h> 40 #include <sys/mutex.h> 41 #include <sys/kmem.h> 42 43 #include <machine/cpu.h> 44 45 #include <arm/cpufunc.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pciconf.h> 50 51 #include <dev/fdt/fdtvar.h> 52 53 #include <arm/pci/pci_msi_machdep.h> 54 #include <arm/fdt/pcihost_fdtvar.h> 55 56 #define IH_INDEX_MASK 0x0000ffff 57 #define IH_MPSAFE 0x80000000 58 59 #define PCIHOST_DEFAULT_BUS_MIN 0 60 #define PCIHOST_DEFAULT_BUS_MAX 255 61 62 #define PCIHOST_CACHELINE_SIZE arm_dcache_align 63 64 int pcihost_segment = 0; 65 66 static int pcihost_match(device_t, cfdata_t, void *); 67 static void pcihost_attach(device_t, device_t, void *); 68 69 static int pcihost_config(struct pcihost_softc *); 70 71 static void pcihost_attach_hook(device_t, device_t, 72 struct pcibus_attach_args *); 73 static int pcihost_bus_maxdevs(void *, int); 74 static pcitag_t pcihost_make_tag(void *, int, int, int); 75 static void pcihost_decompose_tag(void *, pcitag_t, int *, int *, int *); 76 static u_int pcihost_get_segment(void *); 77 static pcireg_t pcihost_conf_read(void *, pcitag_t, int); 78 static void pcihost_conf_write(void *, pcitag_t, int, pcireg_t); 79 static int pcihost_conf_hook(void *, int, int, int, pcireg_t); 80 static void pcihost_conf_interrupt(void *, int, int, int, int, int *); 81 82 static int pcihost_intr_map(const struct pci_attach_args *, 83 pci_intr_handle_t *); 84 static const char *pcihost_intr_string(void *, pci_intr_handle_t, 85 char *, size_t); 86 static const struct evcnt *pcihost_intr_evcnt(void *, pci_intr_handle_t); 87 static int pcihost_intr_setattr(void *, pci_intr_handle_t *, int, 88 uint64_t); 89 static void * pcihost_intr_establish(void *, pci_intr_handle_t, 90 int, int (*)(void *), void *, 91 const char *); 92 static void pcihost_intr_disestablish(void *, void *); 93 94 static int pcihost_bus_space_map(void *, bus_addr_t, bus_size_t, 95 int, bus_space_handle_t *); 96 97 CFATTACH_DECL_NEW(pcihost_fdt, sizeof(struct pcihost_softc), 98 pcihost_match, pcihost_attach, NULL, NULL); 99 100 static const struct of_compat_data compat_data[] = { 101 { "pci-host-cam-generic", PCIHOST_CAM }, 102 { "pci-host-ecam-generic", PCIHOST_ECAM }, 103 { NULL, 0 } 104 }; 105 106 static int 107 pcihost_match(device_t parent, cfdata_t cf, void *aux) 108 { 109 struct fdt_attach_args * const faa = aux; 110 111 return of_match_compat_data(faa->faa_phandle, compat_data); 112 } 113 114 static void 115 pcihost_attach(device_t parent, device_t self, void *aux) 116 { 117 struct pcihost_softc * const sc = device_private(self); 118 struct fdt_attach_args * const faa = aux; 119 bus_addr_t cs_addr; 120 bus_size_t cs_size; 121 int error; 122 123 if (fdtbus_get_reg(faa->faa_phandle, 0, &cs_addr, &cs_size) != 0) { 124 aprint_error(": couldn't get registers\n"); 125 return; 126 } 127 128 sc->sc_dev = self; 129 sc->sc_dmat = faa->faa_dmat; 130 sc->sc_bst = faa->faa_bst; 131 sc->sc_phandle = faa->faa_phandle; 132 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 0, &sc->sc_bsh); 133 if (error) { 134 aprint_error(": couldn't map registers: %d\n", error); 135 return; 136 } 137 sc->sc_type = of_search_compatible(sc->sc_phandle, compat_data)->data; 138 139 #ifdef __HAVE_PCI_MSI_MSIX 140 if (sc->sc_type == PCIHOST_ECAM) { 141 sc->sc_pci_flags |= PCI_FLAGS_MSI_OKAY; 142 sc->sc_pci_flags |= PCI_FLAGS_MSIX_OKAY; 143 } 144 #endif 145 146 aprint_naive("\n"); 147 aprint_normal(": Generic PCI host controller\n"); 148 149 pcihost_init(&sc->sc_pc, sc); 150 pcihost_init2(sc); 151 } 152 153 void 154 pcihost_init2(struct pcihost_softc *sc) 155 { 156 struct pcibus_attach_args pba; 157 const u_int *data; 158 int len; 159 160 if ((data = fdtbus_get_prop(sc->sc_phandle, "bus-range", &len)) != NULL) { 161 if (len != 8) { 162 aprint_error_dev(sc->sc_dev, "malformed 'bus-range' property\n"); 163 return; 164 } 165 sc->sc_bus_min = be32toh(data[0]); 166 sc->sc_bus_max = be32toh(data[1]); 167 } else { 168 sc->sc_bus_min = PCIHOST_DEFAULT_BUS_MIN; 169 sc->sc_bus_max = PCIHOST_DEFAULT_BUS_MAX; 170 } 171 172 /* 173 * Assign a fixed PCI segment ("domain") number. If the property is not 174 * present, assign one. The binding spec says if this property is used to 175 * assign static segment numbers, all host bridges should have segments 176 * astatic assigned to prevent overlaps. 177 */ 178 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-domain", &sc->sc_seg)) 179 sc->sc_seg = pcihost_segment++; 180 181 if (pcihost_config(sc) != 0) 182 return; 183 184 memset(&pba, 0, sizeof(pba)); 185 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 186 PCI_FLAGS_MRM_OKAY | 187 PCI_FLAGS_MWI_OKAY | 188 sc->sc_pci_flags; 189 pba.pba_iot = &sc->sc_io.bst; 190 pba.pba_memt = &sc->sc_mem.bst; 191 pba.pba_dmat = sc->sc_dmat; 192 #ifdef _PCI_HAVE_DMA64 193 pba.pba_dmat64 = sc->sc_dmat; 194 #endif 195 pba.pba_pc = &sc->sc_pc; 196 pba.pba_bus = sc->sc_bus_min; 197 198 config_found_ia(sc->sc_dev, "pcibus", &pba, pcibusprint); 199 } 200 201 void 202 pcihost_init(pci_chipset_tag_t pc, void *priv) 203 { 204 pc->pc_conf_v = priv; 205 pc->pc_attach_hook = pcihost_attach_hook; 206 pc->pc_bus_maxdevs = pcihost_bus_maxdevs; 207 pc->pc_make_tag = pcihost_make_tag; 208 pc->pc_decompose_tag = pcihost_decompose_tag; 209 pc->pc_get_segment = pcihost_get_segment; 210 pc->pc_conf_read = pcihost_conf_read; 211 pc->pc_conf_write = pcihost_conf_write; 212 pc->pc_conf_hook = pcihost_conf_hook; 213 pc->pc_conf_interrupt = pcihost_conf_interrupt; 214 215 pc->pc_intr_v = priv; 216 pc->pc_intr_map = pcihost_intr_map; 217 pc->pc_intr_string = pcihost_intr_string; 218 pc->pc_intr_evcnt = pcihost_intr_evcnt; 219 pc->pc_intr_setattr = pcihost_intr_setattr; 220 pc->pc_intr_establish = pcihost_intr_establish; 221 pc->pc_intr_disestablish = pcihost_intr_disestablish; 222 } 223 224 static int 225 pcihost_config(struct pcihost_softc *sc) 226 { 227 struct extent *ioext = NULL, *memext = NULL, *pmemext = NULL; 228 const u_int *ranges; 229 u_int probe_only; 230 int error, len; 231 bool swap; 232 233 struct pcih_bus_space * const pibs = &sc->sc_io; 234 pibs->bst = *sc->sc_bst; 235 pibs->bst.bs_cookie = pibs; 236 pibs->map = pibs->bst.bs_map; 237 pibs->bst.bs_map = pcihost_bus_space_map; 238 239 struct pcih_bus_space * const pmbs = &sc->sc_mem; 240 pmbs->bst = *sc->sc_bst; 241 pmbs->bst.bs_cookie = pmbs; 242 pmbs->map = pmbs->bst.bs_map; 243 pmbs->bst.bs_map = pcihost_bus_space_map; 244 245 /* 246 * If this flag is set, skip configuration of the PCI bus and use existing config. 247 */ 248 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-probe-only", &probe_only)) 249 probe_only = 0; 250 if (probe_only) 251 return 0; 252 253 if (sc->sc_pci_ranges != NULL) { 254 ranges = sc->sc_pci_ranges; 255 len = sc->sc_pci_ranges_cells * 4; 256 swap = false; 257 } else { 258 ranges = fdtbus_get_prop(sc->sc_phandle, "ranges", &len); 259 if (ranges == NULL) { 260 aprint_error_dev(sc->sc_dev, "missing 'ranges' property\n"); 261 return EINVAL; 262 } 263 swap = true; 264 } 265 266 /* 267 * Each entry in the ranges table contains: 268 * - bus address (3 cells) 269 * - cpu physical address (2 cells) 270 * - size (2 cells) 271 * Total size for each entry is 28 bytes (7 cells). 272 */ 273 while (len >= 28) { 274 #define DECODE32(x,o) (swap ? be32dec(&(x)[o]) : (x)[o]) 275 #define DECODE64(x,o) (swap ? be64dec(&(x)[o]) : (((uint64_t)((x)[(o)+0]) << 32) + (x)[(o)+1])) 276 const uint32_t phys_hi = DECODE32(ranges, 0); 277 const uint64_t bus_phys = DECODE64(ranges, 1); 278 const uint64_t cpu_phys = DECODE64(ranges, 3); 279 const uint64_t size = DECODE64(ranges, 5); 280 #undef DECODE32 281 #undef DECODE64 282 283 len -= 28; 284 ranges += 7; 285 286 const bool is64 = (__SHIFTOUT(phys_hi, PHYS_HI_SPACE) == 287 PHYS_HI_SPACE_MEM64) ? true : false; 288 switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) { 289 case PHYS_HI_SPACE_IO: 290 if (pibs->nranges + 1 >= __arraycount(pibs->ranges)) { 291 aprint_error_dev(sc->sc_dev, "too many IO ranges\n"); 292 continue; 293 } 294 pibs->ranges[pibs->nranges].bpci = bus_phys; 295 pibs->ranges[pibs->nranges].bbus = cpu_phys; 296 pibs->ranges[pibs->nranges].size = size; 297 ++pibs->nranges; 298 if (ioext != NULL) { 299 aprint_error_dev(sc->sc_dev, "ignoring duplicate IO space range\n"); 300 continue; 301 } 302 ioext = extent_create("pciio", bus_phys, bus_phys + size - 1, NULL, 0, EX_NOWAIT); 303 aprint_verbose_dev(sc->sc_dev, 304 "IO: 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 305 bus_phys, size, cpu_phys); 306 /* reserve a PC-like legacy IO ports range, perhaps for access to VGA registers */ 307 if (bus_phys == 0 && size >= 0x10000) 308 extent_alloc_region(ioext, 0, 0x1000, EX_WAITOK); 309 sc->sc_pci_flags |= PCI_FLAGS_IO_OKAY; 310 break; 311 case PHYS_HI_SPACE_MEM64: 312 /* FALLTHROUGH */ 313 case PHYS_HI_SPACE_MEM32: 314 if (pmbs->nranges + 1 >= __arraycount(pmbs->ranges)) { 315 aprint_error_dev(sc->sc_dev, "too many mem ranges\n"); 316 continue; 317 } 318 /* both pmem and mem spaces are in the same tag */ 319 pmbs->ranges[pmbs->nranges].bpci = bus_phys; 320 pmbs->ranges[pmbs->nranges].bbus = cpu_phys; 321 pmbs->ranges[pmbs->nranges].size = size; 322 ++pmbs->nranges; 323 if ((phys_hi & PHYS_HI_PREFETCH) != 0 || 324 __SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64) { 325 if (pmemext != NULL) { 326 aprint_error_dev(sc->sc_dev, "ignoring duplicate mem (prefetchable) range\n"); 327 continue; 328 } 329 pmemext = extent_create("pcipmem", bus_phys, bus_phys + size - 1, NULL, 0, EX_NOWAIT); 330 aprint_verbose_dev(sc->sc_dev, 331 "MMIO (%d-bit prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 332 is64 ? 64 : 32, bus_phys, size, cpu_phys); 333 } else { 334 if (memext != NULL) { 335 aprint_error_dev(sc->sc_dev, "ignoring duplicate mem (non-prefetchable) range\n"); 336 continue; 337 } 338 memext = extent_create("pcimem", bus_phys, bus_phys + size - 1, NULL, 0, EX_NOWAIT); 339 aprint_verbose_dev(sc->sc_dev, 340 "MMIO (%d-bit non-prefetchable): 0x%" PRIx64 "+0x%" PRIx64 "@0x%" PRIx64 "\n", 341 is64 ? 64 : 32, bus_phys, size, cpu_phys); 342 } 343 sc->sc_pci_flags |= PCI_FLAGS_MEM_OKAY; 344 break; 345 default: 346 break; 347 } 348 } 349 350 error = pci_configure_bus(&sc->sc_pc, ioext, memext, pmemext, sc->sc_bus_min, PCIHOST_CACHELINE_SIZE); 351 352 if (ioext) 353 extent_destroy(ioext); 354 if (memext) 355 extent_destroy(memext); 356 if (pmemext) 357 extent_destroy(pmemext); 358 359 if (error) { 360 aprint_error_dev(sc->sc_dev, "configuration failed: %d\n", error); 361 return error; 362 } 363 364 return 0; 365 } 366 367 static void 368 pcihost_attach_hook(device_t parent, device_t self, 369 struct pcibus_attach_args *pba) 370 { 371 } 372 373 static int 374 pcihost_bus_maxdevs(void *v, int busno) 375 { 376 return 32; 377 } 378 379 static pcitag_t 380 pcihost_make_tag(void *v, int b, int d, int f) 381 { 382 return (b << 16) | (d << 11) | (f << 8); 383 } 384 385 static void 386 pcihost_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 387 { 388 if (bp) 389 *bp = (tag >> 16) & 0xff; 390 if (dp) 391 *dp = (tag >> 11) & 0x1f; 392 if (fp) 393 *fp = (tag >> 8) & 0x7; 394 } 395 396 static u_int 397 pcihost_get_segment(void *v) 398 { 399 struct pcihost_softc *sc = v; 400 401 return sc->sc_seg; 402 } 403 404 static pcireg_t 405 pcihost_conf_read(void *v, pcitag_t tag, int offset) 406 { 407 struct pcihost_softc *sc = v; 408 int b, d, f; 409 u_int reg; 410 411 pcihost_decompose_tag(v, tag, &b, &d, &f); 412 413 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 414 return (pcireg_t) -1; 415 416 if (sc->sc_type == PCIHOST_CAM) { 417 if (offset & ~0xff) 418 return (pcireg_t) -1; 419 reg = (b << 16) | (d << 11) | (f << 8) | offset; 420 } else if (sc->sc_type == PCIHOST_ECAM) { 421 if (offset & ~0xfff) 422 return (pcireg_t) -1; 423 reg = (b << 20) | (d << 15) | (f << 12) | offset; 424 } else { 425 return (pcireg_t) -1; 426 } 427 428 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg); 429 } 430 431 static void 432 pcihost_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 433 { 434 struct pcihost_softc *sc = v; 435 int b, d, f; 436 u_int reg; 437 438 pcihost_decompose_tag(v, tag, &b, &d, &f); 439 440 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 441 return; 442 443 if (sc->sc_type == PCIHOST_CAM) { 444 if (offset & ~0xff) 445 return; 446 reg = (b << 16) | (d << 11) | (f << 8) | offset; 447 } else if (sc->sc_type == PCIHOST_ECAM) { 448 if (offset & ~0xfff) 449 return; 450 reg = (b << 20) | (d << 15) | (f << 12) | offset; 451 } else { 452 return; 453 } 454 455 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val); 456 } 457 458 static int 459 pcihost_conf_hook(void *v, int b, int d, int f, pcireg_t id) 460 { 461 return PCI_CONF_DEFAULT; 462 } 463 464 static void 465 pcihost_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep) 466 { 467 } 468 469 static int 470 pcihost_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 471 { 472 struct pcihost_softc *sc = pa->pa_pc->pc_intr_v; 473 u_int addr_cells, interrupt_cells; 474 const u_int *imap, *imask; 475 int imaplen, imasklen; 476 u_int match[4]; 477 int index; 478 479 if (pa->pa_intrpin == 0) 480 return EINVAL; 481 482 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 483 imask = fdtbus_get_prop(sc->sc_phandle, "interrupt-map-mask", &imasklen); 484 if (imap == NULL || imask == NULL || imasklen != 16) 485 return EINVAL; 486 487 /* Convert attach args to specifier */ 488 match[0] = htobe32( 489 __SHIFTIN(pa->pa_bus, PHYS_HI_BUS) | 490 __SHIFTIN(pa->pa_device, PHYS_HI_DEVICE) | 491 __SHIFTIN(pa->pa_function, PHYS_HI_FUNCTION) 492 ) & imask[0]; 493 match[1] = htobe32(0) & imask[1]; 494 match[2] = htobe32(0) & imask[2]; 495 match[3] = htobe32(pa->pa_intrpin) & imask[3]; 496 497 index = 0; 498 while (imaplen >= 20) { 499 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 500 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 501 addr_cells = 2; 502 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 503 interrupt_cells = 0; 504 if (imaplen < (addr_cells + interrupt_cells) * 4) 505 return ENXIO; 506 507 if ((imap[0] & imask[0]) == match[0] && 508 (imap[1] & imask[1]) == match[1] && 509 (imap[2] & imask[2]) == match[2] && 510 (imap[3] & imask[3]) == match[3]) { 511 *ih = index; 512 return 0; 513 } 514 515 imap += (5 + addr_cells + interrupt_cells); 516 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 517 index++; 518 } 519 520 return EINVAL; 521 } 522 523 static const u_int * 524 pcihost_find_intr(struct pcihost_softc *sc, pci_intr_handle_t ih, int *pihandle) 525 { 526 u_int addr_cells, interrupt_cells; 527 int imaplen, index; 528 const u_int *imap; 529 530 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 531 KASSERT(imap != NULL); 532 533 index = 0; 534 while (imaplen >= 20) { 535 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 536 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 537 addr_cells = 2; 538 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 539 interrupt_cells = 0; 540 if (imaplen < (addr_cells + interrupt_cells) * 4) 541 return NULL; 542 543 if (index == ih) { 544 *pihandle = map_ihandle; 545 return imap + 5 + addr_cells; 546 } 547 548 imap += (5 + addr_cells + interrupt_cells); 549 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 550 index++; 551 } 552 553 return NULL; 554 } 555 556 static const char * 557 pcihost_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 558 { 559 const int irq = __SHIFTOUT(ih, ARM_PCI_INTR_IRQ); 560 const int vec = __SHIFTOUT(ih, ARM_PCI_INTR_MSI_VEC); 561 struct pcihost_softc *sc = v; 562 const u_int *specifier; 563 int ihandle; 564 565 if (ih & ARM_PCI_INTR_MSIX) { 566 snprintf(buf, len, "irq %d (MSI-X vec %d)", irq, vec); 567 } else if (ih & ARM_PCI_INTR_MSI) { 568 snprintf(buf, len, "irq %d (MSI vec %d)", irq, vec); 569 } else { 570 specifier = pcihost_find_intr(sc, ih & IH_INDEX_MASK, &ihandle); 571 if (specifier == NULL) 572 return NULL; 573 574 if (!fdtbus_intr_str_raw(ihandle, specifier, buf, len)) 575 return NULL; 576 } 577 578 return buf; 579 } 580 581 const struct evcnt * 582 pcihost_intr_evcnt(void *v, pci_intr_handle_t ih) 583 { 584 return NULL; 585 } 586 587 static int 588 pcihost_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 589 { 590 switch (attr) { 591 case PCI_INTR_MPSAFE: 592 if (data) 593 *ih |= IH_MPSAFE; 594 else 595 *ih &= ~IH_MPSAFE; 596 return 0; 597 default: 598 return ENODEV; 599 } 600 } 601 602 static void * 603 pcihost_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 604 int (*callback)(void *), void *arg, const char *xname) 605 { 606 struct pcihost_softc *sc = v; 607 const int flags = (ih & IH_MPSAFE) ? FDT_INTR_MPSAFE : 0; 608 const u_int *specifier; 609 int ihandle; 610 611 if ((ih & (ARM_PCI_INTR_MSI | ARM_PCI_INTR_MSIX)) != 0) 612 return arm_pci_msi_intr_establish(&sc->sc_pc, ih, ipl, callback, arg, xname); 613 614 specifier = pcihost_find_intr(sc, ih & IH_INDEX_MASK, &ihandle); 615 if (specifier == NULL) 616 return NULL; 617 618 return fdtbus_intr_establish_raw(ihandle, specifier, ipl, flags, callback, arg); 619 } 620 621 static void 622 pcihost_intr_disestablish(void *v, void *vih) 623 { 624 struct pcihost_softc *sc = v; 625 626 fdtbus_intr_disestablish(sc->sc_phandle, vih); 627 } 628 629 static int 630 pcihost_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 631 bus_space_handle_t *bshp) 632 { 633 struct pcih_bus_space * const pbs = t; 634 635 for (size_t i = 0; i < pbs->nranges; i++) { 636 const bus_addr_t rmin = pbs->ranges[i].bpci; 637 const bus_addr_t rmax = pbs->ranges[i].bpci - 1 + pbs->ranges[i].size; 638 if ((bpa >= rmin) && ((bpa - 1 + size) <= rmax)) { 639 return pbs->map(t, bpa - pbs->ranges[i].bpci + pbs->ranges[i].bbus, size, flag, bshp); 640 } 641 } 642 643 return ERANGE; 644 } 645
Indexes created Wed Sep 24 02:09:48 GMT 2025