pmu_fdt.c revision 1.3.2.2
1 /* $NetBSD: pmu_fdt.c,v 1.3.2.2 2018/07/28 04:37:28 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pmu_fdt.c,v 1.3.2.2 2018/07/28 04:37:28 pgoyette Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/cpu.h> 38 #include <sys/interrupt.h> 39 40 #include <dev/fdt/fdtvar.h> 41 42 #if defined(__aarch64__) 43 #include <dev/tprof/tprof_armv8.h> 44 #define arm_pmu_intr armv8_pmu_intr 45 #define arm_pmu_init armv8_pmu_init 46 #elif defined(_ARM_ARCH_7) 47 #include <dev/tprof/tprof_armv7.h> 48 #define arm_pmu_intr armv7_pmu_intr 49 #define arm_pmu_init armv7_pmu_init 50 #endif 51 52 #include <arm/armreg.h> 53 54 static int pmu_fdt_match(device_t, cfdata_t, void *); 55 static void pmu_fdt_attach(device_t, device_t, void *); 56 57 static void pmu_fdt_init(device_t); 58 static int pmu_fdt_intr_distribute(const int, int, void *); 59 60 static const char * const compatible[] = { 61 "arm,armv8-pmuv3", 62 "arm,cortex-a73-pmu", 63 "arm,cortex-a72-pmu", 64 "arm,cortex-a57-pmu", 65 "arm,cortex-a53-pmu", 66 67 "arm,cortex-a35-pmu", 68 "arm,cortex-a17-pmu", 69 "arm,cortex-a12-pmu", 70 "arm,cortex-a9-pmu", 71 "arm,cortex-a8-pmu", 72 "arm,cortex-a7-pmu", 73 "arm,cortex-a5-pmu", 74 75 NULL 76 }; 77 78 struct pmu_fdt_softc { 79 device_t sc_dev; 80 int sc_phandle; 81 }; 82 83 CFATTACH_DECL_NEW(pmu_fdt, sizeof(struct pmu_fdt_softc), 84 pmu_fdt_match, pmu_fdt_attach, NULL, NULL); 85 86 static int 87 pmu_fdt_match(device_t parent, cfdata_t cf, void *aux) 88 { 89 struct fdt_attach_args * const faa = aux; 90 91 return of_match_compatible(faa->faa_phandle, compatible); 92 } 93 94 static void 95 pmu_fdt_attach(device_t parent, device_t self, void *aux) 96 { 97 struct pmu_fdt_softc * const sc = device_private(self); 98 struct fdt_attach_args * const faa = aux; 99 const int phandle = faa->faa_phandle; 100 101 aprint_naive("\n"); 102 aprint_normal(": Performance Monitor Unit\n"); 103 104 sc->sc_dev = self; 105 sc->sc_phandle = phandle; 106 107 config_interrupts(self, pmu_fdt_init); 108 } 109 110 static void 111 pmu_fdt_init(device_t self) 112 { 113 struct pmu_fdt_softc * const sc = device_private(self); 114 const int phandle = sc->sc_phandle; 115 char intrstr[128]; 116 int error, n; 117 void *ih; 118 119 for (n = 0; ; n++) { 120 ih = fdtbus_intr_establish(phandle, n, IPL_HIGH, 121 FDT_INTR_MPSAFE, arm_pmu_intr, NULL); 122 if (ih == NULL) 123 break; 124 if (!fdtbus_intr_str(phandle, n, intrstr, sizeof(intrstr))) { 125 aprint_error_dev(self, 126 "couldn't decode interrupt %u\n", n); 127 return; 128 } 129 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 130 error = pmu_fdt_intr_distribute(phandle, n, ih); 131 if (error != 0) { 132 aprint_error_dev(self, 133 "failed to distribute interrupt %u: %d\n", 134 n, error); 135 return; 136 } 137 } 138 /* We need either one IRQ (PPI), or one per CPU (SPI) */ 139 if (n == 0) { 140 aprint_error_dev(self, "couldn't establish interrupts\n"); 141 return; 142 } 143 144 error = arm_pmu_init(); 145 if (error != 0) { 146 aprint_error_dev(self, "failed to initialize PMU\n"); 147 return; 148 } 149 } 150 151 static int 152 pmu_fdt_intr_distribute(const int phandle, int index, void *ih) 153 { 154 CPU_INFO_ITERATOR cii; 155 struct cpu_info *ci; 156 bus_addr_t mpidr; 157 int len, cpunode; 158 const u_int *aff; 159 kcpuset_t *set; 160 int error; 161 162 kcpuset_create(&set, true); 163 164 if (of_hasprop(phandle, "interrupt-affinity")) { 165 aff = fdtbus_get_prop(phandle, "interrupt-affinity", &len); 166 if (len < (index + 1) * 4) 167 return EINVAL; 168 cpunode = fdtbus_get_phandle_from_native(be32toh(aff[index])); 169 if (fdtbus_get_reg(cpunode, 0, &mpidr, NULL) != 0) 170 return ENXIO; 171 for (CPU_INFO_FOREACH(cii, ci)) { 172 const uint32_t ci_mpidr = 173 __SHIFTIN(ci->ci_data.cpu_core_id, MPIDR_AFF0) | 174 __SHIFTIN(ci->ci_data.cpu_package_id, MPIDR_AFF1); 175 if (ci_mpidr == mpidr) { 176 kcpuset_set(set, cpu_index(ci)); 177 break; 178 } 179 } 180 } else { 181 kcpuset_set(set, index); 182 } 183 184 if (kcpuset_iszero(set)) { 185 kcpuset_destroy(set); 186 return ENOENT; 187 } 188 189 error = interrupt_distribute(ih, set, NULL); 190 191 kcpuset_destroy(set); 192 193 return error; 194 } 195
Indexes created Fri Oct 17 00:09:41 GMT 2025