pmu_fdt.c revision 1.3.2.3
1 /* $NetBSD: pmu_fdt.c,v 1.3.2.3 2018/09/06 06:55:26 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pmu_fdt.c,v 1.3.2.3 2018/09/06 06:55:26 pgoyette Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/cpu.h> 38 #include <sys/interrupt.h> 39 #include <sys/kmem.h> 40 41 #include <dev/fdt/fdtvar.h> 42 43 #if defined(__aarch64__) 44 #include <dev/tprof/tprof_armv8.h> 45 #define arm_pmu_intr armv8_pmu_intr 46 #define arm_pmu_init armv8_pmu_init 47 #elif defined(_ARM_ARCH_7) 48 #include <dev/tprof/tprof_armv7.h> 49 #define arm_pmu_intr armv7_pmu_intr 50 #define arm_pmu_init armv7_pmu_init 51 #endif 52 53 #include <arm/armreg.h> 54 55 static int pmu_fdt_match(device_t, cfdata_t, void *); 56 static void pmu_fdt_attach(device_t, device_t, void *); 57 58 static void pmu_fdt_init(device_t); 59 static int pmu_fdt_intr_distribute(const int, int, void *); 60 61 static const char * const compatible[] = { 62 "arm,armv8-pmuv3", 63 "arm,cortex-a73-pmu", 64 "arm,cortex-a72-pmu", 65 "arm,cortex-a57-pmu", 66 "arm,cortex-a53-pmu", 67 68 "arm,cortex-a35-pmu", 69 "arm,cortex-a17-pmu", 70 "arm,cortex-a12-pmu", 71 "arm,cortex-a9-pmu", 72 "arm,cortex-a8-pmu", 73 "arm,cortex-a7-pmu", 74 "arm,cortex-a5-pmu", 75 76 NULL 77 }; 78 79 struct pmu_fdt_softc { 80 device_t sc_dev; 81 int sc_phandle; 82 }; 83 84 CFATTACH_DECL_NEW(pmu_fdt, sizeof(struct pmu_fdt_softc), 85 pmu_fdt_match, pmu_fdt_attach, NULL, NULL); 86 87 static int 88 pmu_fdt_match(device_t parent, cfdata_t cf, void *aux) 89 { 90 struct fdt_attach_args * const faa = aux; 91 92 return of_match_compatible(faa->faa_phandle, compatible); 93 } 94 95 static void 96 pmu_fdt_attach(device_t parent, device_t self, void *aux) 97 { 98 struct pmu_fdt_softc * const sc = device_private(self); 99 struct fdt_attach_args * const faa = aux; 100 const int phandle = faa->faa_phandle; 101 102 aprint_naive("\n"); 103 aprint_normal(": Performance Monitor Unit\n"); 104 105 sc->sc_dev = self; 106 sc->sc_phandle = phandle; 107 108 config_interrupts(self, pmu_fdt_init); 109 } 110 111 static void 112 pmu_fdt_init(device_t self) 113 { 114 struct pmu_fdt_softc * const sc = device_private(self); 115 const int phandle = sc->sc_phandle; 116 char intrstr[128]; 117 int error, n; 118 void **ih; 119 120 error = arm_pmu_init(); 121 if (error != 0) { 122 aprint_error_dev(self, "failed to initialize PMU\n"); 123 return; 124 } 125 126 ih = kmem_zalloc(sizeof(void *) * ncpu, KM_SLEEP); 127 128 for (n = 0; n < ncpu; n++) { 129 ih[n] = fdtbus_intr_establish(phandle, n, IPL_HIGH, 130 FDT_INTR_MPSAFE, arm_pmu_intr, NULL); 131 if (ih[n] == NULL) 132 break; 133 if (!fdtbus_intr_str(phandle, n, intrstr, sizeof(intrstr))) { 134 aprint_error_dev(self, 135 "couldn't decode interrupt %u\n", n); 136 goto cleanup; 137 } 138 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 139 } 140 141 /* We need either one IRQ (PPI), or one per CPU (SPI) */ 142 const int nirq = n; 143 if (nirq == 0) { 144 aprint_error_dev(self, "couldn't establish interrupts\n"); 145 goto cleanup; 146 } 147 148 /* Set interrupt affinity if we have more than one interrupt */ 149 if (nirq > 1) { 150 for (n = 0; n < nirq; n++) { 151 error = pmu_fdt_intr_distribute(phandle, n, ih[n]); 152 if (error != 0) { 153 aprint_error_dev(self, 154 "failed to distribute interrupt %u: %d\n", 155 n, error); 156 goto cleanup; 157 } 158 } 159 } 160 161 cleanup: 162 kmem_free(ih, sizeof(void *) * ncpu); 163 } 164 165 static int 166 pmu_fdt_intr_distribute(const int phandle, int index, void *ih) 167 { 168 CPU_INFO_ITERATOR cii; 169 struct cpu_info *ci; 170 bus_addr_t mpidr; 171 int len, cpunode; 172 const u_int *aff; 173 kcpuset_t *set; 174 int error; 175 176 kcpuset_create(&set, true); 177 178 if (of_hasprop(phandle, "interrupt-affinity")) { 179 aff = fdtbus_get_prop(phandle, "interrupt-affinity", &len); 180 if (len < (index + 1) * 4) 181 return EINVAL; 182 cpunode = fdtbus_get_phandle_from_native(be32toh(aff[index])); 183 if (fdtbus_get_reg(cpunode, 0, &mpidr, NULL) != 0) 184 return ENXIO; 185 for (CPU_INFO_FOREACH(cii, ci)) { 186 const uint32_t ci_mpidr = 187 __SHIFTIN(ci->ci_data.cpu_core_id, MPIDR_AFF0) | 188 __SHIFTIN(ci->ci_data.cpu_package_id, MPIDR_AFF1); 189 if (ci_mpidr == mpidr) { 190 kcpuset_set(set, cpu_index(ci)); 191 break; 192 } 193 } 194 } else { 195 kcpuset_set(set, index); 196 } 197 198 if (kcpuset_iszero(set)) { 199 kcpuset_destroy(set); 200 return ENOENT; 201 } 202 203 error = interrupt_distribute(ih, set, NULL); 204 205 kcpuset_destroy(set); 206 207 return error; 208 } 209
Indexes created Fri Oct 17 00:09:41 GMT 2025