pmu_fdt.c revision 1.8
1 /* $NetBSD: pmu_fdt.c,v 1.8 2021/01/27 03:10:19 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pmu_fdt.c,v 1.8 2021/01/27 03:10:19 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/systm.h> 36 #include <sys/kernel.h> 37 #include <sys/cpu.h> 38 #include <sys/interrupt.h> 39 #include <sys/kmem.h> 40 #include <sys/xcall.h> 41 42 #include <dev/fdt/fdtvar.h> 43 44 #if defined(__aarch64__) 45 #include <dev/tprof/tprof_armv8.h> 46 #define arm_pmu_intr armv8_pmu_intr 47 #define arm_pmu_init armv8_pmu_init 48 #elif defined(_ARM_ARCH_7) 49 #include <dev/tprof/tprof_armv7.h> 50 #define arm_pmu_intr armv7_pmu_intr 51 #define arm_pmu_init armv7_pmu_init 52 #endif 53 54 #include <arm/armreg.h> 55 56 static bool pmu_fdt_uses_ppi; 57 static int pmu_fdt_count; 58 59 static int pmu_fdt_match(device_t, cfdata_t, void *); 60 static void pmu_fdt_attach(device_t, device_t, void *); 61 62 static void pmu_fdt_init(device_t); 63 static int pmu_fdt_intr_distribute(const int, int, void *); 64 65 static const struct device_compatible_entry compat_data[] = { 66 { .compat = "arm,armv8-pmuv3" }, 67 { .compat = "arm,cortex-a73-pmu" }, 68 { .compat = "arm,cortex-a72-pmu" }, 69 { .compat = "arm,cortex-a57-pmu" }, 70 { .compat = "arm,cortex-a53-pmu" }, 71 72 { .compat = "arm,cortex-a35-pmu" }, 73 { .compat = "arm,cortex-a17-pmu" }, 74 { .compat = "arm,cortex-a12-pmu" }, 75 { .compat = "arm,cortex-a9-pmu" }, 76 { .compat = "arm,cortex-a8-pmu" }, 77 { .compat = "arm,cortex-a7-pmu" }, 78 { .compat = "arm,cortex-a5-pmu" }, 79 80 DEVICE_COMPAT_EOL 81 }; 82 83 struct pmu_fdt_softc { 84 device_t sc_dev; 85 int sc_phandle; 86 }; 87 88 CFATTACH_DECL_NEW(pmu_fdt, sizeof(struct pmu_fdt_softc), 89 pmu_fdt_match, pmu_fdt_attach, NULL, NULL); 90 91 static int 92 pmu_fdt_match(device_t parent, cfdata_t cf, void *aux) 93 { 94 struct fdt_attach_args * const faa = aux; 95 96 return of_compatible_match(faa->faa_phandle, compat_data); 97 } 98 99 static void 100 pmu_fdt_attach(device_t parent, device_t self, void *aux) 101 { 102 struct pmu_fdt_softc * const sc = device_private(self); 103 struct fdt_attach_args * const faa = aux; 104 const int phandle = faa->faa_phandle; 105 106 aprint_naive("\n"); 107 aprint_normal(": Performance Monitor Unit\n"); 108 109 sc->sc_dev = self; 110 sc->sc_phandle = phandle; 111 112 config_interrupts(self, pmu_fdt_init); 113 } 114 115 static void 116 pmu_fdt_init_cpu(void *arg1, void *arg2) 117 { 118 arm_pmu_init(); 119 } 120 121 static void 122 pmu_fdt_init(device_t self) 123 { 124 struct pmu_fdt_softc * const sc = device_private(self); 125 const int phandle = sc->sc_phandle; 126 char intrstr[128]; 127 int error, n; 128 uint64_t xc; 129 void **ih; 130 131 if (pmu_fdt_uses_ppi && pmu_fdt_count > 0) { 132 /* 133 * Second instance of a PMU where PPIs are used. Since the PMU 134 * is already initialized and the PPI interrupt handler has 135 * already been installed, there is nothing left to do here. 136 */ 137 if (fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) 138 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 139 return; 140 } 141 142 if (pmu_fdt_count == 0) { 143 xc = xc_broadcast(0, pmu_fdt_init_cpu, NULL, NULL); 144 xc_wait(xc); 145 } 146 147 ih = kmem_zalloc(sizeof(void *) * ncpu, KM_SLEEP); 148 149 for (n = 0; n < ncpu; n++) { 150 ih[n] = fdtbus_intr_establish_xname(phandle, n, IPL_HIGH, 151 FDT_INTR_MPSAFE, arm_pmu_intr, NULL, device_xname(self)); 152 if (ih[n] == NULL) 153 break; 154 if (!fdtbus_intr_str(phandle, n, intrstr, sizeof(intrstr))) { 155 aprint_error_dev(self, 156 "couldn't decode interrupt %u\n", n); 157 goto cleanup; 158 } 159 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 160 } 161 162 /* We need either one IRQ (PPI), or one per CPU (SPI) */ 163 const int nirq = n; 164 if (nirq == 0) { 165 aprint_error_dev(self, "couldn't establish interrupts\n"); 166 goto cleanup; 167 } 168 169 /* Set interrupt affinity if we have more than one interrupt */ 170 if (nirq > 1) { 171 for (n = 0; n < nirq; n++) { 172 error = pmu_fdt_intr_distribute(phandle, n, ih[n]); 173 if (error != 0) { 174 aprint_error_dev(self, 175 "failed to distribute interrupt %u: %d\n", 176 n, error); 177 goto cleanup; 178 } 179 } 180 } 181 182 pmu_fdt_count++; 183 pmu_fdt_uses_ppi = nirq == 1 && ncpu > 1; 184 185 cleanup: 186 kmem_free(ih, sizeof(void *) * ncpu); 187 } 188 189 static int 190 pmu_fdt_intr_distribute(const int phandle, int index, void *ih) 191 { 192 CPU_INFO_ITERATOR cii; 193 struct cpu_info *ci; 194 bus_addr_t mpidr; 195 int len, cpunode; 196 const u_int *aff; 197 kcpuset_t *set; 198 int error; 199 200 kcpuset_create(&set, true); 201 202 if (of_hasprop(phandle, "interrupt-affinity")) { 203 aff = fdtbus_get_prop(phandle, "interrupt-affinity", &len); 204 if (len < (index + 1) * 4) 205 return EINVAL; 206 cpunode = fdtbus_get_phandle_from_native(be32toh(aff[index])); 207 if (fdtbus_get_reg(cpunode, 0, &mpidr, NULL) != 0) 208 return ENXIO; 209 for (CPU_INFO_FOREACH(cii, ci)) { 210 const uint32_t ci_mpidr = 211 __SHIFTIN(ci->ci_core_id, MPIDR_AFF0) | 212 __SHIFTIN(ci->ci_package_id, MPIDR_AFF1); 213 if (ci_mpidr == mpidr) { 214 kcpuset_set(set, cpu_index(ci)); 215 break; 216 } 217 } 218 } else { 219 kcpuset_set(set, index); 220 } 221 222 if (kcpuset_iszero(set)) { 223 kcpuset_destroy(set); 224 return ENOENT; 225 } 226 227 error = interrupt_distribute(ih, set, NULL); 228 229 kcpuset_destroy(set); 230 231 return error; 232 } 233
Indexes created Fri Oct 17 00:09:41 GMT 2025