footbridge_com.c revision 1.18 1 1.18 thorpej /* $NetBSD: footbridge_com.c,v 1.18 2006/03/26 04:39:40 thorpej Exp $ */
2 1.1 chris
3 1.1 chris /*-
4 1.1 chris * Copyright (c) 1997 Mark Brinicombe
5 1.1 chris * Copyright (c) 1997 Causality Limited
6 1.1 chris *
7 1.1 chris * Redistribution and use in source and binary forms, with or without
8 1.1 chris * modification, are permitted provided that the following conditions
9 1.1 chris * are met:
10 1.1 chris * 1. Redistributions of source code must retain the above copyright
11 1.1 chris * notice, this list of conditions and the following disclaimer.
12 1.1 chris * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 chris * notice, this list of conditions and the following disclaimer in the
14 1.1 chris * documentation and/or other materials provided with the distribution.
15 1.1 chris * 3. All advertising materials mentioning features or use of this software
16 1.1 chris * must display the following acknowledgement:
17 1.1 chris * This product includes software developed by Mark Brinicombe
18 1.1 chris * for the NetBSD Project.
19 1.1 chris * 4. The name of the author may not be used to endorse or promote products
20 1.1 chris * derived from this software without specific prior written permission.
21 1.1 chris *
22 1.1 chris * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 1.1 chris * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 1.1 chris * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 1.1 chris * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 1.1 chris * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 1.1 chris * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 1.1 chris * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 1.1 chris * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 1.1 chris * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 1.1 chris * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 1.1 chris */
33 1.1 chris
34 1.1 chris /*
35 1.1 chris * COM driver, using the footbridge UART
36 1.1 chris */
37 1.13 chris
38 1.13 chris #include <sys/cdefs.h>
39 1.18 thorpej __KERNEL_RCSID(0, "$NetBSD: footbridge_com.c,v 1.18 2006/03/26 04:39:40 thorpej Exp $");
40 1.1 chris
41 1.1 chris #include "opt_ddb.h"
42 1.11 itohy #include "opt_ddbparam.h"
43 1.1 chris
44 1.1 chris #include <sys/param.h>
45 1.1 chris #include <sys/systm.h>
46 1.1 chris #include <sys/ioctl.h>
47 1.1 chris #include <sys/select.h>
48 1.1 chris #include <sys/tty.h>
49 1.1 chris #include <sys/proc.h>
50 1.1 chris #include <sys/conf.h>
51 1.1 chris #include <sys/syslog.h>
52 1.1 chris #include <sys/device.h>
53 1.1 chris #include <sys/malloc.h>
54 1.1 chris #include <sys/termios.h>
55 1.1 chris #include <machine/bus.h>
56 1.2 matt #include <machine/intr.h>
57 1.1 chris #include <arm/footbridge/dc21285mem.h>
58 1.1 chris #include <arm/footbridge/dc21285reg.h>
59 1.1 chris #include <arm/footbridge/footbridgevar.h>
60 1.3 chris #include <arm/footbridge/footbridge.h>
61 1.1 chris
62 1.1 chris #include <dev/cons.h>
63 1.1 chris
64 1.1 chris #include "fcom.h"
65 1.1 chris
66 1.1 chris extern u_int dc21285_fclk;
67 1.1 chris
68 1.3 chris
69 1.1 chris #ifdef DDB
70 1.1 chris /*
71 1.1 chris * Define the keycode recognised as a request to call the debugger
72 1.1 chris * A value of 0 disables the feature when DDB is built in
73 1.1 chris */
74 1.1 chris #ifndef DDB_KEYCODE
75 1.1 chris #define DDB_KEYCODE 0
76 1.1 chris #endif /* DDB_KEYCODE */
77 1.1 chris #endif /* DDB */
78 1.1 chris
79 1.1 chris struct fcom_softc {
80 1.1 chris struct device sc_dev;
81 1.1 chris bus_space_tag_t sc_iot;
82 1.1 chris bus_space_handle_t sc_ioh;
83 1.1 chris void *sc_ih;
84 1.1 chris struct callout sc_softintr_ch;
85 1.1 chris int sc_rx_irq;
86 1.1 chris int sc_tx_irq;
87 1.1 chris int sc_hwflags;
88 1.1 chris #define HW_FLAG_CONSOLE 0x01
89 1.1 chris int sc_swflags;
90 1.1 chris int sc_l_ubrlcr;
91 1.1 chris int sc_m_ubrlcr;
92 1.1 chris int sc_h_ubrlcr;
93 1.1 chris char *sc_rxbuffer[2];
94 1.1 chris char *sc_rxbuf;
95 1.1 chris int sc_rxpos;
96 1.1 chris int sc_rxcur;
97 1.1 chris struct tty *sc_tty;
98 1.1 chris };
99 1.1 chris
100 1.1 chris #define RX_BUFFER_SIZE 0x100
101 1.1 chris
102 1.1 chris static int fcom_probe __P((struct device *, struct cfdata *, void *));
103 1.1 chris static void fcom_attach __P((struct device *, struct device *, void *));
104 1.3 chris static void fcom_softintr __P((void *));
105 1.1 chris
106 1.1 chris static int fcom_rxintr __P((void *));
107 1.1 chris /*static int fcom_txintr __P((void *));*/
108 1.1 chris
109 1.1 chris /*struct consdev;*/
110 1.1 chris /*void fcomcnprobe __P((struct consdev *));
111 1.1 chris void fcomcninit __P((struct consdev *));*/
112 1.1 chris int fcomcngetc __P((dev_t));
113 1.1 chris void fcomcnputc __P((dev_t, int));
114 1.1 chris void fcomcnpollc __P((dev_t, int));
115 1.1 chris
116 1.8 thorpej CFATTACH_DECL(fcom, sizeof(struct fcom_softc),
117 1.8 thorpej fcom_probe, fcom_attach, NULL, NULL);
118 1.1 chris
119 1.1 chris extern struct cfdriver fcom_cd;
120 1.1 chris
121 1.5 gehenna dev_type_open(fcomopen);
122 1.5 gehenna dev_type_close(fcomclose);
123 1.5 gehenna dev_type_read(fcomread);
124 1.5 gehenna dev_type_write(fcomwrite);
125 1.5 gehenna dev_type_ioctl(fcomioctl);
126 1.5 gehenna dev_type_tty(fcomtty);
127 1.5 gehenna dev_type_poll(fcompoll);
128 1.5 gehenna
129 1.5 gehenna const struct cdevsw fcom_cdevsw = {
130 1.5 gehenna fcomopen, fcomclose, fcomread, fcomwrite, fcomioctl,
131 1.9 jdolecek nostop, fcomtty, fcompoll, nommap, ttykqfilter, D_TTY
132 1.5 gehenna };
133 1.5 gehenna
134 1.1 chris void fcominit __P((bus_space_tag_t, bus_space_handle_t, int, int));
135 1.1 chris void fcominitcons __P((bus_space_tag_t, bus_space_handle_t));
136 1.1 chris
137 1.1 chris bus_space_tag_t fcomconstag;
138 1.1 chris bus_space_handle_t fcomconsioh;
139 1.1 chris extern int comcnmode;
140 1.1 chris extern int comcnspeed;
141 1.1 chris
142 1.1 chris #define COMUNIT(x) (minor(x))
143 1.1 chris #ifndef CONUNIT
144 1.1 chris #define CONUNIT 0
145 1.1 chris #endif
146 1.1 chris
147 1.1 chris /*
148 1.1 chris * The console is set up at init time, well in advance of the reset of the
149 1.1 chris * system and thus we have a private bus space tag for the console.
150 1.1 chris *
151 1.1 chris * The tag is provided by fcom_io.c and fcom_io_asm.S
152 1.1 chris */
153 1.1 chris extern struct bus_space fcomcons_bs_tag;
154 1.1 chris
155 1.1 chris /*
156 1.1 chris * int fcom_probe(struct device *parent, struct cfdata *cf, void *aux)
157 1.1 chris *
158 1.1 chris * Make sure we are trying to attach a com device and then
159 1.1 chris * probe for one.
160 1.1 chris */
161 1.1 chris
162 1.1 chris static int
163 1.1 chris fcom_probe(parent, cf, aux)
164 1.1 chris struct device *parent;
165 1.1 chris struct cfdata *cf;
166 1.1 chris void *aux;
167 1.1 chris {
168 1.1 chris union footbridge_attach_args *fba = aux;
169 1.1 chris
170 1.1 chris if (strcmp(fba->fba_name, "fcom") == 0)
171 1.1 chris return(1);
172 1.1 chris return(0);
173 1.1 chris }
174 1.1 chris
175 1.1 chris /*
176 1.1 chris * void fcom_attach(struct device *parent, struct device *self, void *aux)
177 1.1 chris *
178 1.1 chris * attach the com device
179 1.1 chris */
180 1.1 chris
181 1.1 chris static void
182 1.1 chris fcom_attach(parent, self, aux)
183 1.1 chris struct device *parent, *self;
184 1.1 chris void *aux;
185 1.1 chris {
186 1.1 chris union footbridge_attach_args *fba = aux;
187 1.1 chris struct fcom_softc *sc = (struct fcom_softc *)self;
188 1.1 chris
189 1.1 chris /* Set up the softc */
190 1.1 chris sc->sc_iot = fba->fba_fca.fca_iot;
191 1.1 chris sc->sc_ioh = fba->fba_fca.fca_ioh;
192 1.1 chris callout_init(&sc->sc_softintr_ch);
193 1.1 chris sc->sc_rx_irq = fba->fba_fca.fca_rx_irq;
194 1.1 chris sc->sc_tx_irq = fba->fba_fca.fca_tx_irq;
195 1.1 chris sc->sc_hwflags = 0;
196 1.1 chris sc->sc_swflags = 0;
197 1.1 chris
198 1.1 chris /* If we have a console tag then make a note of it */
199 1.1 chris if (fcomconstag)
200 1.1 chris sc->sc_hwflags |= HW_FLAG_CONSOLE;
201 1.1 chris
202 1.1 chris if (sc->sc_hwflags & HW_FLAG_CONSOLE) {
203 1.1 chris int major;
204 1.1 chris
205 1.1 chris /* locate the major number */
206 1.5 gehenna major = cdevsw_lookup_major(&fcom_cdevsw);
207 1.1 chris
208 1.18 thorpej cn_tab->cn_dev = makedev(major, device_unit(&sc->sc_dev));
209 1.1 chris printf(": console");
210 1.1 chris }
211 1.1 chris printf("\n");
212 1.1 chris
213 1.10 chris sc->sc_ih = footbridge_intr_claim(sc->sc_rx_irq, IPL_SERIAL,
214 1.10 chris "serial rx", fcom_rxintr, sc);
215 1.1 chris if (sc->sc_ih == NULL)
216 1.6 provos panic("%s: Cannot install rx interrupt handler",
217 1.1 chris sc->sc_dev.dv_xname);
218 1.1 chris }
219 1.1 chris
220 1.1 chris static void fcomstart __P((struct tty *));
221 1.1 chris static int fcomparam __P((struct tty *, struct termios *));
222 1.1 chris
223 1.1 chris int
224 1.16 christos fcomopen(dev, flag, mode, l)
225 1.1 chris dev_t dev;
226 1.1 chris int flag, mode;
227 1.16 christos struct lwp *l;
228 1.1 chris {
229 1.16 christos struct proc *p = l->l_proc;
230 1.1 chris struct fcom_softc *sc;
231 1.1 chris int unit = minor(dev);
232 1.1 chris struct tty *tp;
233 1.1 chris
234 1.1 chris if (unit >= fcom_cd.cd_ndevs)
235 1.1 chris return ENXIO;
236 1.1 chris sc = fcom_cd.cd_devs[unit];
237 1.1 chris if (!sc)
238 1.1 chris return ENXIO;
239 1.1 chris if (!(tp = sc->sc_tty))
240 1.1 chris sc->sc_tty = tp = ttymalloc();
241 1.1 chris if (!sc->sc_rxbuffer[0]) {
242 1.1 chris sc->sc_rxbuffer[0] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK);
243 1.1 chris sc->sc_rxbuffer[1] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK);
244 1.1 chris sc->sc_rxpos = 0;
245 1.1 chris sc->sc_rxcur = 0;
246 1.1 chris sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur];
247 1.1 chris if (!sc->sc_rxbuf)
248 1.1 chris panic("%s: Cannot allocate rx buffer memory",
249 1.1 chris sc->sc_dev.dv_xname);
250 1.1 chris }
251 1.1 chris tp->t_oproc = fcomstart;
252 1.1 chris tp->t_param = fcomparam;
253 1.1 chris tp->t_dev = dev;
254 1.1 chris if (!(tp->t_state & TS_ISOPEN && tp->t_wopen == 0)) {
255 1.1 chris ttychars(tp);
256 1.1 chris tp->t_cflag = TTYDEF_CFLAG;
257 1.1 chris tp->t_iflag = TTYDEF_IFLAG;
258 1.1 chris tp->t_oflag = TTYDEF_OFLAG;
259 1.1 chris tp->t_lflag = TTYDEF_LFLAG;
260 1.1 chris
261 1.1 chris /*
262 1.1 chris * Initialize the termios status to the defaults. Add in the
263 1.1 chris * sticky bits from TIOCSFLAGS.
264 1.1 chris */
265 1.1 chris tp->t_ispeed = 0;
266 1.1 chris if (ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE))
267 1.1 chris tp->t_ospeed = comcnspeed;
268 1.1 chris else
269 1.1 chris tp->t_ospeed = TTYDEF_SPEED;
270 1.1 chris
271 1.1 chris fcomparam(tp, &tp->t_termios);
272 1.1 chris ttsetwater(tp);
273 1.1 chris } else if ((tp->t_state&TS_XCLUDE) && suser(p->p_ucred, &p->p_acflag))
274 1.1 chris return EBUSY;
275 1.1 chris tp->t_state |= TS_CARR_ON;
276 1.1 chris
277 1.1 chris return (*tp->t_linesw->l_open)(dev, tp);
278 1.1 chris }
279 1.1 chris
280 1.1 chris int
281 1.16 christos fcomclose(dev, flag, mode, l)
282 1.1 chris dev_t dev;
283 1.1 chris int flag, mode;
284 1.16 christos struct lwp *l;
285 1.1 chris {
286 1.1 chris struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)];
287 1.1 chris struct tty *tp = sc->sc_tty;
288 1.1 chris /* XXX This is for cons.c. */
289 1.1 chris if (!ISSET(tp->t_state, TS_ISOPEN))
290 1.1 chris return (0);
291 1.1 chris
292 1.1 chris (*tp->t_linesw->l_close)(tp, flag);
293 1.1 chris ttyclose(tp);
294 1.1 chris #ifdef DIAGNOSTIC
295 1.1 chris if (sc->sc_rxbuffer[0] == NULL)
296 1.6 provos panic("fcomclose: rx buffers not allocated");
297 1.1 chris #endif /* DIAGNOSTIC */
298 1.1 chris free(sc->sc_rxbuffer[0], M_DEVBUF);
299 1.1 chris free(sc->sc_rxbuffer[1], M_DEVBUF);
300 1.1 chris sc->sc_rxbuffer[0] = NULL;
301 1.1 chris sc->sc_rxbuffer[1] = NULL;
302 1.1 chris
303 1.1 chris return 0;
304 1.1 chris }
305 1.1 chris
306 1.1 chris int
307 1.1 chris fcomread(dev, uio, flag)
308 1.1 chris dev_t dev;
309 1.1 chris struct uio *uio;
310 1.1 chris int flag;
311 1.1 chris {
312 1.1 chris struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)];
313 1.1 chris struct tty *tp = sc->sc_tty;
314 1.1 chris
315 1.1 chris return (*tp->t_linesw->l_read)(tp, uio, flag);
316 1.1 chris }
317 1.1 chris
318 1.1 chris int
319 1.1 chris fcomwrite(dev, uio, flag)
320 1.1 chris dev_t dev;
321 1.1 chris struct uio *uio;
322 1.1 chris int flag;
323 1.1 chris {
324 1.1 chris struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)];
325 1.1 chris struct tty *tp = sc->sc_tty;
326 1.1 chris
327 1.1 chris return (*tp->t_linesw->l_write)(tp, uio, flag);
328 1.1 chris }
329 1.1 chris
330 1.1 chris int
331 1.16 christos fcompoll(dev, events, l)
332 1.1 chris dev_t dev;
333 1.1 chris int events;
334 1.16 christos struct lwp *l;
335 1.1 chris {
336 1.1 chris struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)];
337 1.1 chris struct tty *tp = sc->sc_tty;
338 1.1 chris
339 1.16 christos return ((*tp->t_linesw->l_poll)(tp, events, l));
340 1.1 chris }
341 1.1 chris
342 1.1 chris int
343 1.16 christos fcomioctl(dev, cmd, data, flag, l)
344 1.1 chris dev_t dev;
345 1.1 chris u_long cmd;
346 1.1 chris caddr_t data;
347 1.1 chris int flag;
348 1.16 christos struct lwp *l;
349 1.1 chris {
350 1.16 christos struct proc *p = l->l_proc;
351 1.1 chris struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)];
352 1.1 chris struct tty *tp = sc->sc_tty;
353 1.1 chris int error;
354 1.1 chris
355 1.16 christos if ((error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l)) !=
356 1.4 atatat EPASSTHROUGH)
357 1.1 chris return error;
358 1.16 christos if ((error = ttioctl(tp, cmd, data, flag, l)) != EPASSTHROUGH)
359 1.1 chris return error;
360 1.1 chris
361 1.1 chris switch (cmd) {
362 1.1 chris case TIOCGFLAGS:
363 1.1 chris *(int *)data = sc->sc_swflags;
364 1.1 chris break;
365 1.1 chris
366 1.1 chris case TIOCSFLAGS:
367 1.1 chris error = suser(p->p_ucred, &p->p_acflag);
368 1.1 chris if (error)
369 1.1 chris return (error);
370 1.1 chris sc->sc_swflags = *(int *)data;
371 1.1 chris break;
372 1.1 chris }
373 1.1 chris
374 1.4 atatat return EPASSTHROUGH;
375 1.1 chris }
376 1.1 chris
377 1.1 chris struct tty *
378 1.1 chris fcomtty(dev)
379 1.1 chris dev_t dev;
380 1.1 chris {
381 1.1 chris struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)];
382 1.1 chris
383 1.1 chris return sc->sc_tty;
384 1.1 chris }
385 1.1 chris
386 1.1 chris static void
387 1.1 chris fcomstart(tp)
388 1.1 chris struct tty *tp;
389 1.1 chris {
390 1.1 chris struct clist *cl;
391 1.1 chris int s, len;
392 1.1 chris u_char buf[64];
393 1.1 chris int loop;
394 1.1 chris struct fcom_softc *sc = fcom_cd.cd_devs[minor(tp->t_dev)];
395 1.1 chris bus_space_tag_t iot = sc->sc_iot;
396 1.1 chris bus_space_handle_t ioh = sc->sc_ioh;
397 1.1 chris int timo;
398 1.1 chris
399 1.1 chris s = spltty();
400 1.1 chris if (tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) {
401 1.1 chris (void)splx(s);
402 1.1 chris return;
403 1.1 chris }
404 1.1 chris tp->t_state |= TS_BUSY;
405 1.1 chris (void)splx(s);
406 1.1 chris
407 1.1 chris /* s = splserial();*/
408 1.1 chris /* wait for any pending transmission to finish */
409 1.1 chris timo = 100000;
410 1.1 chris while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo)
411 1.1 chris ;
412 1.1 chris
413 1.1 chris s = splserial();
414 1.1 chris if (bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) {
415 1.1 chris tp->t_state |= TS_TIMEOUT;
416 1.1 chris callout_reset(&tp->t_rstrt_ch, 1, ttrstrt, tp);
417 1.1 chris (void)splx(s);
418 1.1 chris return;
419 1.1 chris }
420 1.1 chris
421 1.1 chris (void)splx(s);
422 1.1 chris
423 1.1 chris cl = &tp->t_outq;
424 1.1 chris len = q_to_b(cl, buf, 64);
425 1.1 chris for (loop = 0; loop < len; ++loop) {
426 1.1 chris /* s = splserial();*/
427 1.1 chris
428 1.1 chris bus_space_write_4(iot, ioh, UART_DATA, buf[loop]);
429 1.1 chris
430 1.1 chris /* wait for this transmission to complete */
431 1.1 chris timo = 100000;
432 1.1 chris while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo)
433 1.1 chris ;
434 1.1 chris /* (void)splx(s);*/
435 1.1 chris }
436 1.1 chris s = spltty();
437 1.1 chris tp->t_state &= ~TS_BUSY;
438 1.1 chris if (cl->c_cc) {
439 1.1 chris tp->t_state |= TS_TIMEOUT;
440 1.1 chris callout_reset(&tp->t_rstrt_ch, 1, ttrstrt, tp);
441 1.1 chris }
442 1.1 chris if (cl->c_cc <= tp->t_lowat) {
443 1.1 chris if (tp->t_state & TS_ASLEEP) {
444 1.1 chris tp->t_state &= ~TS_ASLEEP;
445 1.1 chris wakeup(cl);
446 1.1 chris }
447 1.1 chris selwakeup(&tp->t_wsel);
448 1.1 chris }
449 1.1 chris (void)splx(s);
450 1.1 chris }
451 1.1 chris
452 1.1 chris static int
453 1.1 chris fcomparam(tp, t)
454 1.1 chris struct tty *tp;
455 1.1 chris struct termios *t;
456 1.1 chris {
457 1.1 chris struct fcom_softc *sc = fcom_cd.cd_devs[minor(tp->t_dev)];
458 1.1 chris bus_space_tag_t iot = sc->sc_iot;
459 1.1 chris bus_space_handle_t ioh = sc->sc_ioh;
460 1.1 chris int baudrate;
461 1.1 chris int h_ubrlcr;
462 1.1 chris int m_ubrlcr;
463 1.1 chris int l_ubrlcr;
464 1.1 chris int s;
465 1.1 chris
466 1.1 chris /* check requested parameters */
467 1.1 chris if (t->c_ospeed < 0)
468 1.1 chris return (EINVAL);
469 1.1 chris if (t->c_ispeed && t->c_ispeed != t->c_ospeed)
470 1.1 chris return (EINVAL);
471 1.1 chris
472 1.1 chris switch (t->c_ospeed) {
473 1.1 chris case B1200:
474 1.1 chris case B2400:
475 1.1 chris case B4800:
476 1.1 chris case B9600:
477 1.1 chris case B19200:
478 1.1 chris case B38400:
479 1.1 chris baudrate = UART_BRD(dc21285_fclk, t->c_ospeed);
480 1.1 chris break;
481 1.1 chris default:
482 1.1 chris baudrate = UART_BRD(dc21285_fclk, 9600);
483 1.1 chris break;
484 1.1 chris }
485 1.1 chris
486 1.1 chris l_ubrlcr = baudrate & 0xff;
487 1.1 chris m_ubrlcr = (baudrate >> 8) & 0xf;
488 1.1 chris h_ubrlcr = 0;
489 1.1 chris
490 1.1 chris switch (ISSET(t->c_cflag, CSIZE)) {
491 1.1 chris case CS5:
492 1.1 chris h_ubrlcr |= UART_DATA_BITS_5;
493 1.1 chris break;
494 1.1 chris case CS6:
495 1.1 chris h_ubrlcr |= UART_DATA_BITS_6;
496 1.1 chris break;
497 1.1 chris case CS7:
498 1.1 chris h_ubrlcr |= UART_DATA_BITS_7;
499 1.1 chris break;
500 1.1 chris case CS8:
501 1.1 chris h_ubrlcr |= UART_DATA_BITS_8;
502 1.1 chris break;
503 1.1 chris }
504 1.1 chris
505 1.1 chris if (ISSET(t->c_cflag, PARENB)) {
506 1.1 chris h_ubrlcr |= UART_PARITY_ENABLE;
507 1.1 chris if (ISSET(t->c_cflag, PARODD))
508 1.1 chris h_ubrlcr |= UART_ODD_PARITY;
509 1.1 chris else
510 1.1 chris h_ubrlcr |= UART_EVEN_PARITY;
511 1.1 chris }
512 1.1 chris
513 1.1 chris if (ISSET(t->c_cflag, CSTOPB))
514 1.1 chris h_ubrlcr |= UART_STOP_BITS_2;
515 1.1 chris
516 1.1 chris bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr);
517 1.1 chris bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr);
518 1.1 chris bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr);
519 1.1 chris
520 1.1 chris s = splserial();
521 1.1 chris
522 1.1 chris sc->sc_l_ubrlcr = l_ubrlcr;
523 1.1 chris sc->sc_m_ubrlcr = m_ubrlcr;
524 1.1 chris sc->sc_h_ubrlcr = h_ubrlcr;
525 1.1 chris
526 1.1 chris /*
527 1.1 chris * For the console, always force CLOCAL and !HUPCL, so that the port
528 1.1 chris * is always active.
529 1.1 chris */
530 1.1 chris if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) ||
531 1.1 chris ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE)) {
532 1.1 chris SET(t->c_cflag, CLOCAL);
533 1.1 chris CLR(t->c_cflag, HUPCL);
534 1.1 chris }
535 1.1 chris
536 1.1 chris /* and copy to tty */
537 1.1 chris tp->t_ispeed = 0;
538 1.1 chris tp->t_ospeed = t->c_ospeed;
539 1.1 chris tp->t_cflag = t->c_cflag;
540 1.1 chris
541 1.1 chris bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr);
542 1.1 chris bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr);
543 1.1 chris bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr);
544 1.1 chris
545 1.1 chris (void)splx(s);
546 1.1 chris
547 1.1 chris return (0);
548 1.1 chris }
549 1.1 chris
550 1.1 chris static int softint_scheduled = 0;
551 1.1 chris
552 1.1 chris static void
553 1.3 chris fcom_softintr(arg)
554 1.3 chris void *arg;
555 1.1 chris {
556 1.3 chris struct fcom_softc *sc = arg;
557 1.1 chris struct tty *tp = sc->sc_tty;
558 1.1 chris int s;
559 1.1 chris int loop;
560 1.1 chris int len;
561 1.1 chris char *ptr;
562 1.1 chris
563 1.1 chris s = spltty();
564 1.1 chris ptr = sc->sc_rxbuf;
565 1.1 chris len = sc->sc_rxpos;
566 1.1 chris sc->sc_rxcur ^= 1;
567 1.1 chris sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur];
568 1.1 chris sc->sc_rxpos = 0;
569 1.1 chris (void)splx(s);
570 1.1 chris
571 1.1 chris for (loop = 0; loop < len; ++loop)
572 1.1 chris (*tp->t_linesw->l_rint)(ptr[loop], tp);
573 1.1 chris softint_scheduled = 0;
574 1.1 chris }
575 1.1 chris
576 1.1 chris #if 0
577 1.1 chris static int
578 1.1 chris fcom_txintr(arg)
579 1.1 chris void *arg;
580 1.1 chris {
581 1.1 chris /* struct fcom_softc *sc = arg;*/
582 1.1 chris
583 1.1 chris printf("fcom_txintr()\n");
584 1.1 chris return(0);
585 1.1 chris }
586 1.1 chris #endif
587 1.1 chris
588 1.1 chris static int
589 1.1 chris fcom_rxintr(arg)
590 1.1 chris void *arg;
591 1.1 chris {
592 1.1 chris struct fcom_softc *sc = arg;
593 1.1 chris bus_space_tag_t iot = sc->sc_iot;
594 1.1 chris bus_space_handle_t ioh = sc->sc_ioh;
595 1.1 chris struct tty *tp = sc->sc_tty;
596 1.1 chris int status;
597 1.1 chris int byte;
598 1.1 chris
599 1.1 chris do {
600 1.1 chris status = bus_space_read_4(iot, ioh, UART_FLAGS);
601 1.1 chris if ((status & UART_RX_FULL))
602 1.1 chris break;
603 1.1 chris byte = bus_space_read_4(iot, ioh, UART_DATA);
604 1.1 chris status = bus_space_read_4(iot, ioh, UART_RX_STAT);
605 1.11 itohy #if defined(DDB) && DDB_KEYCODE > 0
606 1.1 chris /*
607 1.1 chris * Temporary hack so that I can force the kernel into
608 1.1 chris * the debugger via the serial port
609 1.1 chris */
610 1.1 chris if (byte == DDB_KEYCODE) Debugger();
611 1.1 chris #endif
612 1.1 chris if (tp && (tp->t_state & TS_ISOPEN))
613 1.1 chris if (sc->sc_rxpos < RX_BUFFER_SIZE) {
614 1.1 chris sc->sc_rxbuf[sc->sc_rxpos++] = byte;
615 1.1 chris if (!softint_scheduled) {
616 1.1 chris softint_scheduled = 1;
617 1.1 chris callout_reset(&sc->sc_softintr_ch,
618 1.1 chris 1, fcom_softintr, sc);
619 1.1 chris }
620 1.1 chris }
621 1.1 chris } while (1);
622 1.1 chris return(0);
623 1.1 chris }
624 1.1 chris
625 1.1 chris #if 0
626 1.1 chris void
627 1.1 chris fcom_iflush(sc)
628 1.1 chris struct fcom_softc *sc;
629 1.1 chris {
630 1.1 chris bus_space_tag_t iot = sc->sc_iot;
631 1.1 chris bus_space_handle_t ioh = sc->sc_ioh;
632 1.1 chris
633 1.1 chris /* flush any pending I/O */
634 1.1 chris while (!ISSET(bus_space_read_4(iot, ioh, UART_FLAGS), UART_RX_FULL))
635 1.1 chris (void) bus_space_read_4(iot, ioh, UART_DATA);
636 1.1 chris }
637 1.1 chris #endif
638 1.1 chris
639 1.1 chris /*
640 1.1 chris * Following are all routines needed for COM to act as console
641 1.1 chris */
642 1.1 chris
643 1.1 chris #if 0
644 1.1 chris void
645 1.1 chris fcomcnprobe(cp)
646 1.1 chris struct consdev *cp;
647 1.1 chris {
648 1.1 chris int major;
649 1.1 chris
650 1.1 chris /* Serial console is always present so no probe */
651 1.1 chris
652 1.1 chris /* locate the major number */
653 1.5 gehenna major = cdevsw_lookup_major(&fcom_cdevsw);
654 1.1 chris
655 1.1 chris /* initialize required fields */
656 1.1 chris cp->cn_dev = makedev(major, CONUNIT);
657 1.1 chris cp->cn_pri = CN_REMOTE; /* Force a serial port console */
658 1.1 chris }
659 1.1 chris
660 1.1 chris void
661 1.1 chris fcomcninit(cp)
662 1.1 chris struct consdev *cp;
663 1.1 chris {
664 1.1 chris fcomconstag = &fcomcons_bs_tag;
665 1.1 chris
666 1.1 chris if (bus_space_map(fcomconstag, DC21285_ARMCSR_BASE, DC21285_ARMCSR_SIZE, 0, &fcomconsioh))
667 1.1 chris panic("fcomcninit: mapping failed");
668 1.1 chris
669 1.1 chris fcominitcons(fcomconstag, fcomconsioh);
670 1.1 chris }
671 1.1 chris #endif
672 1.1 chris
673 1.1 chris int
674 1.1 chris fcomcnattach(iobase, rate, cflag)
675 1.1 chris u_int iobase;
676 1.1 chris int rate;
677 1.1 chris tcflag_t cflag;
678 1.1 chris {
679 1.1 chris static struct consdev fcomcons = {
680 1.1 chris NULL, NULL, fcomcngetc, fcomcnputc, fcomcnpollc, NULL,
681 1.12 skrll NULL, NULL, NODEV, CN_NORMAL
682 1.1 chris };
683 1.1 chris
684 1.1 chris fcomconstag = &fcomcons_bs_tag;
685 1.1 chris
686 1.1 chris if (bus_space_map(fcomconstag, iobase, DC21285_ARMCSR_SIZE,
687 1.1 chris 0, &fcomconsioh))
688 1.1 chris panic("fcomcninit: mapping failed");
689 1.1 chris
690 1.1 chris fcominit(fcomconstag, fcomconsioh, rate, cflag);
691 1.1 chris
692 1.1 chris cn_tab = &fcomcons;
693 1.1 chris
694 1.1 chris /* comcnspeed = rate;
695 1.1 chris comcnmode = cflag;*/
696 1.1 chris return (0);
697 1.1 chris }
698 1.1 chris
699 1.1 chris int
700 1.1 chris fcomcndetach(void)
701 1.1 chris {
702 1.1 chris bus_space_unmap(fcomconstag, fcomconsioh, DC21285_ARMCSR_SIZE);
703 1.1 chris
704 1.1 chris cn_tab = NULL;
705 1.1 chris return (0);
706 1.1 chris }
707 1.1 chris
708 1.1 chris /*
709 1.1 chris * Initialize UART to known state.
710 1.1 chris */
711 1.1 chris void
712 1.1 chris fcominit(iot, ioh, rate, mode)
713 1.1 chris bus_space_tag_t iot;
714 1.1 chris bus_space_handle_t ioh;
715 1.1 chris int rate;
716 1.1 chris int mode;
717 1.1 chris {
718 1.1 chris int baudrate;
719 1.1 chris int h_ubrlcr;
720 1.1 chris int m_ubrlcr;
721 1.1 chris int l_ubrlcr;
722 1.1 chris
723 1.1 chris switch (rate) {
724 1.1 chris case B1200:
725 1.1 chris case B2400:
726 1.1 chris case B4800:
727 1.1 chris case B9600:
728 1.1 chris case B19200:
729 1.1 chris case B38400:
730 1.1 chris baudrate = UART_BRD(dc21285_fclk, rate);
731 1.1 chris break;
732 1.1 chris default:
733 1.1 chris baudrate = UART_BRD(dc21285_fclk, 9600);
734 1.1 chris break;
735 1.1 chris }
736 1.1 chris
737 1.1 chris h_ubrlcr = 0;
738 1.1 chris switch (mode & CSIZE) {
739 1.1 chris case CS5:
740 1.1 chris h_ubrlcr |= UART_DATA_BITS_5;
741 1.1 chris break;
742 1.1 chris case CS6:
743 1.1 chris h_ubrlcr |= UART_DATA_BITS_6;
744 1.1 chris break;
745 1.1 chris case CS7:
746 1.1 chris h_ubrlcr |= UART_DATA_BITS_7;
747 1.1 chris break;
748 1.1 chris case CS8:
749 1.1 chris h_ubrlcr |= UART_DATA_BITS_8;
750 1.1 chris break;
751 1.1 chris }
752 1.1 chris
753 1.1 chris if (mode & PARENB)
754 1.1 chris h_ubrlcr |= UART_PARITY_ENABLE;
755 1.1 chris if (mode & PARODD)
756 1.1 chris h_ubrlcr |= UART_ODD_PARITY;
757 1.1 chris else
758 1.1 chris h_ubrlcr |= UART_EVEN_PARITY;
759 1.1 chris
760 1.1 chris if (mode & CSTOPB)
761 1.1 chris h_ubrlcr |= UART_STOP_BITS_2;
762 1.1 chris
763 1.1 chris m_ubrlcr = (baudrate >> 8) & 0xf;
764 1.1 chris l_ubrlcr = baudrate & 0xff;
765 1.1 chris
766 1.1 chris bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr);
767 1.1 chris bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr);
768 1.1 chris bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr);
769 1.1 chris }
770 1.1 chris #if 0
771 1.1 chris /*
772 1.1 chris * Set UART for console use. Do normal init, then enable interrupts.
773 1.1 chris */
774 1.1 chris void
775 1.1 chris fcominitcons(iot, ioh)
776 1.1 chris bus_space_tag_t iot;
777 1.1 chris bus_space_handle_t ioh;
778 1.1 chris {
779 1.1 chris int s = splserial();
780 1.1 chris
781 1.1 chris fcominit(iot, ioh, comcnspeed, comcnmode);
782 1.1 chris
783 1.1 chris delay(10000);
784 1.1 chris
785 1.1 chris (void)splx(s);
786 1.1 chris }
787 1.1 chris #endif
788 1.1 chris
789 1.1 chris int
790 1.1 chris fcomcngetc(dev)
791 1.1 chris dev_t dev;
792 1.1 chris {
793 1.1 chris int s = splserial();
794 1.1 chris bus_space_tag_t iot = fcomconstag;
795 1.1 chris bus_space_handle_t ioh = fcomconsioh;
796 1.1 chris u_char stat, c;
797 1.1 chris
798 1.1 chris while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_RX_FULL) != 0)
799 1.1 chris ;
800 1.1 chris c = bus_space_read_4(iot, ioh, UART_DATA);
801 1.1 chris stat = bus_space_read_4(iot, ioh, UART_RX_STAT);
802 1.1 chris (void)splx(s);
803 1.11 itohy #if defined(DDB) && DDB_KEYCODE > 0
804 1.1 chris /*
805 1.1 chris * Temporary hack so that I can force the kernel into
806 1.1 chris * the debugger via the serial port
807 1.1 chris */
808 1.1 chris if (c == DDB_KEYCODE) Debugger();
809 1.1 chris #endif
810 1.1 chris
811 1.1 chris return (c);
812 1.1 chris }
813 1.1 chris
814 1.1 chris /*
815 1.1 chris * Console kernel output character routine.
816 1.1 chris */
817 1.1 chris void
818 1.1 chris fcomcnputc(dev, c)
819 1.1 chris dev_t dev;
820 1.1 chris int c;
821 1.1 chris {
822 1.1 chris int s = splserial();
823 1.1 chris bus_space_tag_t iot = fcomconstag;
824 1.1 chris bus_space_handle_t ioh = fcomconsioh;
825 1.1 chris int timo;
826 1.1 chris
827 1.1 chris /* wait for any pending transmission to finish */
828 1.1 chris timo = 50000;
829 1.1 chris while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo)
830 1.1 chris ;
831 1.1 chris bus_space_write_4(iot, ioh, UART_DATA, c);
832 1.1 chris
833 1.1 chris /* wait for this transmission to complete */
834 1.1 chris timo = 1500000;
835 1.1 chris while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo)
836 1.1 chris ;
837 1.1 chris /* Clear interrupt status here */
838 1.1 chris (void)splx(s);
839 1.1 chris }
840 1.1 chris
841 1.1 chris void
842 1.1 chris fcomcnpollc(dev, on)
843 1.1 chris dev_t dev;
844 1.1 chris int on;
845 1.1 chris {
846 1.1 chris }
847