footbridge_com.c revision 1.27 1 1.27 ad /* $NetBSD: footbridge_com.c,v 1.27 2007/11/19 18:51:38 ad Exp $ */
2 1.1 chris
3 1.1 chris /*-
4 1.1 chris * Copyright (c) 1997 Mark Brinicombe
5 1.1 chris * Copyright (c) 1997 Causality Limited
6 1.1 chris *
7 1.1 chris * Redistribution and use in source and binary forms, with or without
8 1.1 chris * modification, are permitted provided that the following conditions
9 1.1 chris * are met:
10 1.1 chris * 1. Redistributions of source code must retain the above copyright
11 1.1 chris * notice, this list of conditions and the following disclaimer.
12 1.1 chris * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 chris * notice, this list of conditions and the following disclaimer in the
14 1.1 chris * documentation and/or other materials provided with the distribution.
15 1.1 chris * 3. All advertising materials mentioning features or use of this software
16 1.1 chris * must display the following acknowledgement:
17 1.1 chris * This product includes software developed by Mark Brinicombe
18 1.1 chris * for the NetBSD Project.
19 1.1 chris * 4. The name of the author may not be used to endorse or promote products
20 1.1 chris * derived from this software without specific prior written permission.
21 1.1 chris *
22 1.1 chris * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 1.1 chris * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 1.1 chris * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 1.1 chris * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 1.1 chris * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 1.1 chris * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 1.1 chris * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 1.1 chris * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 1.1 chris * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 1.1 chris * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 1.1 chris */
33 1.1 chris
34 1.1 chris /*
35 1.1 chris * COM driver, using the footbridge UART
36 1.1 chris */
37 1.13 chris
38 1.13 chris #include <sys/cdefs.h>
39 1.27 ad __KERNEL_RCSID(0, "$NetBSD: footbridge_com.c,v 1.27 2007/11/19 18:51:38 ad Exp $");
40 1.1 chris
41 1.1 chris #include "opt_ddb.h"
42 1.11 itohy #include "opt_ddbparam.h"
43 1.1 chris
44 1.1 chris #include <sys/param.h>
45 1.1 chris #include <sys/systm.h>
46 1.1 chris #include <sys/ioctl.h>
47 1.1 chris #include <sys/select.h>
48 1.1 chris #include <sys/tty.h>
49 1.1 chris #include <sys/proc.h>
50 1.1 chris #include <sys/conf.h>
51 1.1 chris #include <sys/syslog.h>
52 1.1 chris #include <sys/device.h>
53 1.1 chris #include <sys/malloc.h>
54 1.1 chris #include <sys/termios.h>
55 1.19 elad #include <sys/kauth.h>
56 1.1 chris #include <machine/bus.h>
57 1.2 matt #include <machine/intr.h>
58 1.1 chris #include <arm/footbridge/dc21285mem.h>
59 1.1 chris #include <arm/footbridge/dc21285reg.h>
60 1.1 chris #include <arm/footbridge/footbridgevar.h>
61 1.3 chris #include <arm/footbridge/footbridge.h>
62 1.1 chris
63 1.1 chris #include <dev/cons.h>
64 1.1 chris
65 1.1 chris #include "fcom.h"
66 1.1 chris
67 1.1 chris extern u_int dc21285_fclk;
68 1.1 chris
69 1.3 chris
70 1.1 chris #ifdef DDB
71 1.1 chris /*
72 1.1 chris * Define the keycode recognised as a request to call the debugger
73 1.1 chris * A value of 0 disables the feature when DDB is built in
74 1.1 chris */
75 1.1 chris #ifndef DDB_KEYCODE
76 1.1 chris #define DDB_KEYCODE 0
77 1.1 chris #endif /* DDB_KEYCODE */
78 1.1 chris #endif /* DDB */
79 1.1 chris
80 1.1 chris struct fcom_softc {
81 1.1 chris struct device sc_dev;
82 1.1 chris bus_space_tag_t sc_iot;
83 1.1 chris bus_space_handle_t sc_ioh;
84 1.1 chris void *sc_ih;
85 1.1 chris struct callout sc_softintr_ch;
86 1.1 chris int sc_rx_irq;
87 1.1 chris int sc_tx_irq;
88 1.1 chris int sc_hwflags;
89 1.1 chris #define HW_FLAG_CONSOLE 0x01
90 1.1 chris int sc_swflags;
91 1.1 chris int sc_l_ubrlcr;
92 1.1 chris int sc_m_ubrlcr;
93 1.1 chris int sc_h_ubrlcr;
94 1.1 chris char *sc_rxbuffer[2];
95 1.1 chris char *sc_rxbuf;
96 1.1 chris int sc_rxpos;
97 1.1 chris int sc_rxcur;
98 1.1 chris struct tty *sc_tty;
99 1.1 chris };
100 1.1 chris
101 1.1 chris #define RX_BUFFER_SIZE 0x100
102 1.1 chris
103 1.1 chris static int fcom_probe __P((struct device *, struct cfdata *, void *));
104 1.1 chris static void fcom_attach __P((struct device *, struct device *, void *));
105 1.3 chris static void fcom_softintr __P((void *));
106 1.1 chris
107 1.1 chris static int fcom_rxintr __P((void *));
108 1.1 chris /*static int fcom_txintr __P((void *));*/
109 1.1 chris
110 1.1 chris /*struct consdev;*/
111 1.1 chris /*void fcomcnprobe __P((struct consdev *));
112 1.1 chris void fcomcninit __P((struct consdev *));*/
113 1.1 chris int fcomcngetc __P((dev_t));
114 1.1 chris void fcomcnputc __P((dev_t, int));
115 1.1 chris void fcomcnpollc __P((dev_t, int));
116 1.1 chris
117 1.8 thorpej CFATTACH_DECL(fcom, sizeof(struct fcom_softc),
118 1.8 thorpej fcom_probe, fcom_attach, NULL, NULL);
119 1.1 chris
120 1.1 chris extern struct cfdriver fcom_cd;
121 1.1 chris
122 1.5 gehenna dev_type_open(fcomopen);
123 1.5 gehenna dev_type_close(fcomclose);
124 1.5 gehenna dev_type_read(fcomread);
125 1.5 gehenna dev_type_write(fcomwrite);
126 1.5 gehenna dev_type_ioctl(fcomioctl);
127 1.5 gehenna dev_type_tty(fcomtty);
128 1.5 gehenna dev_type_poll(fcompoll);
129 1.5 gehenna
130 1.5 gehenna const struct cdevsw fcom_cdevsw = {
131 1.5 gehenna fcomopen, fcomclose, fcomread, fcomwrite, fcomioctl,
132 1.9 jdolecek nostop, fcomtty, fcompoll, nommap, ttykqfilter, D_TTY
133 1.5 gehenna };
134 1.5 gehenna
135 1.1 chris void fcominit __P((bus_space_tag_t, bus_space_handle_t, int, int));
136 1.1 chris void fcominitcons __P((bus_space_tag_t, bus_space_handle_t));
137 1.1 chris
138 1.1 chris bus_space_tag_t fcomconstag;
139 1.1 chris bus_space_handle_t fcomconsioh;
140 1.1 chris extern int comcnmode;
141 1.1 chris extern int comcnspeed;
142 1.1 chris
143 1.1 chris #define COMUNIT(x) (minor(x))
144 1.1 chris #ifndef CONUNIT
145 1.1 chris #define CONUNIT 0
146 1.1 chris #endif
147 1.1 chris
148 1.1 chris /*
149 1.1 chris * The console is set up at init time, well in advance of the reset of the
150 1.1 chris * system and thus we have a private bus space tag for the console.
151 1.1 chris *
152 1.1 chris * The tag is provided by fcom_io.c and fcom_io_asm.S
153 1.1 chris */
154 1.1 chris extern struct bus_space fcomcons_bs_tag;
155 1.1 chris
156 1.1 chris /*
157 1.1 chris * int fcom_probe(struct device *parent, struct cfdata *cf, void *aux)
158 1.1 chris *
159 1.1 chris * Make sure we are trying to attach a com device and then
160 1.1 chris * probe for one.
161 1.1 chris */
162 1.1 chris
163 1.1 chris static int
164 1.1 chris fcom_probe(parent, cf, aux)
165 1.1 chris struct device *parent;
166 1.1 chris struct cfdata *cf;
167 1.1 chris void *aux;
168 1.1 chris {
169 1.1 chris union footbridge_attach_args *fba = aux;
170 1.1 chris
171 1.1 chris if (strcmp(fba->fba_name, "fcom") == 0)
172 1.1 chris return(1);
173 1.1 chris return(0);
174 1.1 chris }
175 1.1 chris
176 1.1 chris /*
177 1.1 chris * void fcom_attach(struct device *parent, struct device *self, void *aux)
178 1.1 chris *
179 1.1 chris * attach the com device
180 1.1 chris */
181 1.1 chris
182 1.1 chris static void
183 1.1 chris fcom_attach(parent, self, aux)
184 1.1 chris struct device *parent, *self;
185 1.1 chris void *aux;
186 1.1 chris {
187 1.1 chris union footbridge_attach_args *fba = aux;
188 1.1 chris struct fcom_softc *sc = (struct fcom_softc *)self;
189 1.1 chris
190 1.1 chris /* Set up the softc */
191 1.1 chris sc->sc_iot = fba->fba_fca.fca_iot;
192 1.1 chris sc->sc_ioh = fba->fba_fca.fca_ioh;
193 1.24 ad callout_init(&sc->sc_softintr_ch, 0);
194 1.1 chris sc->sc_rx_irq = fba->fba_fca.fca_rx_irq;
195 1.1 chris sc->sc_tx_irq = fba->fba_fca.fca_tx_irq;
196 1.1 chris sc->sc_hwflags = 0;
197 1.1 chris sc->sc_swflags = 0;
198 1.1 chris
199 1.1 chris /* If we have a console tag then make a note of it */
200 1.1 chris if (fcomconstag)
201 1.1 chris sc->sc_hwflags |= HW_FLAG_CONSOLE;
202 1.1 chris
203 1.1 chris if (sc->sc_hwflags & HW_FLAG_CONSOLE) {
204 1.1 chris int major;
205 1.1 chris
206 1.1 chris /* locate the major number */
207 1.5 gehenna major = cdevsw_lookup_major(&fcom_cdevsw);
208 1.1 chris
209 1.18 thorpej cn_tab->cn_dev = makedev(major, device_unit(&sc->sc_dev));
210 1.1 chris printf(": console");
211 1.1 chris }
212 1.1 chris printf("\n");
213 1.1 chris
214 1.10 chris sc->sc_ih = footbridge_intr_claim(sc->sc_rx_irq, IPL_SERIAL,
215 1.10 chris "serial rx", fcom_rxintr, sc);
216 1.1 chris if (sc->sc_ih == NULL)
217 1.6 provos panic("%s: Cannot install rx interrupt handler",
218 1.1 chris sc->sc_dev.dv_xname);
219 1.1 chris }
220 1.1 chris
221 1.1 chris static void fcomstart __P((struct tty *));
222 1.1 chris static int fcomparam __P((struct tty *, struct termios *));
223 1.1 chris
224 1.1 chris int
225 1.16 christos fcomopen(dev, flag, mode, l)
226 1.1 chris dev_t dev;
227 1.1 chris int flag, mode;
228 1.16 christos struct lwp *l;
229 1.1 chris {
230 1.1 chris struct fcom_softc *sc;
231 1.1 chris int unit = minor(dev);
232 1.1 chris struct tty *tp;
233 1.1 chris
234 1.1 chris if (unit >= fcom_cd.cd_ndevs)
235 1.1 chris return ENXIO;
236 1.1 chris sc = fcom_cd.cd_devs[unit];
237 1.1 chris if (!sc)
238 1.1 chris return ENXIO;
239 1.1 chris if (!(tp = sc->sc_tty))
240 1.1 chris sc->sc_tty = tp = ttymalloc();
241 1.1 chris if (!sc->sc_rxbuffer[0]) {
242 1.1 chris sc->sc_rxbuffer[0] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK);
243 1.1 chris sc->sc_rxbuffer[1] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK);
244 1.1 chris sc->sc_rxpos = 0;
245 1.1 chris sc->sc_rxcur = 0;
246 1.1 chris sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur];
247 1.1 chris if (!sc->sc_rxbuf)
248 1.1 chris panic("%s: Cannot allocate rx buffer memory",
249 1.1 chris sc->sc_dev.dv_xname);
250 1.1 chris }
251 1.1 chris tp->t_oproc = fcomstart;
252 1.1 chris tp->t_param = fcomparam;
253 1.1 chris tp->t_dev = dev;
254 1.21 elad
255 1.21 elad if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp))
256 1.21 elad return (EBUSY);
257 1.21 elad
258 1.1 chris if (!(tp->t_state & TS_ISOPEN && tp->t_wopen == 0)) {
259 1.1 chris ttychars(tp);
260 1.1 chris tp->t_cflag = TTYDEF_CFLAG;
261 1.1 chris tp->t_iflag = TTYDEF_IFLAG;
262 1.1 chris tp->t_oflag = TTYDEF_OFLAG;
263 1.1 chris tp->t_lflag = TTYDEF_LFLAG;
264 1.1 chris
265 1.1 chris /*
266 1.1 chris * Initialize the termios status to the defaults. Add in the
267 1.1 chris * sticky bits from TIOCSFLAGS.
268 1.1 chris */
269 1.1 chris tp->t_ispeed = 0;
270 1.1 chris if (ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE))
271 1.1 chris tp->t_ospeed = comcnspeed;
272 1.1 chris else
273 1.1 chris tp->t_ospeed = TTYDEF_SPEED;
274 1.1 chris
275 1.1 chris fcomparam(tp, &tp->t_termios);
276 1.1 chris ttsetwater(tp);
277 1.21 elad }
278 1.1 chris tp->t_state |= TS_CARR_ON;
279 1.1 chris
280 1.1 chris return (*tp->t_linesw->l_open)(dev, tp);
281 1.1 chris }
282 1.1 chris
283 1.1 chris int
284 1.16 christos fcomclose(dev, flag, mode, l)
285 1.1 chris dev_t dev;
286 1.1 chris int flag, mode;
287 1.16 christos struct lwp *l;
288 1.1 chris {
289 1.1 chris struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)];
290 1.1 chris struct tty *tp = sc->sc_tty;
291 1.1 chris /* XXX This is for cons.c. */
292 1.1 chris if (!ISSET(tp->t_state, TS_ISOPEN))
293 1.1 chris return (0);
294 1.1 chris
295 1.1 chris (*tp->t_linesw->l_close)(tp, flag);
296 1.1 chris ttyclose(tp);
297 1.1 chris #ifdef DIAGNOSTIC
298 1.1 chris if (sc->sc_rxbuffer[0] == NULL)
299 1.6 provos panic("fcomclose: rx buffers not allocated");
300 1.1 chris #endif /* DIAGNOSTIC */
301 1.1 chris free(sc->sc_rxbuffer[0], M_DEVBUF);
302 1.1 chris free(sc->sc_rxbuffer[1], M_DEVBUF);
303 1.1 chris sc->sc_rxbuffer[0] = NULL;
304 1.1 chris sc->sc_rxbuffer[1] = NULL;
305 1.1 chris
306 1.1 chris return 0;
307 1.1 chris }
308 1.1 chris
309 1.1 chris int
310 1.1 chris fcomread(dev, uio, flag)
311 1.1 chris dev_t dev;
312 1.1 chris struct uio *uio;
313 1.1 chris int flag;
314 1.1 chris {
315 1.1 chris struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)];
316 1.1 chris struct tty *tp = sc->sc_tty;
317 1.1 chris
318 1.1 chris return (*tp->t_linesw->l_read)(tp, uio, flag);
319 1.1 chris }
320 1.1 chris
321 1.1 chris int
322 1.1 chris fcomwrite(dev, uio, flag)
323 1.1 chris dev_t dev;
324 1.1 chris struct uio *uio;
325 1.1 chris int flag;
326 1.1 chris {
327 1.1 chris struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)];
328 1.1 chris struct tty *tp = sc->sc_tty;
329 1.1 chris
330 1.1 chris return (*tp->t_linesw->l_write)(tp, uio, flag);
331 1.1 chris }
332 1.1 chris
333 1.1 chris int
334 1.16 christos fcompoll(dev, events, l)
335 1.1 chris dev_t dev;
336 1.1 chris int events;
337 1.16 christos struct lwp *l;
338 1.1 chris {
339 1.1 chris struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)];
340 1.1 chris struct tty *tp = sc->sc_tty;
341 1.1 chris
342 1.16 christos return ((*tp->t_linesw->l_poll)(tp, events, l));
343 1.1 chris }
344 1.1 chris
345 1.1 chris int
346 1.16 christos fcomioctl(dev, cmd, data, flag, l)
347 1.1 chris dev_t dev;
348 1.1 chris u_long cmd;
349 1.23 christos void *data;
350 1.1 chris int flag;
351 1.16 christos struct lwp *l;
352 1.1 chris {
353 1.1 chris struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)];
354 1.1 chris struct tty *tp = sc->sc_tty;
355 1.1 chris int error;
356 1.1 chris
357 1.16 christos if ((error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l)) !=
358 1.4 atatat EPASSTHROUGH)
359 1.1 chris return error;
360 1.16 christos if ((error = ttioctl(tp, cmd, data, flag, l)) != EPASSTHROUGH)
361 1.1 chris return error;
362 1.1 chris
363 1.1 chris switch (cmd) {
364 1.1 chris case TIOCGFLAGS:
365 1.1 chris *(int *)data = sc->sc_swflags;
366 1.1 chris break;
367 1.1 chris
368 1.1 chris case TIOCSFLAGS:
369 1.22 elad error = kauth_authorize_device_tty(l->l_cred,
370 1.22 elad KAUTH_DEVICE_TTY_PRIVSET, tp);
371 1.1 chris if (error)
372 1.1 chris return (error);
373 1.1 chris sc->sc_swflags = *(int *)data;
374 1.1 chris break;
375 1.1 chris }
376 1.1 chris
377 1.4 atatat return EPASSTHROUGH;
378 1.1 chris }
379 1.1 chris
380 1.1 chris struct tty *
381 1.1 chris fcomtty(dev)
382 1.1 chris dev_t dev;
383 1.1 chris {
384 1.1 chris struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)];
385 1.1 chris
386 1.1 chris return sc->sc_tty;
387 1.1 chris }
388 1.1 chris
389 1.1 chris static void
390 1.1 chris fcomstart(tp)
391 1.1 chris struct tty *tp;
392 1.1 chris {
393 1.1 chris struct clist *cl;
394 1.1 chris int s, len;
395 1.1 chris u_char buf[64];
396 1.1 chris int loop;
397 1.1 chris struct fcom_softc *sc = fcom_cd.cd_devs[minor(tp->t_dev)];
398 1.1 chris bus_space_tag_t iot = sc->sc_iot;
399 1.1 chris bus_space_handle_t ioh = sc->sc_ioh;
400 1.1 chris int timo;
401 1.1 chris
402 1.1 chris s = spltty();
403 1.1 chris if (tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) {
404 1.1 chris (void)splx(s);
405 1.1 chris return;
406 1.1 chris }
407 1.1 chris tp->t_state |= TS_BUSY;
408 1.1 chris (void)splx(s);
409 1.1 chris
410 1.1 chris /* s = splserial();*/
411 1.1 chris /* wait for any pending transmission to finish */
412 1.1 chris timo = 100000;
413 1.1 chris while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo)
414 1.1 chris ;
415 1.1 chris
416 1.1 chris s = splserial();
417 1.1 chris if (bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) {
418 1.1 chris tp->t_state |= TS_TIMEOUT;
419 1.26 joerg callout_schedule(&tp->t_rstrt_ch, 1);
420 1.1 chris (void)splx(s);
421 1.1 chris return;
422 1.1 chris }
423 1.1 chris
424 1.1 chris (void)splx(s);
425 1.1 chris
426 1.1 chris cl = &tp->t_outq;
427 1.1 chris len = q_to_b(cl, buf, 64);
428 1.1 chris for (loop = 0; loop < len; ++loop) {
429 1.1 chris /* s = splserial();*/
430 1.1 chris
431 1.1 chris bus_space_write_4(iot, ioh, UART_DATA, buf[loop]);
432 1.1 chris
433 1.1 chris /* wait for this transmission to complete */
434 1.1 chris timo = 100000;
435 1.1 chris while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo)
436 1.1 chris ;
437 1.1 chris /* (void)splx(s);*/
438 1.1 chris }
439 1.1 chris s = spltty();
440 1.1 chris tp->t_state &= ~TS_BUSY;
441 1.27 ad if (ttypull(tp)) {
442 1.1 chris tp->t_state |= TS_TIMEOUT;
443 1.26 joerg callout_schedule(&tp->t_rstrt_ch, 1);
444 1.1 chris }
445 1.1 chris (void)splx(s);
446 1.1 chris }
447 1.1 chris
448 1.1 chris static int
449 1.1 chris fcomparam(tp, t)
450 1.1 chris struct tty *tp;
451 1.1 chris struct termios *t;
452 1.1 chris {
453 1.1 chris struct fcom_softc *sc = fcom_cd.cd_devs[minor(tp->t_dev)];
454 1.1 chris bus_space_tag_t iot = sc->sc_iot;
455 1.1 chris bus_space_handle_t ioh = sc->sc_ioh;
456 1.1 chris int baudrate;
457 1.1 chris int h_ubrlcr;
458 1.1 chris int m_ubrlcr;
459 1.1 chris int l_ubrlcr;
460 1.1 chris int s;
461 1.1 chris
462 1.1 chris /* check requested parameters */
463 1.1 chris if (t->c_ospeed < 0)
464 1.1 chris return (EINVAL);
465 1.1 chris if (t->c_ispeed && t->c_ispeed != t->c_ospeed)
466 1.1 chris return (EINVAL);
467 1.1 chris
468 1.1 chris switch (t->c_ospeed) {
469 1.1 chris case B1200:
470 1.1 chris case B2400:
471 1.1 chris case B4800:
472 1.1 chris case B9600:
473 1.1 chris case B19200:
474 1.1 chris case B38400:
475 1.1 chris baudrate = UART_BRD(dc21285_fclk, t->c_ospeed);
476 1.1 chris break;
477 1.1 chris default:
478 1.1 chris baudrate = UART_BRD(dc21285_fclk, 9600);
479 1.1 chris break;
480 1.1 chris }
481 1.1 chris
482 1.1 chris l_ubrlcr = baudrate & 0xff;
483 1.1 chris m_ubrlcr = (baudrate >> 8) & 0xf;
484 1.1 chris h_ubrlcr = 0;
485 1.1 chris
486 1.1 chris switch (ISSET(t->c_cflag, CSIZE)) {
487 1.1 chris case CS5:
488 1.1 chris h_ubrlcr |= UART_DATA_BITS_5;
489 1.1 chris break;
490 1.1 chris case CS6:
491 1.1 chris h_ubrlcr |= UART_DATA_BITS_6;
492 1.1 chris break;
493 1.1 chris case CS7:
494 1.1 chris h_ubrlcr |= UART_DATA_BITS_7;
495 1.1 chris break;
496 1.1 chris case CS8:
497 1.1 chris h_ubrlcr |= UART_DATA_BITS_8;
498 1.1 chris break;
499 1.1 chris }
500 1.1 chris
501 1.1 chris if (ISSET(t->c_cflag, PARENB)) {
502 1.1 chris h_ubrlcr |= UART_PARITY_ENABLE;
503 1.1 chris if (ISSET(t->c_cflag, PARODD))
504 1.1 chris h_ubrlcr |= UART_ODD_PARITY;
505 1.1 chris else
506 1.1 chris h_ubrlcr |= UART_EVEN_PARITY;
507 1.1 chris }
508 1.1 chris
509 1.1 chris if (ISSET(t->c_cflag, CSTOPB))
510 1.1 chris h_ubrlcr |= UART_STOP_BITS_2;
511 1.1 chris
512 1.1 chris bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr);
513 1.1 chris bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr);
514 1.1 chris bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr);
515 1.1 chris
516 1.1 chris s = splserial();
517 1.1 chris
518 1.1 chris sc->sc_l_ubrlcr = l_ubrlcr;
519 1.1 chris sc->sc_m_ubrlcr = m_ubrlcr;
520 1.1 chris sc->sc_h_ubrlcr = h_ubrlcr;
521 1.1 chris
522 1.1 chris /*
523 1.1 chris * For the console, always force CLOCAL and !HUPCL, so that the port
524 1.1 chris * is always active.
525 1.1 chris */
526 1.1 chris if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) ||
527 1.1 chris ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE)) {
528 1.1 chris SET(t->c_cflag, CLOCAL);
529 1.1 chris CLR(t->c_cflag, HUPCL);
530 1.1 chris }
531 1.1 chris
532 1.1 chris /* and copy to tty */
533 1.1 chris tp->t_ispeed = 0;
534 1.1 chris tp->t_ospeed = t->c_ospeed;
535 1.1 chris tp->t_cflag = t->c_cflag;
536 1.1 chris
537 1.1 chris bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr);
538 1.1 chris bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr);
539 1.1 chris bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr);
540 1.1 chris
541 1.1 chris (void)splx(s);
542 1.1 chris
543 1.1 chris return (0);
544 1.1 chris }
545 1.1 chris
546 1.1 chris static int softint_scheduled = 0;
547 1.1 chris
548 1.1 chris static void
549 1.3 chris fcom_softintr(arg)
550 1.3 chris void *arg;
551 1.1 chris {
552 1.3 chris struct fcom_softc *sc = arg;
553 1.1 chris struct tty *tp = sc->sc_tty;
554 1.1 chris int s;
555 1.1 chris int loop;
556 1.1 chris int len;
557 1.1 chris char *ptr;
558 1.1 chris
559 1.1 chris s = spltty();
560 1.1 chris ptr = sc->sc_rxbuf;
561 1.1 chris len = sc->sc_rxpos;
562 1.1 chris sc->sc_rxcur ^= 1;
563 1.1 chris sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur];
564 1.1 chris sc->sc_rxpos = 0;
565 1.1 chris (void)splx(s);
566 1.1 chris
567 1.1 chris for (loop = 0; loop < len; ++loop)
568 1.1 chris (*tp->t_linesw->l_rint)(ptr[loop], tp);
569 1.1 chris softint_scheduled = 0;
570 1.1 chris }
571 1.1 chris
572 1.1 chris #if 0
573 1.1 chris static int
574 1.1 chris fcom_txintr(arg)
575 1.1 chris void *arg;
576 1.1 chris {
577 1.1 chris /* struct fcom_softc *sc = arg;*/
578 1.1 chris
579 1.1 chris printf("fcom_txintr()\n");
580 1.1 chris return(0);
581 1.1 chris }
582 1.1 chris #endif
583 1.1 chris
584 1.1 chris static int
585 1.1 chris fcom_rxintr(arg)
586 1.1 chris void *arg;
587 1.1 chris {
588 1.1 chris struct fcom_softc *sc = arg;
589 1.1 chris bus_space_tag_t iot = sc->sc_iot;
590 1.1 chris bus_space_handle_t ioh = sc->sc_ioh;
591 1.1 chris struct tty *tp = sc->sc_tty;
592 1.1 chris int status;
593 1.1 chris int byte;
594 1.1 chris
595 1.1 chris do {
596 1.1 chris status = bus_space_read_4(iot, ioh, UART_FLAGS);
597 1.1 chris if ((status & UART_RX_FULL))
598 1.1 chris break;
599 1.1 chris byte = bus_space_read_4(iot, ioh, UART_DATA);
600 1.1 chris status = bus_space_read_4(iot, ioh, UART_RX_STAT);
601 1.11 itohy #if defined(DDB) && DDB_KEYCODE > 0
602 1.1 chris /*
603 1.1 chris * Temporary hack so that I can force the kernel into
604 1.1 chris * the debugger via the serial port
605 1.1 chris */
606 1.1 chris if (byte == DDB_KEYCODE) Debugger();
607 1.1 chris #endif
608 1.1 chris if (tp && (tp->t_state & TS_ISOPEN))
609 1.1 chris if (sc->sc_rxpos < RX_BUFFER_SIZE) {
610 1.1 chris sc->sc_rxbuf[sc->sc_rxpos++] = byte;
611 1.1 chris if (!softint_scheduled) {
612 1.1 chris softint_scheduled = 1;
613 1.1 chris callout_reset(&sc->sc_softintr_ch,
614 1.1 chris 1, fcom_softintr, sc);
615 1.1 chris }
616 1.1 chris }
617 1.1 chris } while (1);
618 1.1 chris return(0);
619 1.1 chris }
620 1.1 chris
621 1.1 chris #if 0
622 1.1 chris void
623 1.1 chris fcom_iflush(sc)
624 1.1 chris struct fcom_softc *sc;
625 1.1 chris {
626 1.1 chris bus_space_tag_t iot = sc->sc_iot;
627 1.1 chris bus_space_handle_t ioh = sc->sc_ioh;
628 1.1 chris
629 1.1 chris /* flush any pending I/O */
630 1.1 chris while (!ISSET(bus_space_read_4(iot, ioh, UART_FLAGS), UART_RX_FULL))
631 1.1 chris (void) bus_space_read_4(iot, ioh, UART_DATA);
632 1.1 chris }
633 1.1 chris #endif
634 1.1 chris
635 1.1 chris /*
636 1.1 chris * Following are all routines needed for COM to act as console
637 1.1 chris */
638 1.1 chris
639 1.1 chris #if 0
640 1.1 chris void
641 1.1 chris fcomcnprobe(cp)
642 1.1 chris struct consdev *cp;
643 1.1 chris {
644 1.1 chris int major;
645 1.1 chris
646 1.1 chris /* Serial console is always present so no probe */
647 1.1 chris
648 1.1 chris /* locate the major number */
649 1.5 gehenna major = cdevsw_lookup_major(&fcom_cdevsw);
650 1.1 chris
651 1.1 chris /* initialize required fields */
652 1.1 chris cp->cn_dev = makedev(major, CONUNIT);
653 1.1 chris cp->cn_pri = CN_REMOTE; /* Force a serial port console */
654 1.1 chris }
655 1.1 chris
656 1.1 chris void
657 1.1 chris fcomcninit(cp)
658 1.1 chris struct consdev *cp;
659 1.1 chris {
660 1.1 chris fcomconstag = &fcomcons_bs_tag;
661 1.1 chris
662 1.1 chris if (bus_space_map(fcomconstag, DC21285_ARMCSR_BASE, DC21285_ARMCSR_SIZE, 0, &fcomconsioh))
663 1.1 chris panic("fcomcninit: mapping failed");
664 1.1 chris
665 1.1 chris fcominitcons(fcomconstag, fcomconsioh);
666 1.1 chris }
667 1.1 chris #endif
668 1.1 chris
669 1.1 chris int
670 1.1 chris fcomcnattach(iobase, rate, cflag)
671 1.1 chris u_int iobase;
672 1.1 chris int rate;
673 1.1 chris tcflag_t cflag;
674 1.1 chris {
675 1.1 chris static struct consdev fcomcons = {
676 1.1 chris NULL, NULL, fcomcngetc, fcomcnputc, fcomcnpollc, NULL,
677 1.12 skrll NULL, NULL, NODEV, CN_NORMAL
678 1.1 chris };
679 1.1 chris
680 1.1 chris fcomconstag = &fcomcons_bs_tag;
681 1.1 chris
682 1.1 chris if (bus_space_map(fcomconstag, iobase, DC21285_ARMCSR_SIZE,
683 1.1 chris 0, &fcomconsioh))
684 1.1 chris panic("fcomcninit: mapping failed");
685 1.1 chris
686 1.1 chris fcominit(fcomconstag, fcomconsioh, rate, cflag);
687 1.1 chris
688 1.1 chris cn_tab = &fcomcons;
689 1.1 chris
690 1.1 chris /* comcnspeed = rate;
691 1.1 chris comcnmode = cflag;*/
692 1.1 chris return (0);
693 1.1 chris }
694 1.1 chris
695 1.1 chris int
696 1.1 chris fcomcndetach(void)
697 1.1 chris {
698 1.1 chris bus_space_unmap(fcomconstag, fcomconsioh, DC21285_ARMCSR_SIZE);
699 1.1 chris
700 1.1 chris cn_tab = NULL;
701 1.1 chris return (0);
702 1.1 chris }
703 1.1 chris
704 1.1 chris /*
705 1.1 chris * Initialize UART to known state.
706 1.1 chris */
707 1.1 chris void
708 1.1 chris fcominit(iot, ioh, rate, mode)
709 1.1 chris bus_space_tag_t iot;
710 1.1 chris bus_space_handle_t ioh;
711 1.1 chris int rate;
712 1.1 chris int mode;
713 1.1 chris {
714 1.1 chris int baudrate;
715 1.1 chris int h_ubrlcr;
716 1.1 chris int m_ubrlcr;
717 1.1 chris int l_ubrlcr;
718 1.1 chris
719 1.1 chris switch (rate) {
720 1.1 chris case B1200:
721 1.1 chris case B2400:
722 1.1 chris case B4800:
723 1.1 chris case B9600:
724 1.1 chris case B19200:
725 1.1 chris case B38400:
726 1.1 chris baudrate = UART_BRD(dc21285_fclk, rate);
727 1.1 chris break;
728 1.1 chris default:
729 1.1 chris baudrate = UART_BRD(dc21285_fclk, 9600);
730 1.1 chris break;
731 1.1 chris }
732 1.1 chris
733 1.1 chris h_ubrlcr = 0;
734 1.1 chris switch (mode & CSIZE) {
735 1.1 chris case CS5:
736 1.1 chris h_ubrlcr |= UART_DATA_BITS_5;
737 1.1 chris break;
738 1.1 chris case CS6:
739 1.1 chris h_ubrlcr |= UART_DATA_BITS_6;
740 1.1 chris break;
741 1.1 chris case CS7:
742 1.1 chris h_ubrlcr |= UART_DATA_BITS_7;
743 1.1 chris break;
744 1.1 chris case CS8:
745 1.1 chris h_ubrlcr |= UART_DATA_BITS_8;
746 1.1 chris break;
747 1.1 chris }
748 1.1 chris
749 1.1 chris if (mode & PARENB)
750 1.1 chris h_ubrlcr |= UART_PARITY_ENABLE;
751 1.1 chris if (mode & PARODD)
752 1.1 chris h_ubrlcr |= UART_ODD_PARITY;
753 1.1 chris else
754 1.1 chris h_ubrlcr |= UART_EVEN_PARITY;
755 1.1 chris
756 1.1 chris if (mode & CSTOPB)
757 1.1 chris h_ubrlcr |= UART_STOP_BITS_2;
758 1.1 chris
759 1.1 chris m_ubrlcr = (baudrate >> 8) & 0xf;
760 1.1 chris l_ubrlcr = baudrate & 0xff;
761 1.1 chris
762 1.1 chris bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr);
763 1.1 chris bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr);
764 1.1 chris bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr);
765 1.1 chris }
766 1.1 chris #if 0
767 1.1 chris /*
768 1.1 chris * Set UART for console use. Do normal init, then enable interrupts.
769 1.1 chris */
770 1.1 chris void
771 1.1 chris fcominitcons(iot, ioh)
772 1.1 chris bus_space_tag_t iot;
773 1.1 chris bus_space_handle_t ioh;
774 1.1 chris {
775 1.1 chris int s = splserial();
776 1.1 chris
777 1.1 chris fcominit(iot, ioh, comcnspeed, comcnmode);
778 1.1 chris
779 1.1 chris delay(10000);
780 1.1 chris
781 1.1 chris (void)splx(s);
782 1.1 chris }
783 1.1 chris #endif
784 1.1 chris
785 1.1 chris int
786 1.1 chris fcomcngetc(dev)
787 1.1 chris dev_t dev;
788 1.1 chris {
789 1.1 chris int s = splserial();
790 1.1 chris bus_space_tag_t iot = fcomconstag;
791 1.1 chris bus_space_handle_t ioh = fcomconsioh;
792 1.1 chris u_char stat, c;
793 1.1 chris
794 1.1 chris while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_RX_FULL) != 0)
795 1.1 chris ;
796 1.1 chris c = bus_space_read_4(iot, ioh, UART_DATA);
797 1.1 chris stat = bus_space_read_4(iot, ioh, UART_RX_STAT);
798 1.1 chris (void)splx(s);
799 1.11 itohy #if defined(DDB) && DDB_KEYCODE > 0
800 1.1 chris /*
801 1.1 chris * Temporary hack so that I can force the kernel into
802 1.1 chris * the debugger via the serial port
803 1.1 chris */
804 1.1 chris if (c == DDB_KEYCODE) Debugger();
805 1.1 chris #endif
806 1.1 chris
807 1.1 chris return (c);
808 1.1 chris }
809 1.1 chris
810 1.1 chris /*
811 1.1 chris * Console kernel output character routine.
812 1.1 chris */
813 1.1 chris void
814 1.1 chris fcomcnputc(dev, c)
815 1.1 chris dev_t dev;
816 1.1 chris int c;
817 1.1 chris {
818 1.1 chris int s = splserial();
819 1.1 chris bus_space_tag_t iot = fcomconstag;
820 1.1 chris bus_space_handle_t ioh = fcomconsioh;
821 1.1 chris int timo;
822 1.1 chris
823 1.1 chris /* wait for any pending transmission to finish */
824 1.1 chris timo = 50000;
825 1.1 chris while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo)
826 1.1 chris ;
827 1.1 chris bus_space_write_4(iot, ioh, UART_DATA, c);
828 1.1 chris
829 1.1 chris /* wait for this transmission to complete */
830 1.1 chris timo = 1500000;
831 1.1 chris while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo)
832 1.1 chris ;
833 1.1 chris /* Clear interrupt status here */
834 1.1 chris (void)splx(s);
835 1.1 chris }
836 1.1 chris
837 1.1 chris void
838 1.1 chris fcomcnpollc(dev, on)
839 1.1 chris dev_t dev;
840 1.1 chris int on;
841 1.1 chris {
842 1.1 chris }
843