footbridge_com.c revision 1.35 1 1.35 skrll /* $NetBSD: footbridge_com.c,v 1.35 2012/10/10 21:53:09 skrll Exp $ */
2 1.1 chris
3 1.1 chris /*-
4 1.1 chris * Copyright (c) 1997 Mark Brinicombe
5 1.1 chris * Copyright (c) 1997 Causality Limited
6 1.1 chris *
7 1.1 chris * Redistribution and use in source and binary forms, with or without
8 1.1 chris * modification, are permitted provided that the following conditions
9 1.1 chris * are met:
10 1.1 chris * 1. Redistributions of source code must retain the above copyright
11 1.1 chris * notice, this list of conditions and the following disclaimer.
12 1.1 chris * 2. Redistributions in binary form must reproduce the above copyright
13 1.1 chris * notice, this list of conditions and the following disclaimer in the
14 1.1 chris * documentation and/or other materials provided with the distribution.
15 1.1 chris * 3. All advertising materials mentioning features or use of this software
16 1.1 chris * must display the following acknowledgement:
17 1.1 chris * This product includes software developed by Mark Brinicombe
18 1.1 chris * for the NetBSD Project.
19 1.1 chris * 4. The name of the author may not be used to endorse or promote products
20 1.1 chris * derived from this software without specific prior written permission.
21 1.1 chris *
22 1.1 chris * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 1.1 chris * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 1.1 chris * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 1.1 chris * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 1.1 chris * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 1.1 chris * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 1.1 chris * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 1.1 chris * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 1.1 chris * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 1.1 chris * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 1.1 chris */
33 1.1 chris
34 1.1 chris /*
35 1.1 chris * COM driver, using the footbridge UART
36 1.1 chris */
37 1.13 chris
38 1.13 chris #include <sys/cdefs.h>
39 1.35 skrll __KERNEL_RCSID(0, "$NetBSD: footbridge_com.c,v 1.35 2012/10/10 21:53:09 skrll Exp $");
40 1.1 chris
41 1.1 chris #include "opt_ddb.h"
42 1.11 itohy #include "opt_ddbparam.h"
43 1.1 chris
44 1.1 chris #include <sys/param.h>
45 1.1 chris #include <sys/systm.h>
46 1.1 chris #include <sys/ioctl.h>
47 1.1 chris #include <sys/select.h>
48 1.1 chris #include <sys/tty.h>
49 1.1 chris #include <sys/proc.h>
50 1.1 chris #include <sys/conf.h>
51 1.1 chris #include <sys/syslog.h>
52 1.1 chris #include <sys/device.h>
53 1.1 chris #include <sys/malloc.h>
54 1.1 chris #include <sys/termios.h>
55 1.19 elad #include <sys/kauth.h>
56 1.34 dyoung #include <sys/bus.h>
57 1.2 matt #include <machine/intr.h>
58 1.1 chris #include <arm/footbridge/dc21285mem.h>
59 1.1 chris #include <arm/footbridge/dc21285reg.h>
60 1.1 chris #include <arm/footbridge/footbridgevar.h>
61 1.3 chris #include <arm/footbridge/footbridge.h>
62 1.1 chris
63 1.1 chris #include <dev/cons.h>
64 1.1 chris
65 1.1 chris #include "fcom.h"
66 1.1 chris
67 1.1 chris extern u_int dc21285_fclk;
68 1.1 chris
69 1.3 chris
70 1.1 chris #ifdef DDB
71 1.1 chris /*
72 1.1 chris * Define the keycode recognised as a request to call the debugger
73 1.1 chris * A value of 0 disables the feature when DDB is built in
74 1.1 chris */
75 1.1 chris #ifndef DDB_KEYCODE
76 1.1 chris #define DDB_KEYCODE 0
77 1.1 chris #endif /* DDB_KEYCODE */
78 1.1 chris #endif /* DDB */
79 1.1 chris
80 1.1 chris struct fcom_softc {
81 1.32 skrll device_t sc_dev;
82 1.1 chris bus_space_tag_t sc_iot;
83 1.1 chris bus_space_handle_t sc_ioh;
84 1.1 chris void *sc_ih;
85 1.1 chris struct callout sc_softintr_ch;
86 1.1 chris int sc_rx_irq;
87 1.1 chris int sc_tx_irq;
88 1.1 chris int sc_hwflags;
89 1.1 chris #define HW_FLAG_CONSOLE 0x01
90 1.1 chris int sc_swflags;
91 1.1 chris int sc_l_ubrlcr;
92 1.1 chris int sc_m_ubrlcr;
93 1.1 chris int sc_h_ubrlcr;
94 1.1 chris char *sc_rxbuffer[2];
95 1.1 chris char *sc_rxbuf;
96 1.1 chris int sc_rxpos;
97 1.1 chris int sc_rxcur;
98 1.1 chris struct tty *sc_tty;
99 1.1 chris };
100 1.1 chris
101 1.1 chris #define RX_BUFFER_SIZE 0x100
102 1.1 chris
103 1.32 skrll static int fcom_probe(device_t, cfdata_t, void *);
104 1.32 skrll static void fcom_attach(device_t, device_t, void *);
105 1.29 dsl static void fcom_softintr(void *);
106 1.1 chris
107 1.29 dsl static int fcom_rxintr(void *);
108 1.29 dsl /*static int fcom_txintr(void *);*/
109 1.1 chris
110 1.1 chris /*struct consdev;*/
111 1.29 dsl /*void fcomcnprobe(struct consdev *);
112 1.29 dsl void fcomcninit(struct consdev *);*/
113 1.29 dsl int fcomcngetc(dev_t);
114 1.29 dsl void fcomcnputc(dev_t, int);
115 1.29 dsl void fcomcnpollc(dev_t, int);
116 1.1 chris
117 1.32 skrll CFATTACH_DECL_NEW(fcom, sizeof(struct fcom_softc),
118 1.8 thorpej fcom_probe, fcom_attach, NULL, NULL);
119 1.1 chris
120 1.1 chris extern struct cfdriver fcom_cd;
121 1.1 chris
122 1.5 gehenna dev_type_open(fcomopen);
123 1.5 gehenna dev_type_close(fcomclose);
124 1.5 gehenna dev_type_read(fcomread);
125 1.5 gehenna dev_type_write(fcomwrite);
126 1.5 gehenna dev_type_ioctl(fcomioctl);
127 1.5 gehenna dev_type_tty(fcomtty);
128 1.5 gehenna dev_type_poll(fcompoll);
129 1.5 gehenna
130 1.5 gehenna const struct cdevsw fcom_cdevsw = {
131 1.5 gehenna fcomopen, fcomclose, fcomread, fcomwrite, fcomioctl,
132 1.9 jdolecek nostop, fcomtty, fcompoll, nommap, ttykqfilter, D_TTY
133 1.5 gehenna };
134 1.5 gehenna
135 1.29 dsl void fcominit(bus_space_tag_t, bus_space_handle_t, int, int);
136 1.29 dsl void fcominitcons(bus_space_tag_t, bus_space_handle_t);
137 1.1 chris
138 1.1 chris bus_space_tag_t fcomconstag;
139 1.1 chris bus_space_handle_t fcomconsioh;
140 1.1 chris extern int comcnmode;
141 1.1 chris extern int comcnspeed;
142 1.1 chris
143 1.1 chris #define COMUNIT(x) (minor(x))
144 1.1 chris #ifndef CONUNIT
145 1.1 chris #define CONUNIT 0
146 1.1 chris #endif
147 1.1 chris
148 1.1 chris /*
149 1.1 chris * The console is set up at init time, well in advance of the reset of the
150 1.1 chris * system and thus we have a private bus space tag for the console.
151 1.1 chris *
152 1.1 chris * The tag is provided by fcom_io.c and fcom_io_asm.S
153 1.1 chris */
154 1.1 chris extern struct bus_space fcomcons_bs_tag;
155 1.1 chris
156 1.1 chris /*
157 1.35 skrll * int fcom_probe(device_t parent, cfdata_t cf, void *aux)
158 1.1 chris *
159 1.1 chris * Make sure we are trying to attach a com device and then
160 1.1 chris * probe for one.
161 1.1 chris */
162 1.1 chris
163 1.1 chris static int
164 1.32 skrll fcom_probe(device_t parent, cfdata_t cf, void *aux)
165 1.1 chris {
166 1.1 chris union footbridge_attach_args *fba = aux;
167 1.1 chris
168 1.1 chris if (strcmp(fba->fba_name, "fcom") == 0)
169 1.1 chris return(1);
170 1.1 chris return(0);
171 1.1 chris }
172 1.1 chris
173 1.1 chris /*
174 1.32 skrll * void fcom_attach(device_t parent, device_t self, void *aux)
175 1.1 chris *
176 1.1 chris * attach the com device
177 1.1 chris */
178 1.1 chris
179 1.1 chris static void
180 1.32 skrll fcom_attach(device_t parent, device_t self, void *aux)
181 1.1 chris {
182 1.1 chris union footbridge_attach_args *fba = aux;
183 1.32 skrll struct fcom_softc *sc = device_private(self);
184 1.1 chris
185 1.1 chris /* Set up the softc */
186 1.32 skrll sc->sc_dev = self;
187 1.1 chris sc->sc_iot = fba->fba_fca.fca_iot;
188 1.1 chris sc->sc_ioh = fba->fba_fca.fca_ioh;
189 1.24 ad callout_init(&sc->sc_softintr_ch, 0);
190 1.1 chris sc->sc_rx_irq = fba->fba_fca.fca_rx_irq;
191 1.1 chris sc->sc_tx_irq = fba->fba_fca.fca_tx_irq;
192 1.1 chris sc->sc_hwflags = 0;
193 1.1 chris sc->sc_swflags = 0;
194 1.1 chris
195 1.1 chris /* If we have a console tag then make a note of it */
196 1.1 chris if (fcomconstag)
197 1.1 chris sc->sc_hwflags |= HW_FLAG_CONSOLE;
198 1.1 chris
199 1.1 chris if (sc->sc_hwflags & HW_FLAG_CONSOLE) {
200 1.1 chris int major;
201 1.1 chris
202 1.1 chris /* locate the major number */
203 1.5 gehenna major = cdevsw_lookup_major(&fcom_cdevsw);
204 1.1 chris
205 1.32 skrll cn_tab->cn_dev = makedev(major, device_unit(sc->sc_dev));
206 1.32 skrll aprint_normal(": console");
207 1.1 chris }
208 1.32 skrll aprint_normal("\n");
209 1.1 chris
210 1.10 chris sc->sc_ih = footbridge_intr_claim(sc->sc_rx_irq, IPL_SERIAL,
211 1.10 chris "serial rx", fcom_rxintr, sc);
212 1.1 chris if (sc->sc_ih == NULL)
213 1.6 provos panic("%s: Cannot install rx interrupt handler",
214 1.32 skrll device_xname(sc->sc_dev));
215 1.1 chris }
216 1.1 chris
217 1.29 dsl static void fcomstart(struct tty *);
218 1.29 dsl static int fcomparam(struct tty *, struct termios *);
219 1.1 chris
220 1.1 chris int
221 1.28 cegger fcomopen(dev_t dev, int flag, int mode, struct lwp *l)
222 1.1 chris {
223 1.1 chris struct fcom_softc *sc;
224 1.1 chris struct tty *tp;
225 1.1 chris
226 1.28 cegger sc = device_lookup_private(&fcom_cd, minor(dev));
227 1.1 chris if (!sc)
228 1.1 chris return ENXIO;
229 1.1 chris if (!(tp = sc->sc_tty))
230 1.33 rmind sc->sc_tty = tp = tty_alloc();
231 1.1 chris if (!sc->sc_rxbuffer[0]) {
232 1.1 chris sc->sc_rxbuffer[0] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK);
233 1.1 chris sc->sc_rxbuffer[1] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK);
234 1.1 chris sc->sc_rxpos = 0;
235 1.1 chris sc->sc_rxcur = 0;
236 1.1 chris sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur];
237 1.1 chris if (!sc->sc_rxbuf)
238 1.1 chris panic("%s: Cannot allocate rx buffer memory",
239 1.32 skrll device_xname(sc->sc_dev));
240 1.1 chris }
241 1.1 chris tp->t_oproc = fcomstart;
242 1.1 chris tp->t_param = fcomparam;
243 1.1 chris tp->t_dev = dev;
244 1.21 elad
245 1.21 elad if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp))
246 1.21 elad return (EBUSY);
247 1.21 elad
248 1.1 chris if (!(tp->t_state & TS_ISOPEN && tp->t_wopen == 0)) {
249 1.1 chris ttychars(tp);
250 1.1 chris tp->t_cflag = TTYDEF_CFLAG;
251 1.1 chris tp->t_iflag = TTYDEF_IFLAG;
252 1.1 chris tp->t_oflag = TTYDEF_OFLAG;
253 1.1 chris tp->t_lflag = TTYDEF_LFLAG;
254 1.1 chris
255 1.1 chris /*
256 1.1 chris * Initialize the termios status to the defaults. Add in the
257 1.1 chris * sticky bits from TIOCSFLAGS.
258 1.1 chris */
259 1.1 chris tp->t_ispeed = 0;
260 1.1 chris if (ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE))
261 1.1 chris tp->t_ospeed = comcnspeed;
262 1.1 chris else
263 1.1 chris tp->t_ospeed = TTYDEF_SPEED;
264 1.1 chris
265 1.1 chris fcomparam(tp, &tp->t_termios);
266 1.1 chris ttsetwater(tp);
267 1.21 elad }
268 1.1 chris tp->t_state |= TS_CARR_ON;
269 1.1 chris
270 1.1 chris return (*tp->t_linesw->l_open)(dev, tp);
271 1.1 chris }
272 1.1 chris
273 1.1 chris int
274 1.28 cegger fcomclose(dev_t dev, int flag, int mode, struct lwp *l)
275 1.1 chris {
276 1.28 cegger struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(dev));
277 1.1 chris struct tty *tp = sc->sc_tty;
278 1.1 chris /* XXX This is for cons.c. */
279 1.1 chris if (!ISSET(tp->t_state, TS_ISOPEN))
280 1.1 chris return (0);
281 1.1 chris
282 1.1 chris (*tp->t_linesw->l_close)(tp, flag);
283 1.1 chris ttyclose(tp);
284 1.1 chris #ifdef DIAGNOSTIC
285 1.1 chris if (sc->sc_rxbuffer[0] == NULL)
286 1.6 provos panic("fcomclose: rx buffers not allocated");
287 1.1 chris #endif /* DIAGNOSTIC */
288 1.1 chris free(sc->sc_rxbuffer[0], M_DEVBUF);
289 1.1 chris free(sc->sc_rxbuffer[1], M_DEVBUF);
290 1.1 chris sc->sc_rxbuffer[0] = NULL;
291 1.1 chris sc->sc_rxbuffer[1] = NULL;
292 1.1 chris
293 1.1 chris return 0;
294 1.1 chris }
295 1.1 chris
296 1.1 chris int
297 1.28 cegger fcomread(dev_t dev, struct uio *uio, int flag)
298 1.1 chris {
299 1.28 cegger struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(dev));
300 1.1 chris struct tty *tp = sc->sc_tty;
301 1.1 chris
302 1.1 chris return (*tp->t_linesw->l_read)(tp, uio, flag);
303 1.1 chris }
304 1.1 chris
305 1.1 chris int
306 1.28 cegger fcomwrite(dev_t dev, struct uio *uio, int flag)
307 1.1 chris {
308 1.28 cegger struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(dev));
309 1.1 chris struct tty *tp = sc->sc_tty;
310 1.1 chris
311 1.1 chris return (*tp->t_linesw->l_write)(tp, uio, flag);
312 1.1 chris }
313 1.1 chris
314 1.1 chris int
315 1.28 cegger fcompoll(dev_t dev, int events, struct lwp *l)
316 1.1 chris {
317 1.28 cegger struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(dev));
318 1.1 chris struct tty *tp = sc->sc_tty;
319 1.1 chris
320 1.16 christos return ((*tp->t_linesw->l_poll)(tp, events, l));
321 1.1 chris }
322 1.1 chris
323 1.1 chris int
324 1.28 cegger fcomioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
325 1.1 chris {
326 1.28 cegger struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(dev));
327 1.1 chris struct tty *tp = sc->sc_tty;
328 1.1 chris int error;
329 1.1 chris
330 1.16 christos if ((error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l)) !=
331 1.4 atatat EPASSTHROUGH)
332 1.1 chris return error;
333 1.16 christos if ((error = ttioctl(tp, cmd, data, flag, l)) != EPASSTHROUGH)
334 1.1 chris return error;
335 1.1 chris
336 1.1 chris switch (cmd) {
337 1.1 chris case TIOCGFLAGS:
338 1.1 chris *(int *)data = sc->sc_swflags;
339 1.1 chris break;
340 1.1 chris
341 1.1 chris case TIOCSFLAGS:
342 1.22 elad error = kauth_authorize_device_tty(l->l_cred,
343 1.22 elad KAUTH_DEVICE_TTY_PRIVSET, tp);
344 1.1 chris if (error)
345 1.1 chris return (error);
346 1.1 chris sc->sc_swflags = *(int *)data;
347 1.1 chris break;
348 1.1 chris }
349 1.1 chris
350 1.4 atatat return EPASSTHROUGH;
351 1.1 chris }
352 1.1 chris
353 1.1 chris struct tty *
354 1.28 cegger fcomtty(dev_t dev)
355 1.1 chris {
356 1.28 cegger struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(dev));
357 1.1 chris
358 1.1 chris return sc->sc_tty;
359 1.1 chris }
360 1.1 chris
361 1.1 chris static void
362 1.28 cegger fcomstart(struct tty *tp)
363 1.1 chris {
364 1.1 chris struct clist *cl;
365 1.1 chris int s, len;
366 1.1 chris u_char buf[64];
367 1.1 chris int loop;
368 1.28 cegger struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(tp->t_dev));
369 1.1 chris bus_space_tag_t iot = sc->sc_iot;
370 1.1 chris bus_space_handle_t ioh = sc->sc_ioh;
371 1.1 chris int timo;
372 1.1 chris
373 1.1 chris s = spltty();
374 1.1 chris if (tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) {
375 1.1 chris (void)splx(s);
376 1.1 chris return;
377 1.1 chris }
378 1.1 chris tp->t_state |= TS_BUSY;
379 1.1 chris (void)splx(s);
380 1.1 chris
381 1.1 chris /* s = splserial();*/
382 1.1 chris /* wait for any pending transmission to finish */
383 1.1 chris timo = 100000;
384 1.1 chris while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo)
385 1.1 chris ;
386 1.1 chris
387 1.1 chris s = splserial();
388 1.1 chris if (bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) {
389 1.1 chris tp->t_state |= TS_TIMEOUT;
390 1.26 joerg callout_schedule(&tp->t_rstrt_ch, 1);
391 1.1 chris (void)splx(s);
392 1.1 chris return;
393 1.1 chris }
394 1.1 chris
395 1.1 chris (void)splx(s);
396 1.1 chris
397 1.1 chris cl = &tp->t_outq;
398 1.1 chris len = q_to_b(cl, buf, 64);
399 1.1 chris for (loop = 0; loop < len; ++loop) {
400 1.1 chris /* s = splserial();*/
401 1.1 chris
402 1.1 chris bus_space_write_4(iot, ioh, UART_DATA, buf[loop]);
403 1.1 chris
404 1.1 chris /* wait for this transmission to complete */
405 1.1 chris timo = 100000;
406 1.1 chris while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo)
407 1.1 chris ;
408 1.1 chris /* (void)splx(s);*/
409 1.1 chris }
410 1.1 chris s = spltty();
411 1.1 chris tp->t_state &= ~TS_BUSY;
412 1.27 ad if (ttypull(tp)) {
413 1.1 chris tp->t_state |= TS_TIMEOUT;
414 1.26 joerg callout_schedule(&tp->t_rstrt_ch, 1);
415 1.1 chris }
416 1.1 chris (void)splx(s);
417 1.1 chris }
418 1.1 chris
419 1.1 chris static int
420 1.28 cegger fcomparam(struct tty *tp, struct termios *t)
421 1.1 chris {
422 1.28 cegger struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(tp->t_dev));
423 1.1 chris bus_space_tag_t iot = sc->sc_iot;
424 1.1 chris bus_space_handle_t ioh = sc->sc_ioh;
425 1.1 chris int baudrate;
426 1.1 chris int h_ubrlcr;
427 1.1 chris int m_ubrlcr;
428 1.1 chris int l_ubrlcr;
429 1.1 chris int s;
430 1.1 chris
431 1.1 chris /* check requested parameters */
432 1.1 chris if (t->c_ospeed < 0)
433 1.1 chris return (EINVAL);
434 1.1 chris if (t->c_ispeed && t->c_ispeed != t->c_ospeed)
435 1.1 chris return (EINVAL);
436 1.1 chris
437 1.1 chris switch (t->c_ospeed) {
438 1.1 chris case B1200:
439 1.1 chris case B2400:
440 1.1 chris case B4800:
441 1.1 chris case B9600:
442 1.1 chris case B19200:
443 1.1 chris case B38400:
444 1.1 chris baudrate = UART_BRD(dc21285_fclk, t->c_ospeed);
445 1.1 chris break;
446 1.1 chris default:
447 1.1 chris baudrate = UART_BRD(dc21285_fclk, 9600);
448 1.1 chris break;
449 1.1 chris }
450 1.1 chris
451 1.1 chris l_ubrlcr = baudrate & 0xff;
452 1.1 chris m_ubrlcr = (baudrate >> 8) & 0xf;
453 1.1 chris h_ubrlcr = 0;
454 1.1 chris
455 1.1 chris switch (ISSET(t->c_cflag, CSIZE)) {
456 1.1 chris case CS5:
457 1.1 chris h_ubrlcr |= UART_DATA_BITS_5;
458 1.1 chris break;
459 1.1 chris case CS6:
460 1.1 chris h_ubrlcr |= UART_DATA_BITS_6;
461 1.1 chris break;
462 1.1 chris case CS7:
463 1.1 chris h_ubrlcr |= UART_DATA_BITS_7;
464 1.1 chris break;
465 1.1 chris case CS8:
466 1.1 chris h_ubrlcr |= UART_DATA_BITS_8;
467 1.1 chris break;
468 1.1 chris }
469 1.1 chris
470 1.1 chris if (ISSET(t->c_cflag, PARENB)) {
471 1.1 chris h_ubrlcr |= UART_PARITY_ENABLE;
472 1.1 chris if (ISSET(t->c_cflag, PARODD))
473 1.1 chris h_ubrlcr |= UART_ODD_PARITY;
474 1.1 chris else
475 1.1 chris h_ubrlcr |= UART_EVEN_PARITY;
476 1.1 chris }
477 1.1 chris
478 1.1 chris if (ISSET(t->c_cflag, CSTOPB))
479 1.1 chris h_ubrlcr |= UART_STOP_BITS_2;
480 1.1 chris
481 1.1 chris bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr);
482 1.1 chris bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr);
483 1.1 chris bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr);
484 1.1 chris
485 1.1 chris s = splserial();
486 1.1 chris
487 1.1 chris sc->sc_l_ubrlcr = l_ubrlcr;
488 1.1 chris sc->sc_m_ubrlcr = m_ubrlcr;
489 1.1 chris sc->sc_h_ubrlcr = h_ubrlcr;
490 1.1 chris
491 1.1 chris /*
492 1.1 chris * For the console, always force CLOCAL and !HUPCL, so that the port
493 1.1 chris * is always active.
494 1.1 chris */
495 1.1 chris if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) ||
496 1.1 chris ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE)) {
497 1.1 chris SET(t->c_cflag, CLOCAL);
498 1.1 chris CLR(t->c_cflag, HUPCL);
499 1.1 chris }
500 1.1 chris
501 1.1 chris /* and copy to tty */
502 1.1 chris tp->t_ispeed = 0;
503 1.1 chris tp->t_ospeed = t->c_ospeed;
504 1.1 chris tp->t_cflag = t->c_cflag;
505 1.1 chris
506 1.1 chris bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr);
507 1.1 chris bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr);
508 1.1 chris bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr);
509 1.1 chris
510 1.1 chris (void)splx(s);
511 1.1 chris
512 1.1 chris return (0);
513 1.1 chris }
514 1.1 chris
515 1.1 chris static int softint_scheduled = 0;
516 1.1 chris
517 1.1 chris static void
518 1.30 dsl fcom_softintr(void *arg)
519 1.1 chris {
520 1.3 chris struct fcom_softc *sc = arg;
521 1.1 chris struct tty *tp = sc->sc_tty;
522 1.1 chris int s;
523 1.1 chris int loop;
524 1.1 chris int len;
525 1.1 chris char *ptr;
526 1.1 chris
527 1.1 chris s = spltty();
528 1.1 chris ptr = sc->sc_rxbuf;
529 1.1 chris len = sc->sc_rxpos;
530 1.1 chris sc->sc_rxcur ^= 1;
531 1.1 chris sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur];
532 1.1 chris sc->sc_rxpos = 0;
533 1.1 chris (void)splx(s);
534 1.1 chris
535 1.1 chris for (loop = 0; loop < len; ++loop)
536 1.1 chris (*tp->t_linesw->l_rint)(ptr[loop], tp);
537 1.1 chris softint_scheduled = 0;
538 1.1 chris }
539 1.1 chris
540 1.1 chris #if 0
541 1.1 chris static int
542 1.30 dsl fcom_txintr(void *arg)
543 1.1 chris {
544 1.1 chris /* struct fcom_softc *sc = arg;*/
545 1.1 chris
546 1.1 chris printf("fcom_txintr()\n");
547 1.1 chris return(0);
548 1.1 chris }
549 1.1 chris #endif
550 1.1 chris
551 1.1 chris static int
552 1.30 dsl fcom_rxintr(void *arg)
553 1.1 chris {
554 1.1 chris struct fcom_softc *sc = arg;
555 1.1 chris bus_space_tag_t iot = sc->sc_iot;
556 1.1 chris bus_space_handle_t ioh = sc->sc_ioh;
557 1.1 chris struct tty *tp = sc->sc_tty;
558 1.1 chris int status;
559 1.1 chris int byte;
560 1.1 chris
561 1.1 chris do {
562 1.1 chris status = bus_space_read_4(iot, ioh, UART_FLAGS);
563 1.1 chris if ((status & UART_RX_FULL))
564 1.1 chris break;
565 1.1 chris byte = bus_space_read_4(iot, ioh, UART_DATA);
566 1.1 chris status = bus_space_read_4(iot, ioh, UART_RX_STAT);
567 1.11 itohy #if defined(DDB) && DDB_KEYCODE > 0
568 1.1 chris /*
569 1.1 chris * Temporary hack so that I can force the kernel into
570 1.1 chris * the debugger via the serial port
571 1.1 chris */
572 1.1 chris if (byte == DDB_KEYCODE) Debugger();
573 1.1 chris #endif
574 1.1 chris if (tp && (tp->t_state & TS_ISOPEN))
575 1.1 chris if (sc->sc_rxpos < RX_BUFFER_SIZE) {
576 1.1 chris sc->sc_rxbuf[sc->sc_rxpos++] = byte;
577 1.1 chris if (!softint_scheduled) {
578 1.1 chris softint_scheduled = 1;
579 1.1 chris callout_reset(&sc->sc_softintr_ch,
580 1.1 chris 1, fcom_softintr, sc);
581 1.1 chris }
582 1.1 chris }
583 1.1 chris } while (1);
584 1.1 chris return(0);
585 1.1 chris }
586 1.1 chris
587 1.1 chris #if 0
588 1.1 chris void
589 1.30 dsl fcom_iflush(struct fcom_softc *sc)
590 1.1 chris {
591 1.1 chris bus_space_tag_t iot = sc->sc_iot;
592 1.1 chris bus_space_handle_t ioh = sc->sc_ioh;
593 1.1 chris
594 1.1 chris /* flush any pending I/O */
595 1.1 chris while (!ISSET(bus_space_read_4(iot, ioh, UART_FLAGS), UART_RX_FULL))
596 1.1 chris (void) bus_space_read_4(iot, ioh, UART_DATA);
597 1.1 chris }
598 1.1 chris #endif
599 1.1 chris
600 1.1 chris /*
601 1.1 chris * Following are all routines needed for COM to act as console
602 1.1 chris */
603 1.1 chris
604 1.1 chris #if 0
605 1.1 chris void
606 1.30 dsl fcomcnprobe(struct consdev *cp)
607 1.1 chris {
608 1.1 chris int major;
609 1.1 chris
610 1.1 chris /* Serial console is always present so no probe */
611 1.1 chris
612 1.1 chris /* locate the major number */
613 1.5 gehenna major = cdevsw_lookup_major(&fcom_cdevsw);
614 1.1 chris
615 1.1 chris /* initialize required fields */
616 1.1 chris cp->cn_dev = makedev(major, CONUNIT);
617 1.1 chris cp->cn_pri = CN_REMOTE; /* Force a serial port console */
618 1.1 chris }
619 1.1 chris
620 1.1 chris void
621 1.30 dsl fcomcninit(struct consdev *cp)
622 1.1 chris {
623 1.1 chris fcomconstag = &fcomcons_bs_tag;
624 1.1 chris
625 1.1 chris if (bus_space_map(fcomconstag, DC21285_ARMCSR_BASE, DC21285_ARMCSR_SIZE, 0, &fcomconsioh))
626 1.1 chris panic("fcomcninit: mapping failed");
627 1.1 chris
628 1.1 chris fcominitcons(fcomconstag, fcomconsioh);
629 1.1 chris }
630 1.1 chris #endif
631 1.1 chris
632 1.1 chris int
633 1.30 dsl fcomcnattach(u_int iobase, int rate, tcflag_t cflag)
634 1.1 chris {
635 1.1 chris static struct consdev fcomcons = {
636 1.1 chris NULL, NULL, fcomcngetc, fcomcnputc, fcomcnpollc, NULL,
637 1.12 skrll NULL, NULL, NODEV, CN_NORMAL
638 1.1 chris };
639 1.1 chris
640 1.1 chris fcomconstag = &fcomcons_bs_tag;
641 1.1 chris
642 1.1 chris if (bus_space_map(fcomconstag, iobase, DC21285_ARMCSR_SIZE,
643 1.1 chris 0, &fcomconsioh))
644 1.1 chris panic("fcomcninit: mapping failed");
645 1.1 chris
646 1.1 chris fcominit(fcomconstag, fcomconsioh, rate, cflag);
647 1.1 chris
648 1.1 chris cn_tab = &fcomcons;
649 1.1 chris
650 1.1 chris /* comcnspeed = rate;
651 1.1 chris comcnmode = cflag;*/
652 1.1 chris return (0);
653 1.1 chris }
654 1.1 chris
655 1.1 chris int
656 1.1 chris fcomcndetach(void)
657 1.1 chris {
658 1.1 chris bus_space_unmap(fcomconstag, fcomconsioh, DC21285_ARMCSR_SIZE);
659 1.1 chris
660 1.1 chris cn_tab = NULL;
661 1.1 chris return (0);
662 1.1 chris }
663 1.1 chris
664 1.1 chris /*
665 1.1 chris * Initialize UART to known state.
666 1.1 chris */
667 1.1 chris void
668 1.30 dsl fcominit(bus_space_tag_t iot, bus_space_handle_t ioh, int rate, int mode)
669 1.1 chris {
670 1.1 chris int baudrate;
671 1.1 chris int h_ubrlcr;
672 1.1 chris int m_ubrlcr;
673 1.1 chris int l_ubrlcr;
674 1.1 chris
675 1.1 chris switch (rate) {
676 1.1 chris case B1200:
677 1.1 chris case B2400:
678 1.1 chris case B4800:
679 1.1 chris case B9600:
680 1.1 chris case B19200:
681 1.1 chris case B38400:
682 1.1 chris baudrate = UART_BRD(dc21285_fclk, rate);
683 1.1 chris break;
684 1.1 chris default:
685 1.1 chris baudrate = UART_BRD(dc21285_fclk, 9600);
686 1.1 chris break;
687 1.1 chris }
688 1.1 chris
689 1.1 chris h_ubrlcr = 0;
690 1.1 chris switch (mode & CSIZE) {
691 1.1 chris case CS5:
692 1.1 chris h_ubrlcr |= UART_DATA_BITS_5;
693 1.1 chris break;
694 1.1 chris case CS6:
695 1.1 chris h_ubrlcr |= UART_DATA_BITS_6;
696 1.1 chris break;
697 1.1 chris case CS7:
698 1.1 chris h_ubrlcr |= UART_DATA_BITS_7;
699 1.1 chris break;
700 1.1 chris case CS8:
701 1.1 chris h_ubrlcr |= UART_DATA_BITS_8;
702 1.1 chris break;
703 1.1 chris }
704 1.1 chris
705 1.1 chris if (mode & PARENB)
706 1.1 chris h_ubrlcr |= UART_PARITY_ENABLE;
707 1.1 chris if (mode & PARODD)
708 1.1 chris h_ubrlcr |= UART_ODD_PARITY;
709 1.1 chris else
710 1.1 chris h_ubrlcr |= UART_EVEN_PARITY;
711 1.1 chris
712 1.1 chris if (mode & CSTOPB)
713 1.1 chris h_ubrlcr |= UART_STOP_BITS_2;
714 1.1 chris
715 1.1 chris m_ubrlcr = (baudrate >> 8) & 0xf;
716 1.1 chris l_ubrlcr = baudrate & 0xff;
717 1.1 chris
718 1.1 chris bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr);
719 1.1 chris bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr);
720 1.1 chris bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr);
721 1.1 chris }
722 1.1 chris #if 0
723 1.1 chris /*
724 1.1 chris * Set UART for console use. Do normal init, then enable interrupts.
725 1.1 chris */
726 1.1 chris void
727 1.30 dsl fcominitcons(bus_space_tag_t iot, bus_space_handle_t ioh)
728 1.1 chris {
729 1.1 chris int s = splserial();
730 1.1 chris
731 1.1 chris fcominit(iot, ioh, comcnspeed, comcnmode);
732 1.1 chris
733 1.1 chris delay(10000);
734 1.1 chris
735 1.1 chris (void)splx(s);
736 1.1 chris }
737 1.1 chris #endif
738 1.1 chris
739 1.1 chris int
740 1.30 dsl fcomcngetc(dev_t dev)
741 1.1 chris {
742 1.1 chris int s = splserial();
743 1.1 chris bus_space_tag_t iot = fcomconstag;
744 1.1 chris bus_space_handle_t ioh = fcomconsioh;
745 1.1 chris u_char stat, c;
746 1.1 chris
747 1.1 chris while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_RX_FULL) != 0)
748 1.1 chris ;
749 1.1 chris c = bus_space_read_4(iot, ioh, UART_DATA);
750 1.1 chris stat = bus_space_read_4(iot, ioh, UART_RX_STAT);
751 1.1 chris (void)splx(s);
752 1.11 itohy #if defined(DDB) && DDB_KEYCODE > 0
753 1.1 chris /*
754 1.1 chris * Temporary hack so that I can force the kernel into
755 1.1 chris * the debugger via the serial port
756 1.1 chris */
757 1.1 chris if (c == DDB_KEYCODE) Debugger();
758 1.1 chris #endif
759 1.1 chris
760 1.1 chris return (c);
761 1.1 chris }
762 1.1 chris
763 1.1 chris /*
764 1.1 chris * Console kernel output character routine.
765 1.1 chris */
766 1.1 chris void
767 1.30 dsl fcomcnputc(dev_t dev, int c)
768 1.1 chris {
769 1.1 chris int s = splserial();
770 1.1 chris bus_space_tag_t iot = fcomconstag;
771 1.1 chris bus_space_handle_t ioh = fcomconsioh;
772 1.1 chris int timo;
773 1.1 chris
774 1.1 chris /* wait for any pending transmission to finish */
775 1.1 chris timo = 50000;
776 1.1 chris while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo)
777 1.1 chris ;
778 1.1 chris bus_space_write_4(iot, ioh, UART_DATA, c);
779 1.1 chris
780 1.1 chris /* wait for this transmission to complete */
781 1.1 chris timo = 1500000;
782 1.1 chris while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo)
783 1.1 chris ;
784 1.1 chris /* Clear interrupt status here */
785 1.1 chris (void)splx(s);
786 1.1 chris }
787 1.1 chris
788 1.1 chris void
789 1.30 dsl fcomcnpollc(dev_t dev, int on)
790 1.1 chris {
791 1.1 chris }
792