footbridge_com.c revision 1.16
1 /* $NetBSD: footbridge_com.c,v 1.16 2005/12/11 12:16:45 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 Mark Brinicombe 5 * Copyright (c) 1997 Causality Limited 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Mark Brinicombe 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * COM driver, using the footbridge UART 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: footbridge_com.c,v 1.16 2005/12/11 12:16:45 christos Exp $"); 40 41 #include "opt_ddb.h" 42 #include "opt_ddbparam.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/ioctl.h> 47 #include <sys/select.h> 48 #include <sys/tty.h> 49 #include <sys/proc.h> 50 #include <sys/conf.h> 51 #include <sys/syslog.h> 52 #include <sys/device.h> 53 #include <sys/malloc.h> 54 #include <sys/termios.h> 55 #include <machine/bus.h> 56 #include <machine/intr.h> 57 #include <arm/footbridge/dc21285mem.h> 58 #include <arm/footbridge/dc21285reg.h> 59 #include <arm/footbridge/footbridgevar.h> 60 #include <arm/footbridge/footbridge.h> 61 62 #include <dev/cons.h> 63 64 #include "fcom.h" 65 66 extern u_int dc21285_fclk; 67 68 69 #ifdef DDB 70 /* 71 * Define the keycode recognised as a request to call the debugger 72 * A value of 0 disables the feature when DDB is built in 73 */ 74 #ifndef DDB_KEYCODE 75 #define DDB_KEYCODE 0 76 #endif /* DDB_KEYCODE */ 77 #endif /* DDB */ 78 79 struct fcom_softc { 80 struct device sc_dev; 81 bus_space_tag_t sc_iot; 82 bus_space_handle_t sc_ioh; 83 void *sc_ih; 84 struct callout sc_softintr_ch; 85 int sc_rx_irq; 86 int sc_tx_irq; 87 int sc_hwflags; 88 #define HW_FLAG_CONSOLE 0x01 89 int sc_swflags; 90 int sc_l_ubrlcr; 91 int sc_m_ubrlcr; 92 int sc_h_ubrlcr; 93 char *sc_rxbuffer[2]; 94 char *sc_rxbuf; 95 int sc_rxpos; 96 int sc_rxcur; 97 struct tty *sc_tty; 98 }; 99 100 #define RX_BUFFER_SIZE 0x100 101 102 /* Macros to clear/set/test flags. */ 103 #define SET(t, f) (t) |= (f) 104 #define CLR(t, f) (t) &= ~(f) 105 #define ISSET(t, f) ((t) & (f)) 106 107 static int fcom_probe __P((struct device *, struct cfdata *, void *)); 108 static void fcom_attach __P((struct device *, struct device *, void *)); 109 static void fcom_softintr __P((void *)); 110 111 static int fcom_rxintr __P((void *)); 112 /*static int fcom_txintr __P((void *));*/ 113 114 /*struct consdev;*/ 115 /*void fcomcnprobe __P((struct consdev *)); 116 void fcomcninit __P((struct consdev *));*/ 117 int fcomcngetc __P((dev_t)); 118 void fcomcnputc __P((dev_t, int)); 119 void fcomcnpollc __P((dev_t, int)); 120 121 CFATTACH_DECL(fcom, sizeof(struct fcom_softc), 122 fcom_probe, fcom_attach, NULL, NULL); 123 124 extern struct cfdriver fcom_cd; 125 126 dev_type_open(fcomopen); 127 dev_type_close(fcomclose); 128 dev_type_read(fcomread); 129 dev_type_write(fcomwrite); 130 dev_type_ioctl(fcomioctl); 131 dev_type_tty(fcomtty); 132 dev_type_poll(fcompoll); 133 134 const struct cdevsw fcom_cdevsw = { 135 fcomopen, fcomclose, fcomread, fcomwrite, fcomioctl, 136 nostop, fcomtty, fcompoll, nommap, ttykqfilter, D_TTY 137 }; 138 139 void fcominit __P((bus_space_tag_t, bus_space_handle_t, int, int)); 140 void fcominitcons __P((bus_space_tag_t, bus_space_handle_t)); 141 142 bus_space_tag_t fcomconstag; 143 bus_space_handle_t fcomconsioh; 144 extern int comcnmode; 145 extern int comcnspeed; 146 147 #define COMUNIT(x) (minor(x)) 148 #ifndef CONUNIT 149 #define CONUNIT 0 150 #endif 151 152 /* 153 * The console is set up at init time, well in advance of the reset of the 154 * system and thus we have a private bus space tag for the console. 155 * 156 * The tag is provided by fcom_io.c and fcom_io_asm.S 157 */ 158 extern struct bus_space fcomcons_bs_tag; 159 160 /* 161 * int fcom_probe(struct device *parent, struct cfdata *cf, void *aux) 162 * 163 * Make sure we are trying to attach a com device and then 164 * probe for one. 165 */ 166 167 static int 168 fcom_probe(parent, cf, aux) 169 struct device *parent; 170 struct cfdata *cf; 171 void *aux; 172 { 173 union footbridge_attach_args *fba = aux; 174 175 if (strcmp(fba->fba_name, "fcom") == 0) 176 return(1); 177 return(0); 178 } 179 180 /* 181 * void fcom_attach(struct device *parent, struct device *self, void *aux) 182 * 183 * attach the com device 184 */ 185 186 static void 187 fcom_attach(parent, self, aux) 188 struct device *parent, *self; 189 void *aux; 190 { 191 union footbridge_attach_args *fba = aux; 192 struct fcom_softc *sc = (struct fcom_softc *)self; 193 194 /* Set up the softc */ 195 sc->sc_iot = fba->fba_fca.fca_iot; 196 sc->sc_ioh = fba->fba_fca.fca_ioh; 197 callout_init(&sc->sc_softintr_ch); 198 sc->sc_rx_irq = fba->fba_fca.fca_rx_irq; 199 sc->sc_tx_irq = fba->fba_fca.fca_tx_irq; 200 sc->sc_hwflags = 0; 201 sc->sc_swflags = 0; 202 203 /* If we have a console tag then make a note of it */ 204 if (fcomconstag) 205 sc->sc_hwflags |= HW_FLAG_CONSOLE; 206 207 if (sc->sc_hwflags & HW_FLAG_CONSOLE) { 208 int major; 209 210 /* locate the major number */ 211 major = cdevsw_lookup_major(&fcom_cdevsw); 212 213 cn_tab->cn_dev = makedev(major, sc->sc_dev.dv_unit); 214 printf(": console"); 215 } 216 printf("\n"); 217 218 sc->sc_ih = footbridge_intr_claim(sc->sc_rx_irq, IPL_SERIAL, 219 "serial rx", fcom_rxintr, sc); 220 if (sc->sc_ih == NULL) 221 panic("%s: Cannot install rx interrupt handler", 222 sc->sc_dev.dv_xname); 223 } 224 225 static void fcomstart __P((struct tty *)); 226 static int fcomparam __P((struct tty *, struct termios *)); 227 228 int 229 fcomopen(dev, flag, mode, l) 230 dev_t dev; 231 int flag, mode; 232 struct lwp *l; 233 { 234 struct proc *p = l->l_proc; 235 struct fcom_softc *sc; 236 int unit = minor(dev); 237 struct tty *tp; 238 239 if (unit >= fcom_cd.cd_ndevs) 240 return ENXIO; 241 sc = fcom_cd.cd_devs[unit]; 242 if (!sc) 243 return ENXIO; 244 if (!(tp = sc->sc_tty)) 245 sc->sc_tty = tp = ttymalloc(); 246 if (!sc->sc_rxbuffer[0]) { 247 sc->sc_rxbuffer[0] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK); 248 sc->sc_rxbuffer[1] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK); 249 sc->sc_rxpos = 0; 250 sc->sc_rxcur = 0; 251 sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur]; 252 if (!sc->sc_rxbuf) 253 panic("%s: Cannot allocate rx buffer memory", 254 sc->sc_dev.dv_xname); 255 } 256 tp->t_oproc = fcomstart; 257 tp->t_param = fcomparam; 258 tp->t_dev = dev; 259 if (!(tp->t_state & TS_ISOPEN && tp->t_wopen == 0)) { 260 ttychars(tp); 261 tp->t_cflag = TTYDEF_CFLAG; 262 tp->t_iflag = TTYDEF_IFLAG; 263 tp->t_oflag = TTYDEF_OFLAG; 264 tp->t_lflag = TTYDEF_LFLAG; 265 266 /* 267 * Initialize the termios status to the defaults. Add in the 268 * sticky bits from TIOCSFLAGS. 269 */ 270 tp->t_ispeed = 0; 271 if (ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE)) 272 tp->t_ospeed = comcnspeed; 273 else 274 tp->t_ospeed = TTYDEF_SPEED; 275 276 fcomparam(tp, &tp->t_termios); 277 ttsetwater(tp); 278 } else if ((tp->t_state&TS_XCLUDE) && suser(p->p_ucred, &p->p_acflag)) 279 return EBUSY; 280 tp->t_state |= TS_CARR_ON; 281 282 return (*tp->t_linesw->l_open)(dev, tp); 283 } 284 285 int 286 fcomclose(dev, flag, mode, l) 287 dev_t dev; 288 int flag, mode; 289 struct lwp *l; 290 { 291 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 292 struct tty *tp = sc->sc_tty; 293 /* XXX This is for cons.c. */ 294 if (!ISSET(tp->t_state, TS_ISOPEN)) 295 return (0); 296 297 (*tp->t_linesw->l_close)(tp, flag); 298 ttyclose(tp); 299 #ifdef DIAGNOSTIC 300 if (sc->sc_rxbuffer[0] == NULL) 301 panic("fcomclose: rx buffers not allocated"); 302 #endif /* DIAGNOSTIC */ 303 free(sc->sc_rxbuffer[0], M_DEVBUF); 304 free(sc->sc_rxbuffer[1], M_DEVBUF); 305 sc->sc_rxbuffer[0] = NULL; 306 sc->sc_rxbuffer[1] = NULL; 307 308 return 0; 309 } 310 311 int 312 fcomread(dev, uio, flag) 313 dev_t dev; 314 struct uio *uio; 315 int flag; 316 { 317 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 318 struct tty *tp = sc->sc_tty; 319 320 return (*tp->t_linesw->l_read)(tp, uio, flag); 321 } 322 323 int 324 fcomwrite(dev, uio, flag) 325 dev_t dev; 326 struct uio *uio; 327 int flag; 328 { 329 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 330 struct tty *tp = sc->sc_tty; 331 332 return (*tp->t_linesw->l_write)(tp, uio, flag); 333 } 334 335 int 336 fcompoll(dev, events, l) 337 dev_t dev; 338 int events; 339 struct lwp *l; 340 { 341 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 342 struct tty *tp = sc->sc_tty; 343 344 return ((*tp->t_linesw->l_poll)(tp, events, l)); 345 } 346 347 int 348 fcomioctl(dev, cmd, data, flag, l) 349 dev_t dev; 350 u_long cmd; 351 caddr_t data; 352 int flag; 353 struct lwp *l; 354 { 355 struct proc *p = l->l_proc; 356 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 357 struct tty *tp = sc->sc_tty; 358 int error; 359 360 if ((error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l)) != 361 EPASSTHROUGH) 362 return error; 363 if ((error = ttioctl(tp, cmd, data, flag, l)) != EPASSTHROUGH) 364 return error; 365 366 switch (cmd) { 367 case TIOCGFLAGS: 368 *(int *)data = sc->sc_swflags; 369 break; 370 371 case TIOCSFLAGS: 372 error = suser(p->p_ucred, &p->p_acflag); 373 if (error) 374 return (error); 375 sc->sc_swflags = *(int *)data; 376 break; 377 } 378 379 return EPASSTHROUGH; 380 } 381 382 struct tty * 383 fcomtty(dev) 384 dev_t dev; 385 { 386 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 387 388 return sc->sc_tty; 389 } 390 391 static void 392 fcomstart(tp) 393 struct tty *tp; 394 { 395 struct clist *cl; 396 int s, len; 397 u_char buf[64]; 398 int loop; 399 struct fcom_softc *sc = fcom_cd.cd_devs[minor(tp->t_dev)]; 400 bus_space_tag_t iot = sc->sc_iot; 401 bus_space_handle_t ioh = sc->sc_ioh; 402 int timo; 403 404 s = spltty(); 405 if (tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) { 406 (void)splx(s); 407 return; 408 } 409 tp->t_state |= TS_BUSY; 410 (void)splx(s); 411 412 /* s = splserial();*/ 413 /* wait for any pending transmission to finish */ 414 timo = 100000; 415 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 416 ; 417 418 s = splserial(); 419 if (bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) { 420 tp->t_state |= TS_TIMEOUT; 421 callout_reset(&tp->t_rstrt_ch, 1, ttrstrt, tp); 422 (void)splx(s); 423 return; 424 } 425 426 (void)splx(s); 427 428 cl = &tp->t_outq; 429 len = q_to_b(cl, buf, 64); 430 for (loop = 0; loop < len; ++loop) { 431 /* s = splserial();*/ 432 433 bus_space_write_4(iot, ioh, UART_DATA, buf[loop]); 434 435 /* wait for this transmission to complete */ 436 timo = 100000; 437 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 438 ; 439 /* (void)splx(s);*/ 440 } 441 s = spltty(); 442 tp->t_state &= ~TS_BUSY; 443 if (cl->c_cc) { 444 tp->t_state |= TS_TIMEOUT; 445 callout_reset(&tp->t_rstrt_ch, 1, ttrstrt, tp); 446 } 447 if (cl->c_cc <= tp->t_lowat) { 448 if (tp->t_state & TS_ASLEEP) { 449 tp->t_state &= ~TS_ASLEEP; 450 wakeup(cl); 451 } 452 selwakeup(&tp->t_wsel); 453 } 454 (void)splx(s); 455 } 456 457 static int 458 fcomparam(tp, t) 459 struct tty *tp; 460 struct termios *t; 461 { 462 struct fcom_softc *sc = fcom_cd.cd_devs[minor(tp->t_dev)]; 463 bus_space_tag_t iot = sc->sc_iot; 464 bus_space_handle_t ioh = sc->sc_ioh; 465 int baudrate; 466 int h_ubrlcr; 467 int m_ubrlcr; 468 int l_ubrlcr; 469 int s; 470 471 /* check requested parameters */ 472 if (t->c_ospeed < 0) 473 return (EINVAL); 474 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 475 return (EINVAL); 476 477 switch (t->c_ospeed) { 478 case B1200: 479 case B2400: 480 case B4800: 481 case B9600: 482 case B19200: 483 case B38400: 484 baudrate = UART_BRD(dc21285_fclk, t->c_ospeed); 485 break; 486 default: 487 baudrate = UART_BRD(dc21285_fclk, 9600); 488 break; 489 } 490 491 l_ubrlcr = baudrate & 0xff; 492 m_ubrlcr = (baudrate >> 8) & 0xf; 493 h_ubrlcr = 0; 494 495 switch (ISSET(t->c_cflag, CSIZE)) { 496 case CS5: 497 h_ubrlcr |= UART_DATA_BITS_5; 498 break; 499 case CS6: 500 h_ubrlcr |= UART_DATA_BITS_6; 501 break; 502 case CS7: 503 h_ubrlcr |= UART_DATA_BITS_7; 504 break; 505 case CS8: 506 h_ubrlcr |= UART_DATA_BITS_8; 507 break; 508 } 509 510 if (ISSET(t->c_cflag, PARENB)) { 511 h_ubrlcr |= UART_PARITY_ENABLE; 512 if (ISSET(t->c_cflag, PARODD)) 513 h_ubrlcr |= UART_ODD_PARITY; 514 else 515 h_ubrlcr |= UART_EVEN_PARITY; 516 } 517 518 if (ISSET(t->c_cflag, CSTOPB)) 519 h_ubrlcr |= UART_STOP_BITS_2; 520 521 bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr); 522 bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr); 523 bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr); 524 525 s = splserial(); 526 527 sc->sc_l_ubrlcr = l_ubrlcr; 528 sc->sc_m_ubrlcr = m_ubrlcr; 529 sc->sc_h_ubrlcr = h_ubrlcr; 530 531 /* 532 * For the console, always force CLOCAL and !HUPCL, so that the port 533 * is always active. 534 */ 535 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 536 ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE)) { 537 SET(t->c_cflag, CLOCAL); 538 CLR(t->c_cflag, HUPCL); 539 } 540 541 /* and copy to tty */ 542 tp->t_ispeed = 0; 543 tp->t_ospeed = t->c_ospeed; 544 tp->t_cflag = t->c_cflag; 545 546 bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr); 547 bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr); 548 bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr); 549 550 (void)splx(s); 551 552 return (0); 553 } 554 555 static int softint_scheduled = 0; 556 557 static void 558 fcom_softintr(arg) 559 void *arg; 560 { 561 struct fcom_softc *sc = arg; 562 struct tty *tp = sc->sc_tty; 563 int s; 564 int loop; 565 int len; 566 char *ptr; 567 568 s = spltty(); 569 ptr = sc->sc_rxbuf; 570 len = sc->sc_rxpos; 571 sc->sc_rxcur ^= 1; 572 sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur]; 573 sc->sc_rxpos = 0; 574 (void)splx(s); 575 576 for (loop = 0; loop < len; ++loop) 577 (*tp->t_linesw->l_rint)(ptr[loop], tp); 578 softint_scheduled = 0; 579 } 580 581 #if 0 582 static int 583 fcom_txintr(arg) 584 void *arg; 585 { 586 /* struct fcom_softc *sc = arg;*/ 587 588 printf("fcom_txintr()\n"); 589 return(0); 590 } 591 #endif 592 593 static int 594 fcom_rxintr(arg) 595 void *arg; 596 { 597 struct fcom_softc *sc = arg; 598 bus_space_tag_t iot = sc->sc_iot; 599 bus_space_handle_t ioh = sc->sc_ioh; 600 struct tty *tp = sc->sc_tty; 601 int status; 602 int byte; 603 604 do { 605 status = bus_space_read_4(iot, ioh, UART_FLAGS); 606 if ((status & UART_RX_FULL)) 607 break; 608 byte = bus_space_read_4(iot, ioh, UART_DATA); 609 status = bus_space_read_4(iot, ioh, UART_RX_STAT); 610 #if defined(DDB) && DDB_KEYCODE > 0 611 /* 612 * Temporary hack so that I can force the kernel into 613 * the debugger via the serial port 614 */ 615 if (byte == DDB_KEYCODE) Debugger(); 616 #endif 617 if (tp && (tp->t_state & TS_ISOPEN)) 618 if (sc->sc_rxpos < RX_BUFFER_SIZE) { 619 sc->sc_rxbuf[sc->sc_rxpos++] = byte; 620 if (!softint_scheduled) { 621 softint_scheduled = 1; 622 callout_reset(&sc->sc_softintr_ch, 623 1, fcom_softintr, sc); 624 } 625 } 626 } while (1); 627 return(0); 628 } 629 630 #if 0 631 void 632 fcom_iflush(sc) 633 struct fcom_softc *sc; 634 { 635 bus_space_tag_t iot = sc->sc_iot; 636 bus_space_handle_t ioh = sc->sc_ioh; 637 638 /* flush any pending I/O */ 639 while (!ISSET(bus_space_read_4(iot, ioh, UART_FLAGS), UART_RX_FULL)) 640 (void) bus_space_read_4(iot, ioh, UART_DATA); 641 } 642 #endif 643 644 /* 645 * Following are all routines needed for COM to act as console 646 */ 647 648 #if 0 649 void 650 fcomcnprobe(cp) 651 struct consdev *cp; 652 { 653 int major; 654 655 /* Serial console is always present so no probe */ 656 657 /* locate the major number */ 658 major = cdevsw_lookup_major(&fcom_cdevsw); 659 660 /* initialize required fields */ 661 cp->cn_dev = makedev(major, CONUNIT); 662 cp->cn_pri = CN_REMOTE; /* Force a serial port console */ 663 } 664 665 void 666 fcomcninit(cp) 667 struct consdev *cp; 668 { 669 fcomconstag = &fcomcons_bs_tag; 670 671 if (bus_space_map(fcomconstag, DC21285_ARMCSR_BASE, DC21285_ARMCSR_SIZE, 0, &fcomconsioh)) 672 panic("fcomcninit: mapping failed"); 673 674 fcominitcons(fcomconstag, fcomconsioh); 675 } 676 #endif 677 678 int 679 fcomcnattach(iobase, rate, cflag) 680 u_int iobase; 681 int rate; 682 tcflag_t cflag; 683 { 684 static struct consdev fcomcons = { 685 NULL, NULL, fcomcngetc, fcomcnputc, fcomcnpollc, NULL, 686 NULL, NULL, NODEV, CN_NORMAL 687 }; 688 689 fcomconstag = &fcomcons_bs_tag; 690 691 if (bus_space_map(fcomconstag, iobase, DC21285_ARMCSR_SIZE, 692 0, &fcomconsioh)) 693 panic("fcomcninit: mapping failed"); 694 695 fcominit(fcomconstag, fcomconsioh, rate, cflag); 696 697 cn_tab = &fcomcons; 698 699 /* comcnspeed = rate; 700 comcnmode = cflag;*/ 701 return (0); 702 } 703 704 int 705 fcomcndetach(void) 706 { 707 bus_space_unmap(fcomconstag, fcomconsioh, DC21285_ARMCSR_SIZE); 708 709 cn_tab = NULL; 710 return (0); 711 } 712 713 /* 714 * Initialize UART to known state. 715 */ 716 void 717 fcominit(iot, ioh, rate, mode) 718 bus_space_tag_t iot; 719 bus_space_handle_t ioh; 720 int rate; 721 int mode; 722 { 723 int baudrate; 724 int h_ubrlcr; 725 int m_ubrlcr; 726 int l_ubrlcr; 727 728 switch (rate) { 729 case B1200: 730 case B2400: 731 case B4800: 732 case B9600: 733 case B19200: 734 case B38400: 735 baudrate = UART_BRD(dc21285_fclk, rate); 736 break; 737 default: 738 baudrate = UART_BRD(dc21285_fclk, 9600); 739 break; 740 } 741 742 h_ubrlcr = 0; 743 switch (mode & CSIZE) { 744 case CS5: 745 h_ubrlcr |= UART_DATA_BITS_5; 746 break; 747 case CS6: 748 h_ubrlcr |= UART_DATA_BITS_6; 749 break; 750 case CS7: 751 h_ubrlcr |= UART_DATA_BITS_7; 752 break; 753 case CS8: 754 h_ubrlcr |= UART_DATA_BITS_8; 755 break; 756 } 757 758 if (mode & PARENB) 759 h_ubrlcr |= UART_PARITY_ENABLE; 760 if (mode & PARODD) 761 h_ubrlcr |= UART_ODD_PARITY; 762 else 763 h_ubrlcr |= UART_EVEN_PARITY; 764 765 if (mode & CSTOPB) 766 h_ubrlcr |= UART_STOP_BITS_2; 767 768 m_ubrlcr = (baudrate >> 8) & 0xf; 769 l_ubrlcr = baudrate & 0xff; 770 771 bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr); 772 bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr); 773 bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr); 774 } 775 #if 0 776 /* 777 * Set UART for console use. Do normal init, then enable interrupts. 778 */ 779 void 780 fcominitcons(iot, ioh) 781 bus_space_tag_t iot; 782 bus_space_handle_t ioh; 783 { 784 int s = splserial(); 785 786 fcominit(iot, ioh, comcnspeed, comcnmode); 787 788 delay(10000); 789 790 (void)splx(s); 791 } 792 #endif 793 794 int 795 fcomcngetc(dev) 796 dev_t dev; 797 { 798 int s = splserial(); 799 bus_space_tag_t iot = fcomconstag; 800 bus_space_handle_t ioh = fcomconsioh; 801 u_char stat, c; 802 803 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_RX_FULL) != 0) 804 ; 805 c = bus_space_read_4(iot, ioh, UART_DATA); 806 stat = bus_space_read_4(iot, ioh, UART_RX_STAT); 807 (void)splx(s); 808 #if defined(DDB) && DDB_KEYCODE > 0 809 /* 810 * Temporary hack so that I can force the kernel into 811 * the debugger via the serial port 812 */ 813 if (c == DDB_KEYCODE) Debugger(); 814 #endif 815 816 return (c); 817 } 818 819 /* 820 * Console kernel output character routine. 821 */ 822 void 823 fcomcnputc(dev, c) 824 dev_t dev; 825 int c; 826 { 827 int s = splserial(); 828 bus_space_tag_t iot = fcomconstag; 829 bus_space_handle_t ioh = fcomconsioh; 830 int timo; 831 832 /* wait for any pending transmission to finish */ 833 timo = 50000; 834 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 835 ; 836 bus_space_write_4(iot, ioh, UART_DATA, c); 837 838 /* wait for this transmission to complete */ 839 timo = 1500000; 840 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 841 ; 842 /* Clear interrupt status here */ 843 (void)splx(s); 844 } 845 846 void 847 fcomcnpollc(dev, on) 848 dev_t dev; 849 int on; 850 { 851 } 852
Indexes created Wed Oct 01 19:09:53 GMT 2025