footbridge_com.c revision 1.19
1 /* $NetBSD: footbridge_com.c,v 1.19 2006/05/14 21:55:10 elad Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 Mark Brinicombe 5 * Copyright (c) 1997 Causality Limited 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Mark Brinicombe 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * COM driver, using the footbridge UART 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: footbridge_com.c,v 1.19 2006/05/14 21:55:10 elad Exp $"); 40 41 #include "opt_ddb.h" 42 #include "opt_ddbparam.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/ioctl.h> 47 #include <sys/select.h> 48 #include <sys/tty.h> 49 #include <sys/proc.h> 50 #include <sys/conf.h> 51 #include <sys/syslog.h> 52 #include <sys/device.h> 53 #include <sys/malloc.h> 54 #include <sys/termios.h> 55 #include <sys/kauth.h> 56 #include <machine/bus.h> 57 #include <machine/intr.h> 58 #include <arm/footbridge/dc21285mem.h> 59 #include <arm/footbridge/dc21285reg.h> 60 #include <arm/footbridge/footbridgevar.h> 61 #include <arm/footbridge/footbridge.h> 62 63 #include <dev/cons.h> 64 65 #include "fcom.h" 66 67 extern u_int dc21285_fclk; 68 69 70 #ifdef DDB 71 /* 72 * Define the keycode recognised as a request to call the debugger 73 * A value of 0 disables the feature when DDB is built in 74 */ 75 #ifndef DDB_KEYCODE 76 #define DDB_KEYCODE 0 77 #endif /* DDB_KEYCODE */ 78 #endif /* DDB */ 79 80 struct fcom_softc { 81 struct device sc_dev; 82 bus_space_tag_t sc_iot; 83 bus_space_handle_t sc_ioh; 84 void *sc_ih; 85 struct callout sc_softintr_ch; 86 int sc_rx_irq; 87 int sc_tx_irq; 88 int sc_hwflags; 89 #define HW_FLAG_CONSOLE 0x01 90 int sc_swflags; 91 int sc_l_ubrlcr; 92 int sc_m_ubrlcr; 93 int sc_h_ubrlcr; 94 char *sc_rxbuffer[2]; 95 char *sc_rxbuf; 96 int sc_rxpos; 97 int sc_rxcur; 98 struct tty *sc_tty; 99 }; 100 101 #define RX_BUFFER_SIZE 0x100 102 103 static int fcom_probe __P((struct device *, struct cfdata *, void *)); 104 static void fcom_attach __P((struct device *, struct device *, void *)); 105 static void fcom_softintr __P((void *)); 106 107 static int fcom_rxintr __P((void *)); 108 /*static int fcom_txintr __P((void *));*/ 109 110 /*struct consdev;*/ 111 /*void fcomcnprobe __P((struct consdev *)); 112 void fcomcninit __P((struct consdev *));*/ 113 int fcomcngetc __P((dev_t)); 114 void fcomcnputc __P((dev_t, int)); 115 void fcomcnpollc __P((dev_t, int)); 116 117 CFATTACH_DECL(fcom, sizeof(struct fcom_softc), 118 fcom_probe, fcom_attach, NULL, NULL); 119 120 extern struct cfdriver fcom_cd; 121 122 dev_type_open(fcomopen); 123 dev_type_close(fcomclose); 124 dev_type_read(fcomread); 125 dev_type_write(fcomwrite); 126 dev_type_ioctl(fcomioctl); 127 dev_type_tty(fcomtty); 128 dev_type_poll(fcompoll); 129 130 const struct cdevsw fcom_cdevsw = { 131 fcomopen, fcomclose, fcomread, fcomwrite, fcomioctl, 132 nostop, fcomtty, fcompoll, nommap, ttykqfilter, D_TTY 133 }; 134 135 void fcominit __P((bus_space_tag_t, bus_space_handle_t, int, int)); 136 void fcominitcons __P((bus_space_tag_t, bus_space_handle_t)); 137 138 bus_space_tag_t fcomconstag; 139 bus_space_handle_t fcomconsioh; 140 extern int comcnmode; 141 extern int comcnspeed; 142 143 #define COMUNIT(x) (minor(x)) 144 #ifndef CONUNIT 145 #define CONUNIT 0 146 #endif 147 148 /* 149 * The console is set up at init time, well in advance of the reset of the 150 * system and thus we have a private bus space tag for the console. 151 * 152 * The tag is provided by fcom_io.c and fcom_io_asm.S 153 */ 154 extern struct bus_space fcomcons_bs_tag; 155 156 /* 157 * int fcom_probe(struct device *parent, struct cfdata *cf, void *aux) 158 * 159 * Make sure we are trying to attach a com device and then 160 * probe for one. 161 */ 162 163 static int 164 fcom_probe(parent, cf, aux) 165 struct device *parent; 166 struct cfdata *cf; 167 void *aux; 168 { 169 union footbridge_attach_args *fba = aux; 170 171 if (strcmp(fba->fba_name, "fcom") == 0) 172 return(1); 173 return(0); 174 } 175 176 /* 177 * void fcom_attach(struct device *parent, struct device *self, void *aux) 178 * 179 * attach the com device 180 */ 181 182 static void 183 fcom_attach(parent, self, aux) 184 struct device *parent, *self; 185 void *aux; 186 { 187 union footbridge_attach_args *fba = aux; 188 struct fcom_softc *sc = (struct fcom_softc *)self; 189 190 /* Set up the softc */ 191 sc->sc_iot = fba->fba_fca.fca_iot; 192 sc->sc_ioh = fba->fba_fca.fca_ioh; 193 callout_init(&sc->sc_softintr_ch); 194 sc->sc_rx_irq = fba->fba_fca.fca_rx_irq; 195 sc->sc_tx_irq = fba->fba_fca.fca_tx_irq; 196 sc->sc_hwflags = 0; 197 sc->sc_swflags = 0; 198 199 /* If we have a console tag then make a note of it */ 200 if (fcomconstag) 201 sc->sc_hwflags |= HW_FLAG_CONSOLE; 202 203 if (sc->sc_hwflags & HW_FLAG_CONSOLE) { 204 int major; 205 206 /* locate the major number */ 207 major = cdevsw_lookup_major(&fcom_cdevsw); 208 209 cn_tab->cn_dev = makedev(major, device_unit(&sc->sc_dev)); 210 printf(": console"); 211 } 212 printf("\n"); 213 214 sc->sc_ih = footbridge_intr_claim(sc->sc_rx_irq, IPL_SERIAL, 215 "serial rx", fcom_rxintr, sc); 216 if (sc->sc_ih == NULL) 217 panic("%s: Cannot install rx interrupt handler", 218 sc->sc_dev.dv_xname); 219 } 220 221 static void fcomstart __P((struct tty *)); 222 static int fcomparam __P((struct tty *, struct termios *)); 223 224 int 225 fcomopen(dev, flag, mode, l) 226 dev_t dev; 227 int flag, mode; 228 struct lwp *l; 229 { 230 struct proc *p = l->l_proc; 231 struct fcom_softc *sc; 232 int unit = minor(dev); 233 struct tty *tp; 234 235 if (unit >= fcom_cd.cd_ndevs) 236 return ENXIO; 237 sc = fcom_cd.cd_devs[unit]; 238 if (!sc) 239 return ENXIO; 240 if (!(tp = sc->sc_tty)) 241 sc->sc_tty = tp = ttymalloc(); 242 if (!sc->sc_rxbuffer[0]) { 243 sc->sc_rxbuffer[0] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK); 244 sc->sc_rxbuffer[1] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK); 245 sc->sc_rxpos = 0; 246 sc->sc_rxcur = 0; 247 sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur]; 248 if (!sc->sc_rxbuf) 249 panic("%s: Cannot allocate rx buffer memory", 250 sc->sc_dev.dv_xname); 251 } 252 tp->t_oproc = fcomstart; 253 tp->t_param = fcomparam; 254 tp->t_dev = dev; 255 if (!(tp->t_state & TS_ISOPEN && tp->t_wopen == 0)) { 256 ttychars(tp); 257 tp->t_cflag = TTYDEF_CFLAG; 258 tp->t_iflag = TTYDEF_IFLAG; 259 tp->t_oflag = TTYDEF_OFLAG; 260 tp->t_lflag = TTYDEF_LFLAG; 261 262 /* 263 * Initialize the termios status to the defaults. Add in the 264 * sticky bits from TIOCSFLAGS. 265 */ 266 tp->t_ispeed = 0; 267 if (ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE)) 268 tp->t_ospeed = comcnspeed; 269 else 270 tp->t_ospeed = TTYDEF_SPEED; 271 272 fcomparam(tp, &tp->t_termios); 273 ttsetwater(tp); 274 } else if ((tp->t_state&TS_XCLUDE) && 275 kauth_authorize_generic(p->p_cred, KAUTH_GENERIC_ISSUSER, &p->p_acflag)) 276 return EBUSY; 277 tp->t_state |= TS_CARR_ON; 278 279 return (*tp->t_linesw->l_open)(dev, tp); 280 } 281 282 int 283 fcomclose(dev, flag, mode, l) 284 dev_t dev; 285 int flag, mode; 286 struct lwp *l; 287 { 288 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 289 struct tty *tp = sc->sc_tty; 290 /* XXX This is for cons.c. */ 291 if (!ISSET(tp->t_state, TS_ISOPEN)) 292 return (0); 293 294 (*tp->t_linesw->l_close)(tp, flag); 295 ttyclose(tp); 296 #ifdef DIAGNOSTIC 297 if (sc->sc_rxbuffer[0] == NULL) 298 panic("fcomclose: rx buffers not allocated"); 299 #endif /* DIAGNOSTIC */ 300 free(sc->sc_rxbuffer[0], M_DEVBUF); 301 free(sc->sc_rxbuffer[1], M_DEVBUF); 302 sc->sc_rxbuffer[0] = NULL; 303 sc->sc_rxbuffer[1] = NULL; 304 305 return 0; 306 } 307 308 int 309 fcomread(dev, uio, flag) 310 dev_t dev; 311 struct uio *uio; 312 int flag; 313 { 314 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 315 struct tty *tp = sc->sc_tty; 316 317 return (*tp->t_linesw->l_read)(tp, uio, flag); 318 } 319 320 int 321 fcomwrite(dev, uio, flag) 322 dev_t dev; 323 struct uio *uio; 324 int flag; 325 { 326 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 327 struct tty *tp = sc->sc_tty; 328 329 return (*tp->t_linesw->l_write)(tp, uio, flag); 330 } 331 332 int 333 fcompoll(dev, events, l) 334 dev_t dev; 335 int events; 336 struct lwp *l; 337 { 338 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 339 struct tty *tp = sc->sc_tty; 340 341 return ((*tp->t_linesw->l_poll)(tp, events, l)); 342 } 343 344 int 345 fcomioctl(dev, cmd, data, flag, l) 346 dev_t dev; 347 u_long cmd; 348 caddr_t data; 349 int flag; 350 struct lwp *l; 351 { 352 struct proc *p = l->l_proc; 353 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 354 struct tty *tp = sc->sc_tty; 355 int error; 356 357 if ((error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l)) != 358 EPASSTHROUGH) 359 return error; 360 if ((error = ttioctl(tp, cmd, data, flag, l)) != EPASSTHROUGH) 361 return error; 362 363 switch (cmd) { 364 case TIOCGFLAGS: 365 *(int *)data = sc->sc_swflags; 366 break; 367 368 case TIOCSFLAGS: 369 error = kauth_authorize_generic(p->p_cred, KAUTH_GENERIC_ISSUSER, &p->p_acflag); 370 if (error) 371 return (error); 372 sc->sc_swflags = *(int *)data; 373 break; 374 } 375 376 return EPASSTHROUGH; 377 } 378 379 struct tty * 380 fcomtty(dev) 381 dev_t dev; 382 { 383 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 384 385 return sc->sc_tty; 386 } 387 388 static void 389 fcomstart(tp) 390 struct tty *tp; 391 { 392 struct clist *cl; 393 int s, len; 394 u_char buf[64]; 395 int loop; 396 struct fcom_softc *sc = fcom_cd.cd_devs[minor(tp->t_dev)]; 397 bus_space_tag_t iot = sc->sc_iot; 398 bus_space_handle_t ioh = sc->sc_ioh; 399 int timo; 400 401 s = spltty(); 402 if (tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) { 403 (void)splx(s); 404 return; 405 } 406 tp->t_state |= TS_BUSY; 407 (void)splx(s); 408 409 /* s = splserial();*/ 410 /* wait for any pending transmission to finish */ 411 timo = 100000; 412 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 413 ; 414 415 s = splserial(); 416 if (bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) { 417 tp->t_state |= TS_TIMEOUT; 418 callout_reset(&tp->t_rstrt_ch, 1, ttrstrt, tp); 419 (void)splx(s); 420 return; 421 } 422 423 (void)splx(s); 424 425 cl = &tp->t_outq; 426 len = q_to_b(cl, buf, 64); 427 for (loop = 0; loop < len; ++loop) { 428 /* s = splserial();*/ 429 430 bus_space_write_4(iot, ioh, UART_DATA, buf[loop]); 431 432 /* wait for this transmission to complete */ 433 timo = 100000; 434 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 435 ; 436 /* (void)splx(s);*/ 437 } 438 s = spltty(); 439 tp->t_state &= ~TS_BUSY; 440 if (cl->c_cc) { 441 tp->t_state |= TS_TIMEOUT; 442 callout_reset(&tp->t_rstrt_ch, 1, ttrstrt, tp); 443 } 444 if (cl->c_cc <= tp->t_lowat) { 445 if (tp->t_state & TS_ASLEEP) { 446 tp->t_state &= ~TS_ASLEEP; 447 wakeup(cl); 448 } 449 selwakeup(&tp->t_wsel); 450 } 451 (void)splx(s); 452 } 453 454 static int 455 fcomparam(tp, t) 456 struct tty *tp; 457 struct termios *t; 458 { 459 struct fcom_softc *sc = fcom_cd.cd_devs[minor(tp->t_dev)]; 460 bus_space_tag_t iot = sc->sc_iot; 461 bus_space_handle_t ioh = sc->sc_ioh; 462 int baudrate; 463 int h_ubrlcr; 464 int m_ubrlcr; 465 int l_ubrlcr; 466 int s; 467 468 /* check requested parameters */ 469 if (t->c_ospeed < 0) 470 return (EINVAL); 471 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 472 return (EINVAL); 473 474 switch (t->c_ospeed) { 475 case B1200: 476 case B2400: 477 case B4800: 478 case B9600: 479 case B19200: 480 case B38400: 481 baudrate = UART_BRD(dc21285_fclk, t->c_ospeed); 482 break; 483 default: 484 baudrate = UART_BRD(dc21285_fclk, 9600); 485 break; 486 } 487 488 l_ubrlcr = baudrate & 0xff; 489 m_ubrlcr = (baudrate >> 8) & 0xf; 490 h_ubrlcr = 0; 491 492 switch (ISSET(t->c_cflag, CSIZE)) { 493 case CS5: 494 h_ubrlcr |= UART_DATA_BITS_5; 495 break; 496 case CS6: 497 h_ubrlcr |= UART_DATA_BITS_6; 498 break; 499 case CS7: 500 h_ubrlcr |= UART_DATA_BITS_7; 501 break; 502 case CS8: 503 h_ubrlcr |= UART_DATA_BITS_8; 504 break; 505 } 506 507 if (ISSET(t->c_cflag, PARENB)) { 508 h_ubrlcr |= UART_PARITY_ENABLE; 509 if (ISSET(t->c_cflag, PARODD)) 510 h_ubrlcr |= UART_ODD_PARITY; 511 else 512 h_ubrlcr |= UART_EVEN_PARITY; 513 } 514 515 if (ISSET(t->c_cflag, CSTOPB)) 516 h_ubrlcr |= UART_STOP_BITS_2; 517 518 bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr); 519 bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr); 520 bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr); 521 522 s = splserial(); 523 524 sc->sc_l_ubrlcr = l_ubrlcr; 525 sc->sc_m_ubrlcr = m_ubrlcr; 526 sc->sc_h_ubrlcr = h_ubrlcr; 527 528 /* 529 * For the console, always force CLOCAL and !HUPCL, so that the port 530 * is always active. 531 */ 532 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 533 ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE)) { 534 SET(t->c_cflag, CLOCAL); 535 CLR(t->c_cflag, HUPCL); 536 } 537 538 /* and copy to tty */ 539 tp->t_ispeed = 0; 540 tp->t_ospeed = t->c_ospeed; 541 tp->t_cflag = t->c_cflag; 542 543 bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr); 544 bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr); 545 bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr); 546 547 (void)splx(s); 548 549 return (0); 550 } 551 552 static int softint_scheduled = 0; 553 554 static void 555 fcom_softintr(arg) 556 void *arg; 557 { 558 struct fcom_softc *sc = arg; 559 struct tty *tp = sc->sc_tty; 560 int s; 561 int loop; 562 int len; 563 char *ptr; 564 565 s = spltty(); 566 ptr = sc->sc_rxbuf; 567 len = sc->sc_rxpos; 568 sc->sc_rxcur ^= 1; 569 sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur]; 570 sc->sc_rxpos = 0; 571 (void)splx(s); 572 573 for (loop = 0; loop < len; ++loop) 574 (*tp->t_linesw->l_rint)(ptr[loop], tp); 575 softint_scheduled = 0; 576 } 577 578 #if 0 579 static int 580 fcom_txintr(arg) 581 void *arg; 582 { 583 /* struct fcom_softc *sc = arg;*/ 584 585 printf("fcom_txintr()\n"); 586 return(0); 587 } 588 #endif 589 590 static int 591 fcom_rxintr(arg) 592 void *arg; 593 { 594 struct fcom_softc *sc = arg; 595 bus_space_tag_t iot = sc->sc_iot; 596 bus_space_handle_t ioh = sc->sc_ioh; 597 struct tty *tp = sc->sc_tty; 598 int status; 599 int byte; 600 601 do { 602 status = bus_space_read_4(iot, ioh, UART_FLAGS); 603 if ((status & UART_RX_FULL)) 604 break; 605 byte = bus_space_read_4(iot, ioh, UART_DATA); 606 status = bus_space_read_4(iot, ioh, UART_RX_STAT); 607 #if defined(DDB) && DDB_KEYCODE > 0 608 /* 609 * Temporary hack so that I can force the kernel into 610 * the debugger via the serial port 611 */ 612 if (byte == DDB_KEYCODE) Debugger(); 613 #endif 614 if (tp && (tp->t_state & TS_ISOPEN)) 615 if (sc->sc_rxpos < RX_BUFFER_SIZE) { 616 sc->sc_rxbuf[sc->sc_rxpos++] = byte; 617 if (!softint_scheduled) { 618 softint_scheduled = 1; 619 callout_reset(&sc->sc_softintr_ch, 620 1, fcom_softintr, sc); 621 } 622 } 623 } while (1); 624 return(0); 625 } 626 627 #if 0 628 void 629 fcom_iflush(sc) 630 struct fcom_softc *sc; 631 { 632 bus_space_tag_t iot = sc->sc_iot; 633 bus_space_handle_t ioh = sc->sc_ioh; 634 635 /* flush any pending I/O */ 636 while (!ISSET(bus_space_read_4(iot, ioh, UART_FLAGS), UART_RX_FULL)) 637 (void) bus_space_read_4(iot, ioh, UART_DATA); 638 } 639 #endif 640 641 /* 642 * Following are all routines needed for COM to act as console 643 */ 644 645 #if 0 646 void 647 fcomcnprobe(cp) 648 struct consdev *cp; 649 { 650 int major; 651 652 /* Serial console is always present so no probe */ 653 654 /* locate the major number */ 655 major = cdevsw_lookup_major(&fcom_cdevsw); 656 657 /* initialize required fields */ 658 cp->cn_dev = makedev(major, CONUNIT); 659 cp->cn_pri = CN_REMOTE; /* Force a serial port console */ 660 } 661 662 void 663 fcomcninit(cp) 664 struct consdev *cp; 665 { 666 fcomconstag = &fcomcons_bs_tag; 667 668 if (bus_space_map(fcomconstag, DC21285_ARMCSR_BASE, DC21285_ARMCSR_SIZE, 0, &fcomconsioh)) 669 panic("fcomcninit: mapping failed"); 670 671 fcominitcons(fcomconstag, fcomconsioh); 672 } 673 #endif 674 675 int 676 fcomcnattach(iobase, rate, cflag) 677 u_int iobase; 678 int rate; 679 tcflag_t cflag; 680 { 681 static struct consdev fcomcons = { 682 NULL, NULL, fcomcngetc, fcomcnputc, fcomcnpollc, NULL, 683 NULL, NULL, NODEV, CN_NORMAL 684 }; 685 686 fcomconstag = &fcomcons_bs_tag; 687 688 if (bus_space_map(fcomconstag, iobase, DC21285_ARMCSR_SIZE, 689 0, &fcomconsioh)) 690 panic("fcomcninit: mapping failed"); 691 692 fcominit(fcomconstag, fcomconsioh, rate, cflag); 693 694 cn_tab = &fcomcons; 695 696 /* comcnspeed = rate; 697 comcnmode = cflag;*/ 698 return (0); 699 } 700 701 int 702 fcomcndetach(void) 703 { 704 bus_space_unmap(fcomconstag, fcomconsioh, DC21285_ARMCSR_SIZE); 705 706 cn_tab = NULL; 707 return (0); 708 } 709 710 /* 711 * Initialize UART to known state. 712 */ 713 void 714 fcominit(iot, ioh, rate, mode) 715 bus_space_tag_t iot; 716 bus_space_handle_t ioh; 717 int rate; 718 int mode; 719 { 720 int baudrate; 721 int h_ubrlcr; 722 int m_ubrlcr; 723 int l_ubrlcr; 724 725 switch (rate) { 726 case B1200: 727 case B2400: 728 case B4800: 729 case B9600: 730 case B19200: 731 case B38400: 732 baudrate = UART_BRD(dc21285_fclk, rate); 733 break; 734 default: 735 baudrate = UART_BRD(dc21285_fclk, 9600); 736 break; 737 } 738 739 h_ubrlcr = 0; 740 switch (mode & CSIZE) { 741 case CS5: 742 h_ubrlcr |= UART_DATA_BITS_5; 743 break; 744 case CS6: 745 h_ubrlcr |= UART_DATA_BITS_6; 746 break; 747 case CS7: 748 h_ubrlcr |= UART_DATA_BITS_7; 749 break; 750 case CS8: 751 h_ubrlcr |= UART_DATA_BITS_8; 752 break; 753 } 754 755 if (mode & PARENB) 756 h_ubrlcr |= UART_PARITY_ENABLE; 757 if (mode & PARODD) 758 h_ubrlcr |= UART_ODD_PARITY; 759 else 760 h_ubrlcr |= UART_EVEN_PARITY; 761 762 if (mode & CSTOPB) 763 h_ubrlcr |= UART_STOP_BITS_2; 764 765 m_ubrlcr = (baudrate >> 8) & 0xf; 766 l_ubrlcr = baudrate & 0xff; 767 768 bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr); 769 bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr); 770 bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr); 771 } 772 #if 0 773 /* 774 * Set UART for console use. Do normal init, then enable interrupts. 775 */ 776 void 777 fcominitcons(iot, ioh) 778 bus_space_tag_t iot; 779 bus_space_handle_t ioh; 780 { 781 int s = splserial(); 782 783 fcominit(iot, ioh, comcnspeed, comcnmode); 784 785 delay(10000); 786 787 (void)splx(s); 788 } 789 #endif 790 791 int 792 fcomcngetc(dev) 793 dev_t dev; 794 { 795 int s = splserial(); 796 bus_space_tag_t iot = fcomconstag; 797 bus_space_handle_t ioh = fcomconsioh; 798 u_char stat, c; 799 800 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_RX_FULL) != 0) 801 ; 802 c = bus_space_read_4(iot, ioh, UART_DATA); 803 stat = bus_space_read_4(iot, ioh, UART_RX_STAT); 804 (void)splx(s); 805 #if defined(DDB) && DDB_KEYCODE > 0 806 /* 807 * Temporary hack so that I can force the kernel into 808 * the debugger via the serial port 809 */ 810 if (c == DDB_KEYCODE) Debugger(); 811 #endif 812 813 return (c); 814 } 815 816 /* 817 * Console kernel output character routine. 818 */ 819 void 820 fcomcnputc(dev, c) 821 dev_t dev; 822 int c; 823 { 824 int s = splserial(); 825 bus_space_tag_t iot = fcomconstag; 826 bus_space_handle_t ioh = fcomconsioh; 827 int timo; 828 829 /* wait for any pending transmission to finish */ 830 timo = 50000; 831 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 832 ; 833 bus_space_write_4(iot, ioh, UART_DATA, c); 834 835 /* wait for this transmission to complete */ 836 timo = 1500000; 837 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 838 ; 839 /* Clear interrupt status here */ 840 (void)splx(s); 841 } 842 843 void 844 fcomcnpollc(dev, on) 845 dev_t dev; 846 int on; 847 { 848 } 849
Indexes created Thu Oct 02 01:09:59 GMT 2025