footbridge_com.c revision 1.27
1 /* $NetBSD: footbridge_com.c,v 1.27 2007/11/19 18:51:38 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 Mark Brinicombe 5 * Copyright (c) 1997 Causality Limited 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Mark Brinicombe 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * COM driver, using the footbridge UART 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: footbridge_com.c,v 1.27 2007/11/19 18:51:38 ad Exp $"); 40 41 #include "opt_ddb.h" 42 #include "opt_ddbparam.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/ioctl.h> 47 #include <sys/select.h> 48 #include <sys/tty.h> 49 #include <sys/proc.h> 50 #include <sys/conf.h> 51 #include <sys/syslog.h> 52 #include <sys/device.h> 53 #include <sys/malloc.h> 54 #include <sys/termios.h> 55 #include <sys/kauth.h> 56 #include <machine/bus.h> 57 #include <machine/intr.h> 58 #include <arm/footbridge/dc21285mem.h> 59 #include <arm/footbridge/dc21285reg.h> 60 #include <arm/footbridge/footbridgevar.h> 61 #include <arm/footbridge/footbridge.h> 62 63 #include <dev/cons.h> 64 65 #include "fcom.h" 66 67 extern u_int dc21285_fclk; 68 69 70 #ifdef DDB 71 /* 72 * Define the keycode recognised as a request to call the debugger 73 * A value of 0 disables the feature when DDB is built in 74 */ 75 #ifndef DDB_KEYCODE 76 #define DDB_KEYCODE 0 77 #endif /* DDB_KEYCODE */ 78 #endif /* DDB */ 79 80 struct fcom_softc { 81 struct device sc_dev; 82 bus_space_tag_t sc_iot; 83 bus_space_handle_t sc_ioh; 84 void *sc_ih; 85 struct callout sc_softintr_ch; 86 int sc_rx_irq; 87 int sc_tx_irq; 88 int sc_hwflags; 89 #define HW_FLAG_CONSOLE 0x01 90 int sc_swflags; 91 int sc_l_ubrlcr; 92 int sc_m_ubrlcr; 93 int sc_h_ubrlcr; 94 char *sc_rxbuffer[2]; 95 char *sc_rxbuf; 96 int sc_rxpos; 97 int sc_rxcur; 98 struct tty *sc_tty; 99 }; 100 101 #define RX_BUFFER_SIZE 0x100 102 103 static int fcom_probe __P((struct device *, struct cfdata *, void *)); 104 static void fcom_attach __P((struct device *, struct device *, void *)); 105 static void fcom_softintr __P((void *)); 106 107 static int fcom_rxintr __P((void *)); 108 /*static int fcom_txintr __P((void *));*/ 109 110 /*struct consdev;*/ 111 /*void fcomcnprobe __P((struct consdev *)); 112 void fcomcninit __P((struct consdev *));*/ 113 int fcomcngetc __P((dev_t)); 114 void fcomcnputc __P((dev_t, int)); 115 void fcomcnpollc __P((dev_t, int)); 116 117 CFATTACH_DECL(fcom, sizeof(struct fcom_softc), 118 fcom_probe, fcom_attach, NULL, NULL); 119 120 extern struct cfdriver fcom_cd; 121 122 dev_type_open(fcomopen); 123 dev_type_close(fcomclose); 124 dev_type_read(fcomread); 125 dev_type_write(fcomwrite); 126 dev_type_ioctl(fcomioctl); 127 dev_type_tty(fcomtty); 128 dev_type_poll(fcompoll); 129 130 const struct cdevsw fcom_cdevsw = { 131 fcomopen, fcomclose, fcomread, fcomwrite, fcomioctl, 132 nostop, fcomtty, fcompoll, nommap, ttykqfilter, D_TTY 133 }; 134 135 void fcominit __P((bus_space_tag_t, bus_space_handle_t, int, int)); 136 void fcominitcons __P((bus_space_tag_t, bus_space_handle_t)); 137 138 bus_space_tag_t fcomconstag; 139 bus_space_handle_t fcomconsioh; 140 extern int comcnmode; 141 extern int comcnspeed; 142 143 #define COMUNIT(x) (minor(x)) 144 #ifndef CONUNIT 145 #define CONUNIT 0 146 #endif 147 148 /* 149 * The console is set up at init time, well in advance of the reset of the 150 * system and thus we have a private bus space tag for the console. 151 * 152 * The tag is provided by fcom_io.c and fcom_io_asm.S 153 */ 154 extern struct bus_space fcomcons_bs_tag; 155 156 /* 157 * int fcom_probe(struct device *parent, struct cfdata *cf, void *aux) 158 * 159 * Make sure we are trying to attach a com device and then 160 * probe for one. 161 */ 162 163 static int 164 fcom_probe(parent, cf, aux) 165 struct device *parent; 166 struct cfdata *cf; 167 void *aux; 168 { 169 union footbridge_attach_args *fba = aux; 170 171 if (strcmp(fba->fba_name, "fcom") == 0) 172 return(1); 173 return(0); 174 } 175 176 /* 177 * void fcom_attach(struct device *parent, struct device *self, void *aux) 178 * 179 * attach the com device 180 */ 181 182 static void 183 fcom_attach(parent, self, aux) 184 struct device *parent, *self; 185 void *aux; 186 { 187 union footbridge_attach_args *fba = aux; 188 struct fcom_softc *sc = (struct fcom_softc *)self; 189 190 /* Set up the softc */ 191 sc->sc_iot = fba->fba_fca.fca_iot; 192 sc->sc_ioh = fba->fba_fca.fca_ioh; 193 callout_init(&sc->sc_softintr_ch, 0); 194 sc->sc_rx_irq = fba->fba_fca.fca_rx_irq; 195 sc->sc_tx_irq = fba->fba_fca.fca_tx_irq; 196 sc->sc_hwflags = 0; 197 sc->sc_swflags = 0; 198 199 /* If we have a console tag then make a note of it */ 200 if (fcomconstag) 201 sc->sc_hwflags |= HW_FLAG_CONSOLE; 202 203 if (sc->sc_hwflags & HW_FLAG_CONSOLE) { 204 int major; 205 206 /* locate the major number */ 207 major = cdevsw_lookup_major(&fcom_cdevsw); 208 209 cn_tab->cn_dev = makedev(major, device_unit(&sc->sc_dev)); 210 printf(": console"); 211 } 212 printf("\n"); 213 214 sc->sc_ih = footbridge_intr_claim(sc->sc_rx_irq, IPL_SERIAL, 215 "serial rx", fcom_rxintr, sc); 216 if (sc->sc_ih == NULL) 217 panic("%s: Cannot install rx interrupt handler", 218 sc->sc_dev.dv_xname); 219 } 220 221 static void fcomstart __P((struct tty *)); 222 static int fcomparam __P((struct tty *, struct termios *)); 223 224 int 225 fcomopen(dev, flag, mode, l) 226 dev_t dev; 227 int flag, mode; 228 struct lwp *l; 229 { 230 struct fcom_softc *sc; 231 int unit = minor(dev); 232 struct tty *tp; 233 234 if (unit >= fcom_cd.cd_ndevs) 235 return ENXIO; 236 sc = fcom_cd.cd_devs[unit]; 237 if (!sc) 238 return ENXIO; 239 if (!(tp = sc->sc_tty)) 240 sc->sc_tty = tp = ttymalloc(); 241 if (!sc->sc_rxbuffer[0]) { 242 sc->sc_rxbuffer[0] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK); 243 sc->sc_rxbuffer[1] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK); 244 sc->sc_rxpos = 0; 245 sc->sc_rxcur = 0; 246 sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur]; 247 if (!sc->sc_rxbuf) 248 panic("%s: Cannot allocate rx buffer memory", 249 sc->sc_dev.dv_xname); 250 } 251 tp->t_oproc = fcomstart; 252 tp->t_param = fcomparam; 253 tp->t_dev = dev; 254 255 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 256 return (EBUSY); 257 258 if (!(tp->t_state & TS_ISOPEN && tp->t_wopen == 0)) { 259 ttychars(tp); 260 tp->t_cflag = TTYDEF_CFLAG; 261 tp->t_iflag = TTYDEF_IFLAG; 262 tp->t_oflag = TTYDEF_OFLAG; 263 tp->t_lflag = TTYDEF_LFLAG; 264 265 /* 266 * Initialize the termios status to the defaults. Add in the 267 * sticky bits from TIOCSFLAGS. 268 */ 269 tp->t_ispeed = 0; 270 if (ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE)) 271 tp->t_ospeed = comcnspeed; 272 else 273 tp->t_ospeed = TTYDEF_SPEED; 274 275 fcomparam(tp, &tp->t_termios); 276 ttsetwater(tp); 277 } 278 tp->t_state |= TS_CARR_ON; 279 280 return (*tp->t_linesw->l_open)(dev, tp); 281 } 282 283 int 284 fcomclose(dev, flag, mode, l) 285 dev_t dev; 286 int flag, mode; 287 struct lwp *l; 288 { 289 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 290 struct tty *tp = sc->sc_tty; 291 /* XXX This is for cons.c. */ 292 if (!ISSET(tp->t_state, TS_ISOPEN)) 293 return (0); 294 295 (*tp->t_linesw->l_close)(tp, flag); 296 ttyclose(tp); 297 #ifdef DIAGNOSTIC 298 if (sc->sc_rxbuffer[0] == NULL) 299 panic("fcomclose: rx buffers not allocated"); 300 #endif /* DIAGNOSTIC */ 301 free(sc->sc_rxbuffer[0], M_DEVBUF); 302 free(sc->sc_rxbuffer[1], M_DEVBUF); 303 sc->sc_rxbuffer[0] = NULL; 304 sc->sc_rxbuffer[1] = NULL; 305 306 return 0; 307 } 308 309 int 310 fcomread(dev, uio, flag) 311 dev_t dev; 312 struct uio *uio; 313 int flag; 314 { 315 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 316 struct tty *tp = sc->sc_tty; 317 318 return (*tp->t_linesw->l_read)(tp, uio, flag); 319 } 320 321 int 322 fcomwrite(dev, uio, flag) 323 dev_t dev; 324 struct uio *uio; 325 int flag; 326 { 327 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 328 struct tty *tp = sc->sc_tty; 329 330 return (*tp->t_linesw->l_write)(tp, uio, flag); 331 } 332 333 int 334 fcompoll(dev, events, l) 335 dev_t dev; 336 int events; 337 struct lwp *l; 338 { 339 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 340 struct tty *tp = sc->sc_tty; 341 342 return ((*tp->t_linesw->l_poll)(tp, events, l)); 343 } 344 345 int 346 fcomioctl(dev, cmd, data, flag, l) 347 dev_t dev; 348 u_long cmd; 349 void *data; 350 int flag; 351 struct lwp *l; 352 { 353 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 354 struct tty *tp = sc->sc_tty; 355 int error; 356 357 if ((error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l)) != 358 EPASSTHROUGH) 359 return error; 360 if ((error = ttioctl(tp, cmd, data, flag, l)) != EPASSTHROUGH) 361 return error; 362 363 switch (cmd) { 364 case TIOCGFLAGS: 365 *(int *)data = sc->sc_swflags; 366 break; 367 368 case TIOCSFLAGS: 369 error = kauth_authorize_device_tty(l->l_cred, 370 KAUTH_DEVICE_TTY_PRIVSET, tp); 371 if (error) 372 return (error); 373 sc->sc_swflags = *(int *)data; 374 break; 375 } 376 377 return EPASSTHROUGH; 378 } 379 380 struct tty * 381 fcomtty(dev) 382 dev_t dev; 383 { 384 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 385 386 return sc->sc_tty; 387 } 388 389 static void 390 fcomstart(tp) 391 struct tty *tp; 392 { 393 struct clist *cl; 394 int s, len; 395 u_char buf[64]; 396 int loop; 397 struct fcom_softc *sc = fcom_cd.cd_devs[minor(tp->t_dev)]; 398 bus_space_tag_t iot = sc->sc_iot; 399 bus_space_handle_t ioh = sc->sc_ioh; 400 int timo; 401 402 s = spltty(); 403 if (tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) { 404 (void)splx(s); 405 return; 406 } 407 tp->t_state |= TS_BUSY; 408 (void)splx(s); 409 410 /* s = splserial();*/ 411 /* wait for any pending transmission to finish */ 412 timo = 100000; 413 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 414 ; 415 416 s = splserial(); 417 if (bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) { 418 tp->t_state |= TS_TIMEOUT; 419 callout_schedule(&tp->t_rstrt_ch, 1); 420 (void)splx(s); 421 return; 422 } 423 424 (void)splx(s); 425 426 cl = &tp->t_outq; 427 len = q_to_b(cl, buf, 64); 428 for (loop = 0; loop < len; ++loop) { 429 /* s = splserial();*/ 430 431 bus_space_write_4(iot, ioh, UART_DATA, buf[loop]); 432 433 /* wait for this transmission to complete */ 434 timo = 100000; 435 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 436 ; 437 /* (void)splx(s);*/ 438 } 439 s = spltty(); 440 tp->t_state &= ~TS_BUSY; 441 if (ttypull(tp)) { 442 tp->t_state |= TS_TIMEOUT; 443 callout_schedule(&tp->t_rstrt_ch, 1); 444 } 445 (void)splx(s); 446 } 447 448 static int 449 fcomparam(tp, t) 450 struct tty *tp; 451 struct termios *t; 452 { 453 struct fcom_softc *sc = fcom_cd.cd_devs[minor(tp->t_dev)]; 454 bus_space_tag_t iot = sc->sc_iot; 455 bus_space_handle_t ioh = sc->sc_ioh; 456 int baudrate; 457 int h_ubrlcr; 458 int m_ubrlcr; 459 int l_ubrlcr; 460 int s; 461 462 /* check requested parameters */ 463 if (t->c_ospeed < 0) 464 return (EINVAL); 465 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 466 return (EINVAL); 467 468 switch (t->c_ospeed) { 469 case B1200: 470 case B2400: 471 case B4800: 472 case B9600: 473 case B19200: 474 case B38400: 475 baudrate = UART_BRD(dc21285_fclk, t->c_ospeed); 476 break; 477 default: 478 baudrate = UART_BRD(dc21285_fclk, 9600); 479 break; 480 } 481 482 l_ubrlcr = baudrate & 0xff; 483 m_ubrlcr = (baudrate >> 8) & 0xf; 484 h_ubrlcr = 0; 485 486 switch (ISSET(t->c_cflag, CSIZE)) { 487 case CS5: 488 h_ubrlcr |= UART_DATA_BITS_5; 489 break; 490 case CS6: 491 h_ubrlcr |= UART_DATA_BITS_6; 492 break; 493 case CS7: 494 h_ubrlcr |= UART_DATA_BITS_7; 495 break; 496 case CS8: 497 h_ubrlcr |= UART_DATA_BITS_8; 498 break; 499 } 500 501 if (ISSET(t->c_cflag, PARENB)) { 502 h_ubrlcr |= UART_PARITY_ENABLE; 503 if (ISSET(t->c_cflag, PARODD)) 504 h_ubrlcr |= UART_ODD_PARITY; 505 else 506 h_ubrlcr |= UART_EVEN_PARITY; 507 } 508 509 if (ISSET(t->c_cflag, CSTOPB)) 510 h_ubrlcr |= UART_STOP_BITS_2; 511 512 bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr); 513 bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr); 514 bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr); 515 516 s = splserial(); 517 518 sc->sc_l_ubrlcr = l_ubrlcr; 519 sc->sc_m_ubrlcr = m_ubrlcr; 520 sc->sc_h_ubrlcr = h_ubrlcr; 521 522 /* 523 * For the console, always force CLOCAL and !HUPCL, so that the port 524 * is always active. 525 */ 526 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 527 ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE)) { 528 SET(t->c_cflag, CLOCAL); 529 CLR(t->c_cflag, HUPCL); 530 } 531 532 /* and copy to tty */ 533 tp->t_ispeed = 0; 534 tp->t_ospeed = t->c_ospeed; 535 tp->t_cflag = t->c_cflag; 536 537 bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr); 538 bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr); 539 bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr); 540 541 (void)splx(s); 542 543 return (0); 544 } 545 546 static int softint_scheduled = 0; 547 548 static void 549 fcom_softintr(arg) 550 void *arg; 551 { 552 struct fcom_softc *sc = arg; 553 struct tty *tp = sc->sc_tty; 554 int s; 555 int loop; 556 int len; 557 char *ptr; 558 559 s = spltty(); 560 ptr = sc->sc_rxbuf; 561 len = sc->sc_rxpos; 562 sc->sc_rxcur ^= 1; 563 sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur]; 564 sc->sc_rxpos = 0; 565 (void)splx(s); 566 567 for (loop = 0; loop < len; ++loop) 568 (*tp->t_linesw->l_rint)(ptr[loop], tp); 569 softint_scheduled = 0; 570 } 571 572 #if 0 573 static int 574 fcom_txintr(arg) 575 void *arg; 576 { 577 /* struct fcom_softc *sc = arg;*/ 578 579 printf("fcom_txintr()\n"); 580 return(0); 581 } 582 #endif 583 584 static int 585 fcom_rxintr(arg) 586 void *arg; 587 { 588 struct fcom_softc *sc = arg; 589 bus_space_tag_t iot = sc->sc_iot; 590 bus_space_handle_t ioh = sc->sc_ioh; 591 struct tty *tp = sc->sc_tty; 592 int status; 593 int byte; 594 595 do { 596 status = bus_space_read_4(iot, ioh, UART_FLAGS); 597 if ((status & UART_RX_FULL)) 598 break; 599 byte = bus_space_read_4(iot, ioh, UART_DATA); 600 status = bus_space_read_4(iot, ioh, UART_RX_STAT); 601 #if defined(DDB) && DDB_KEYCODE > 0 602 /* 603 * Temporary hack so that I can force the kernel into 604 * the debugger via the serial port 605 */ 606 if (byte == DDB_KEYCODE) Debugger(); 607 #endif 608 if (tp && (tp->t_state & TS_ISOPEN)) 609 if (sc->sc_rxpos < RX_BUFFER_SIZE) { 610 sc->sc_rxbuf[sc->sc_rxpos++] = byte; 611 if (!softint_scheduled) { 612 softint_scheduled = 1; 613 callout_reset(&sc->sc_softintr_ch, 614 1, fcom_softintr, sc); 615 } 616 } 617 } while (1); 618 return(0); 619 } 620 621 #if 0 622 void 623 fcom_iflush(sc) 624 struct fcom_softc *sc; 625 { 626 bus_space_tag_t iot = sc->sc_iot; 627 bus_space_handle_t ioh = sc->sc_ioh; 628 629 /* flush any pending I/O */ 630 while (!ISSET(bus_space_read_4(iot, ioh, UART_FLAGS), UART_RX_FULL)) 631 (void) bus_space_read_4(iot, ioh, UART_DATA); 632 } 633 #endif 634 635 /* 636 * Following are all routines needed for COM to act as console 637 */ 638 639 #if 0 640 void 641 fcomcnprobe(cp) 642 struct consdev *cp; 643 { 644 int major; 645 646 /* Serial console is always present so no probe */ 647 648 /* locate the major number */ 649 major = cdevsw_lookup_major(&fcom_cdevsw); 650 651 /* initialize required fields */ 652 cp->cn_dev = makedev(major, CONUNIT); 653 cp->cn_pri = CN_REMOTE; /* Force a serial port console */ 654 } 655 656 void 657 fcomcninit(cp) 658 struct consdev *cp; 659 { 660 fcomconstag = &fcomcons_bs_tag; 661 662 if (bus_space_map(fcomconstag, DC21285_ARMCSR_BASE, DC21285_ARMCSR_SIZE, 0, &fcomconsioh)) 663 panic("fcomcninit: mapping failed"); 664 665 fcominitcons(fcomconstag, fcomconsioh); 666 } 667 #endif 668 669 int 670 fcomcnattach(iobase, rate, cflag) 671 u_int iobase; 672 int rate; 673 tcflag_t cflag; 674 { 675 static struct consdev fcomcons = { 676 NULL, NULL, fcomcngetc, fcomcnputc, fcomcnpollc, NULL, 677 NULL, NULL, NODEV, CN_NORMAL 678 }; 679 680 fcomconstag = &fcomcons_bs_tag; 681 682 if (bus_space_map(fcomconstag, iobase, DC21285_ARMCSR_SIZE, 683 0, &fcomconsioh)) 684 panic("fcomcninit: mapping failed"); 685 686 fcominit(fcomconstag, fcomconsioh, rate, cflag); 687 688 cn_tab = &fcomcons; 689 690 /* comcnspeed = rate; 691 comcnmode = cflag;*/ 692 return (0); 693 } 694 695 int 696 fcomcndetach(void) 697 { 698 bus_space_unmap(fcomconstag, fcomconsioh, DC21285_ARMCSR_SIZE); 699 700 cn_tab = NULL; 701 return (0); 702 } 703 704 /* 705 * Initialize UART to known state. 706 */ 707 void 708 fcominit(iot, ioh, rate, mode) 709 bus_space_tag_t iot; 710 bus_space_handle_t ioh; 711 int rate; 712 int mode; 713 { 714 int baudrate; 715 int h_ubrlcr; 716 int m_ubrlcr; 717 int l_ubrlcr; 718 719 switch (rate) { 720 case B1200: 721 case B2400: 722 case B4800: 723 case B9600: 724 case B19200: 725 case B38400: 726 baudrate = UART_BRD(dc21285_fclk, rate); 727 break; 728 default: 729 baudrate = UART_BRD(dc21285_fclk, 9600); 730 break; 731 } 732 733 h_ubrlcr = 0; 734 switch (mode & CSIZE) { 735 case CS5: 736 h_ubrlcr |= UART_DATA_BITS_5; 737 break; 738 case CS6: 739 h_ubrlcr |= UART_DATA_BITS_6; 740 break; 741 case CS7: 742 h_ubrlcr |= UART_DATA_BITS_7; 743 break; 744 case CS8: 745 h_ubrlcr |= UART_DATA_BITS_8; 746 break; 747 } 748 749 if (mode & PARENB) 750 h_ubrlcr |= UART_PARITY_ENABLE; 751 if (mode & PARODD) 752 h_ubrlcr |= UART_ODD_PARITY; 753 else 754 h_ubrlcr |= UART_EVEN_PARITY; 755 756 if (mode & CSTOPB) 757 h_ubrlcr |= UART_STOP_BITS_2; 758 759 m_ubrlcr = (baudrate >> 8) & 0xf; 760 l_ubrlcr = baudrate & 0xff; 761 762 bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr); 763 bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr); 764 bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr); 765 } 766 #if 0 767 /* 768 * Set UART for console use. Do normal init, then enable interrupts. 769 */ 770 void 771 fcominitcons(iot, ioh) 772 bus_space_tag_t iot; 773 bus_space_handle_t ioh; 774 { 775 int s = splserial(); 776 777 fcominit(iot, ioh, comcnspeed, comcnmode); 778 779 delay(10000); 780 781 (void)splx(s); 782 } 783 #endif 784 785 int 786 fcomcngetc(dev) 787 dev_t dev; 788 { 789 int s = splserial(); 790 bus_space_tag_t iot = fcomconstag; 791 bus_space_handle_t ioh = fcomconsioh; 792 u_char stat, c; 793 794 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_RX_FULL) != 0) 795 ; 796 c = bus_space_read_4(iot, ioh, UART_DATA); 797 stat = bus_space_read_4(iot, ioh, UART_RX_STAT); 798 (void)splx(s); 799 #if defined(DDB) && DDB_KEYCODE > 0 800 /* 801 * Temporary hack so that I can force the kernel into 802 * the debugger via the serial port 803 */ 804 if (c == DDB_KEYCODE) Debugger(); 805 #endif 806 807 return (c); 808 } 809 810 /* 811 * Console kernel output character routine. 812 */ 813 void 814 fcomcnputc(dev, c) 815 dev_t dev; 816 int c; 817 { 818 int s = splserial(); 819 bus_space_tag_t iot = fcomconstag; 820 bus_space_handle_t ioh = fcomconsioh; 821 int timo; 822 823 /* wait for any pending transmission to finish */ 824 timo = 50000; 825 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 826 ; 827 bus_space_write_4(iot, ioh, UART_DATA, c); 828 829 /* wait for this transmission to complete */ 830 timo = 1500000; 831 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 832 ; 833 /* Clear interrupt status here */ 834 (void)splx(s); 835 } 836 837 void 838 fcomcnpollc(dev, on) 839 dev_t dev; 840 int on; 841 { 842 } 843
Indexes created Thu Oct 02 01:09:59 GMT 2025