footbridge_com.c revision 1.3
1 /* $NetBSD: footbridge_com.c,v 1.3 2002/01/05 22:41:47 chris Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 Mark Brinicombe 5 * Copyright (c) 1997 Causality Limited 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Mark Brinicombe 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * COM driver, using the footbridge UART 36 */ 37 38 #include "opt_ddb.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/ioctl.h> 43 #include <sys/select.h> 44 #include <sys/tty.h> 45 #include <sys/proc.h> 46 #include <sys/conf.h> 47 #include <sys/syslog.h> 48 #include <sys/device.h> 49 #include <sys/malloc.h> 50 #include <sys/termios.h> 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 #include <arm/conf.h> 54 #include <arm/footbridge/dc21285mem.h> 55 #include <arm/footbridge/dc21285reg.h> 56 #include <arm/footbridge/footbridgevar.h> 57 #include <arm/footbridge/footbridge.h> 58 59 #include <dev/cons.h> 60 61 #include "fcom.h" 62 63 extern u_int dc21285_fclk; 64 65 66 #ifdef DDB 67 /* 68 * Define the keycode recognised as a request to call the debugger 69 * A value of 0 disables the feature when DDB is built in 70 */ 71 #ifndef DDB_KEYCODE 72 #define DDB_KEYCODE 0 73 #endif /* DDB_KEYCODE */ 74 #endif /* DDB */ 75 76 struct fcom_softc { 77 struct device sc_dev; 78 bus_space_tag_t sc_iot; 79 bus_space_handle_t sc_ioh; 80 void *sc_ih; 81 struct callout sc_softintr_ch; 82 int sc_rx_irq; 83 int sc_tx_irq; 84 int sc_hwflags; 85 #define HW_FLAG_CONSOLE 0x01 86 int sc_swflags; 87 int sc_l_ubrlcr; 88 int sc_m_ubrlcr; 89 int sc_h_ubrlcr; 90 char *sc_rxbuffer[2]; 91 char *sc_rxbuf; 92 int sc_rxpos; 93 int sc_rxcur; 94 struct tty *sc_tty; 95 }; 96 97 #define RX_BUFFER_SIZE 0x100 98 99 /* Macros to clear/set/test flags. */ 100 #define SET(t, f) (t) |= (f) 101 #define CLR(t, f) (t) &= ~(f) 102 #define ISSET(t, f) ((t) & (f)) 103 104 static int fcom_probe __P((struct device *, struct cfdata *, void *)); 105 static void fcom_attach __P((struct device *, struct device *, void *)); 106 static void fcom_softintr __P((void *)); 107 108 int fcomopen __P((dev_t dev, int flag, int mode, struct proc *p)); 109 static int fcom_rxintr __P((void *)); 110 /*static int fcom_txintr __P((void *));*/ 111 112 /*struct consdev;*/ 113 /*void fcomcnprobe __P((struct consdev *)); 114 void fcomcninit __P((struct consdev *));*/ 115 int fcomcngetc __P((dev_t)); 116 void fcomcnputc __P((dev_t, int)); 117 void fcomcnpollc __P((dev_t, int)); 118 119 struct cfattach fcom_ca = { 120 sizeof(struct fcom_softc), fcom_probe, fcom_attach 121 }; 122 123 extern struct cfdriver fcom_cd; 124 125 void fcominit __P((bus_space_tag_t, bus_space_handle_t, int, int)); 126 void fcominitcons __P((bus_space_tag_t, bus_space_handle_t)); 127 128 bus_space_tag_t fcomconstag; 129 bus_space_handle_t fcomconsioh; 130 extern int comcnmode; 131 extern int comcnspeed; 132 133 #define COMUNIT(x) (minor(x)) 134 #ifndef CONUNIT 135 #define CONUNIT 0 136 #endif 137 138 /* 139 * The console is set up at init time, well in advance of the reset of the 140 * system and thus we have a private bus space tag for the console. 141 * 142 * The tag is provided by fcom_io.c and fcom_io_asm.S 143 */ 144 extern struct bus_space fcomcons_bs_tag; 145 146 /* 147 * int fcom_probe(struct device *parent, struct cfdata *cf, void *aux) 148 * 149 * Make sure we are trying to attach a com device and then 150 * probe for one. 151 */ 152 153 static int 154 fcom_probe(parent, cf, aux) 155 struct device *parent; 156 struct cfdata *cf; 157 void *aux; 158 { 159 union footbridge_attach_args *fba = aux; 160 161 if (strcmp(fba->fba_name, "fcom") == 0) 162 return(1); 163 return(0); 164 } 165 166 /* 167 * void fcom_attach(struct device *parent, struct device *self, void *aux) 168 * 169 * attach the com device 170 */ 171 172 static void 173 fcom_attach(parent, self, aux) 174 struct device *parent, *self; 175 void *aux; 176 { 177 union footbridge_attach_args *fba = aux; 178 struct fcom_softc *sc = (struct fcom_softc *)self; 179 180 /* Set up the softc */ 181 sc->sc_iot = fba->fba_fca.fca_iot; 182 sc->sc_ioh = fba->fba_fca.fca_ioh; 183 callout_init(&sc->sc_softintr_ch); 184 sc->sc_rx_irq = fba->fba_fca.fca_rx_irq; 185 sc->sc_tx_irq = fba->fba_fca.fca_tx_irq; 186 sc->sc_hwflags = 0; 187 sc->sc_swflags = 0; 188 189 /* If we have a console tag then make a note of it */ 190 if (fcomconstag) 191 sc->sc_hwflags |= HW_FLAG_CONSOLE; 192 193 if (sc->sc_hwflags & HW_FLAG_CONSOLE) { 194 int major; 195 196 /* locate the major number */ 197 for (major = 0; major < nchrdev; ++major) 198 if (cdevsw[major].d_open == fcomopen) 199 break; 200 201 cn_tab->cn_dev = makedev(major, sc->sc_dev.dv_unit); 202 printf(": console"); 203 } 204 printf("\n"); 205 206 sc->sc_ih = intr_claim(sc->sc_rx_irq, IPL_SERIAL, "serial rx", 207 fcom_rxintr, sc); 208 if (sc->sc_ih == NULL) 209 panic("%s: Cannot install rx interrupt handler\n", 210 sc->sc_dev.dv_xname); 211 } 212 213 static void fcomstart __P((struct tty *)); 214 static int fcomparam __P((struct tty *, struct termios *)); 215 216 int 217 fcomopen(dev, flag, mode, p) 218 dev_t dev; 219 int flag, mode; 220 struct proc *p; 221 { 222 struct fcom_softc *sc; 223 int unit = minor(dev); 224 struct tty *tp; 225 226 if (unit >= fcom_cd.cd_ndevs) 227 return ENXIO; 228 sc = fcom_cd.cd_devs[unit]; 229 if (!sc) 230 return ENXIO; 231 if (!(tp = sc->sc_tty)) 232 sc->sc_tty = tp = ttymalloc(); 233 if (!sc->sc_rxbuffer[0]) { 234 sc->sc_rxbuffer[0] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK); 235 sc->sc_rxbuffer[1] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK); 236 sc->sc_rxpos = 0; 237 sc->sc_rxcur = 0; 238 sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur]; 239 if (!sc->sc_rxbuf) 240 panic("%s: Cannot allocate rx buffer memory", 241 sc->sc_dev.dv_xname); 242 } 243 tp->t_oproc = fcomstart; 244 tp->t_param = fcomparam; 245 tp->t_dev = dev; 246 if (!(tp->t_state & TS_ISOPEN && tp->t_wopen == 0)) { 247 ttychars(tp); 248 tp->t_cflag = TTYDEF_CFLAG; 249 tp->t_iflag = TTYDEF_IFLAG; 250 tp->t_oflag = TTYDEF_OFLAG; 251 tp->t_lflag = TTYDEF_LFLAG; 252 253 /* 254 * Initialize the termios status to the defaults. Add in the 255 * sticky bits from TIOCSFLAGS. 256 */ 257 tp->t_ispeed = 0; 258 if (ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE)) 259 tp->t_ospeed = comcnspeed; 260 else 261 tp->t_ospeed = TTYDEF_SPEED; 262 263 fcomparam(tp, &tp->t_termios); 264 ttsetwater(tp); 265 } else if ((tp->t_state&TS_XCLUDE) && suser(p->p_ucred, &p->p_acflag)) 266 return EBUSY; 267 tp->t_state |= TS_CARR_ON; 268 269 return (*tp->t_linesw->l_open)(dev, tp); 270 } 271 272 int 273 fcomclose(dev, flag, mode, p) 274 dev_t dev; 275 int flag, mode; 276 struct proc *p; 277 { 278 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 279 struct tty *tp = sc->sc_tty; 280 /* XXX This is for cons.c. */ 281 if (!ISSET(tp->t_state, TS_ISOPEN)) 282 return (0); 283 284 (*tp->t_linesw->l_close)(tp, flag); 285 ttyclose(tp); 286 #ifdef DIAGNOSTIC 287 if (sc->sc_rxbuffer[0] == NULL) 288 panic("fcomclose: rx buffers not allocated\n"); 289 #endif /* DIAGNOSTIC */ 290 free(sc->sc_rxbuffer[0], M_DEVBUF); 291 free(sc->sc_rxbuffer[1], M_DEVBUF); 292 sc->sc_rxbuffer[0] = NULL; 293 sc->sc_rxbuffer[1] = NULL; 294 295 return 0; 296 } 297 298 int 299 fcomread(dev, uio, flag) 300 dev_t dev; 301 struct uio *uio; 302 int flag; 303 { 304 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 305 struct tty *tp = sc->sc_tty; 306 307 return (*tp->t_linesw->l_read)(tp, uio, flag); 308 } 309 310 int 311 fcomwrite(dev, uio, flag) 312 dev_t dev; 313 struct uio *uio; 314 int flag; 315 { 316 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 317 struct tty *tp = sc->sc_tty; 318 319 return (*tp->t_linesw->l_write)(tp, uio, flag); 320 } 321 322 int 323 fcompoll(dev, events, p) 324 dev_t dev; 325 int events; 326 struct proc *p; 327 { 328 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 329 struct tty *tp = sc->sc_tty; 330 331 return ((*tp->t_linesw->l_poll)(tp, events, p)); 332 } 333 334 int 335 fcomioctl(dev, cmd, data, flag, p) 336 dev_t dev; 337 u_long cmd; 338 caddr_t data; 339 int flag; 340 struct proc *p; 341 { 342 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 343 struct tty *tp = sc->sc_tty; 344 int error; 345 346 if ((error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p)) >= 0) 347 return error; 348 if ((error = ttioctl(tp, cmd, data, flag, p)) >= 0) 349 return error; 350 351 switch (cmd) { 352 case TIOCGFLAGS: 353 *(int *)data = sc->sc_swflags; 354 break; 355 356 case TIOCSFLAGS: 357 error = suser(p->p_ucred, &p->p_acflag); 358 if (error) 359 return (error); 360 sc->sc_swflags = *(int *)data; 361 break; 362 } 363 364 return ENOTTY; 365 } 366 367 struct tty * 368 fcomtty(dev) 369 dev_t dev; 370 { 371 struct fcom_softc *sc = fcom_cd.cd_devs[minor(dev)]; 372 373 return sc->sc_tty; 374 } 375 376 void 377 fcomstop(tp, flag) 378 struct tty *tp; 379 int flag; 380 { 381 } 382 383 static void 384 fcomstart(tp) 385 struct tty *tp; 386 { 387 struct clist *cl; 388 int s, len; 389 u_char buf[64]; 390 int loop; 391 struct fcom_softc *sc = fcom_cd.cd_devs[minor(tp->t_dev)]; 392 bus_space_tag_t iot = sc->sc_iot; 393 bus_space_handle_t ioh = sc->sc_ioh; 394 int timo; 395 396 s = spltty(); 397 if (tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) { 398 (void)splx(s); 399 return; 400 } 401 tp->t_state |= TS_BUSY; 402 (void)splx(s); 403 404 /* s = splserial();*/ 405 /* wait for any pending transmission to finish */ 406 timo = 100000; 407 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 408 ; 409 410 s = splserial(); 411 if (bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) { 412 tp->t_state |= TS_TIMEOUT; 413 callout_reset(&tp->t_rstrt_ch, 1, ttrstrt, tp); 414 (void)splx(s); 415 return; 416 } 417 418 (void)splx(s); 419 420 cl = &tp->t_outq; 421 len = q_to_b(cl, buf, 64); 422 for (loop = 0; loop < len; ++loop) { 423 /* s = splserial();*/ 424 425 bus_space_write_4(iot, ioh, UART_DATA, buf[loop]); 426 427 /* wait for this transmission to complete */ 428 timo = 100000; 429 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 430 ; 431 /* (void)splx(s);*/ 432 } 433 s = spltty(); 434 tp->t_state &= ~TS_BUSY; 435 if (cl->c_cc) { 436 tp->t_state |= TS_TIMEOUT; 437 callout_reset(&tp->t_rstrt_ch, 1, ttrstrt, tp); 438 } 439 if (cl->c_cc <= tp->t_lowat) { 440 if (tp->t_state & TS_ASLEEP) { 441 tp->t_state &= ~TS_ASLEEP; 442 wakeup(cl); 443 } 444 selwakeup(&tp->t_wsel); 445 } 446 (void)splx(s); 447 } 448 449 static int 450 fcomparam(tp, t) 451 struct tty *tp; 452 struct termios *t; 453 { 454 struct fcom_softc *sc = fcom_cd.cd_devs[minor(tp->t_dev)]; 455 bus_space_tag_t iot = sc->sc_iot; 456 bus_space_handle_t ioh = sc->sc_ioh; 457 int baudrate; 458 int h_ubrlcr; 459 int m_ubrlcr; 460 int l_ubrlcr; 461 int s; 462 463 /* check requested parameters */ 464 if (t->c_ospeed < 0) 465 return (EINVAL); 466 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 467 return (EINVAL); 468 469 switch (t->c_ospeed) { 470 case B1200: 471 case B2400: 472 case B4800: 473 case B9600: 474 case B19200: 475 case B38400: 476 baudrate = UART_BRD(dc21285_fclk, t->c_ospeed); 477 break; 478 default: 479 baudrate = UART_BRD(dc21285_fclk, 9600); 480 break; 481 } 482 483 l_ubrlcr = baudrate & 0xff; 484 m_ubrlcr = (baudrate >> 8) & 0xf; 485 h_ubrlcr = 0; 486 487 switch (ISSET(t->c_cflag, CSIZE)) { 488 case CS5: 489 h_ubrlcr |= UART_DATA_BITS_5; 490 break; 491 case CS6: 492 h_ubrlcr |= UART_DATA_BITS_6; 493 break; 494 case CS7: 495 h_ubrlcr |= UART_DATA_BITS_7; 496 break; 497 case CS8: 498 h_ubrlcr |= UART_DATA_BITS_8; 499 break; 500 } 501 502 if (ISSET(t->c_cflag, PARENB)) { 503 h_ubrlcr |= UART_PARITY_ENABLE; 504 if (ISSET(t->c_cflag, PARODD)) 505 h_ubrlcr |= UART_ODD_PARITY; 506 else 507 h_ubrlcr |= UART_EVEN_PARITY; 508 } 509 510 if (ISSET(t->c_cflag, CSTOPB)) 511 h_ubrlcr |= UART_STOP_BITS_2; 512 513 bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr); 514 bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr); 515 bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr); 516 517 s = splserial(); 518 519 sc->sc_l_ubrlcr = l_ubrlcr; 520 sc->sc_m_ubrlcr = m_ubrlcr; 521 sc->sc_h_ubrlcr = h_ubrlcr; 522 523 /* 524 * For the console, always force CLOCAL and !HUPCL, so that the port 525 * is always active. 526 */ 527 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 528 ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE)) { 529 SET(t->c_cflag, CLOCAL); 530 CLR(t->c_cflag, HUPCL); 531 } 532 533 /* and copy to tty */ 534 tp->t_ispeed = 0; 535 tp->t_ospeed = t->c_ospeed; 536 tp->t_cflag = t->c_cflag; 537 538 bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr); 539 bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr); 540 bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr); 541 542 (void)splx(s); 543 544 return (0); 545 } 546 547 static int softint_scheduled = 0; 548 549 static void 550 fcom_softintr(arg) 551 void *arg; 552 { 553 struct fcom_softc *sc = arg; 554 struct tty *tp = sc->sc_tty; 555 int s; 556 int loop; 557 int len; 558 char *ptr; 559 560 s = spltty(); 561 ptr = sc->sc_rxbuf; 562 len = sc->sc_rxpos; 563 sc->sc_rxcur ^= 1; 564 sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur]; 565 sc->sc_rxpos = 0; 566 (void)splx(s); 567 568 for (loop = 0; loop < len; ++loop) 569 (*tp->t_linesw->l_rint)(ptr[loop], tp); 570 softint_scheduled = 0; 571 } 572 573 #if 0 574 static int 575 fcom_txintr(arg) 576 void *arg; 577 { 578 /* struct fcom_softc *sc = arg;*/ 579 580 printf("fcom_txintr()\n"); 581 return(0); 582 } 583 #endif 584 585 static int 586 fcom_rxintr(arg) 587 void *arg; 588 { 589 struct fcom_softc *sc = arg; 590 bus_space_tag_t iot = sc->sc_iot; 591 bus_space_handle_t ioh = sc->sc_ioh; 592 struct tty *tp = sc->sc_tty; 593 int status; 594 int byte; 595 596 do { 597 status = bus_space_read_4(iot, ioh, UART_FLAGS); 598 if ((status & UART_RX_FULL)) 599 break; 600 byte = bus_space_read_4(iot, ioh, UART_DATA); 601 status = bus_space_read_4(iot, ioh, UART_RX_STAT); 602 #if DDB_KEYCODE > 0 603 /* 604 * Temporary hack so that I can force the kernel into 605 * the debugger via the serial port 606 */ 607 if (byte == DDB_KEYCODE) Debugger(); 608 #endif 609 if (tp && (tp->t_state & TS_ISOPEN)) 610 if (sc->sc_rxpos < RX_BUFFER_SIZE) { 611 sc->sc_rxbuf[sc->sc_rxpos++] = byte; 612 if (!softint_scheduled) { 613 softint_scheduled = 1; 614 callout_reset(&sc->sc_softintr_ch, 615 1, fcom_softintr, sc); 616 } 617 } 618 } while (1); 619 return(0); 620 } 621 622 #if 0 623 void 624 fcom_iflush(sc) 625 struct fcom_softc *sc; 626 { 627 bus_space_tag_t iot = sc->sc_iot; 628 bus_space_handle_t ioh = sc->sc_ioh; 629 630 /* flush any pending I/O */ 631 while (!ISSET(bus_space_read_4(iot, ioh, UART_FLAGS), UART_RX_FULL)) 632 (void) bus_space_read_4(iot, ioh, UART_DATA); 633 } 634 #endif 635 636 /* 637 * Following are all routines needed for COM to act as console 638 */ 639 640 #if 0 641 void 642 fcomcnprobe(cp) 643 struct consdev *cp; 644 { 645 int major; 646 647 /* Serial console is always present so no probe */ 648 649 /* locate the major number */ 650 for (major = 0; major < nchrdev; major++) 651 if (cdevsw[major].d_open == fcomopen) 652 break; 653 654 /* initialize required fields */ 655 cp->cn_dev = makedev(major, CONUNIT); 656 cp->cn_pri = CN_REMOTE; /* Force a serial port console */ 657 } 658 659 void 660 fcomcninit(cp) 661 struct consdev *cp; 662 { 663 fcomconstag = &fcomcons_bs_tag; 664 665 if (bus_space_map(fcomconstag, DC21285_ARMCSR_BASE, DC21285_ARMCSR_SIZE, 0, &fcomconsioh)) 666 panic("fcomcninit: mapping failed"); 667 668 fcominitcons(fcomconstag, fcomconsioh); 669 } 670 #endif 671 672 int 673 fcomcnattach(iobase, rate, cflag) 674 u_int iobase; 675 int rate; 676 tcflag_t cflag; 677 { 678 static struct consdev fcomcons = { 679 NULL, NULL, fcomcngetc, fcomcnputc, fcomcnpollc, NULL, 680 NODEV, CN_NORMAL 681 }; 682 683 fcomconstag = &fcomcons_bs_tag; 684 685 if (bus_space_map(fcomconstag, iobase, DC21285_ARMCSR_SIZE, 686 0, &fcomconsioh)) 687 panic("fcomcninit: mapping failed"); 688 689 fcominit(fcomconstag, fcomconsioh, rate, cflag); 690 691 cn_tab = &fcomcons; 692 693 /* comcnspeed = rate; 694 comcnmode = cflag;*/ 695 return (0); 696 } 697 698 int 699 fcomcndetach(void) 700 { 701 bus_space_unmap(fcomconstag, fcomconsioh, DC21285_ARMCSR_SIZE); 702 703 cn_tab = NULL; 704 return (0); 705 } 706 707 /* 708 * Initialize UART to known state. 709 */ 710 void 711 fcominit(iot, ioh, rate, mode) 712 bus_space_tag_t iot; 713 bus_space_handle_t ioh; 714 int rate; 715 int mode; 716 { 717 int baudrate; 718 int h_ubrlcr; 719 int m_ubrlcr; 720 int l_ubrlcr; 721 722 switch (rate) { 723 case B1200: 724 case B2400: 725 case B4800: 726 case B9600: 727 case B19200: 728 case B38400: 729 baudrate = UART_BRD(dc21285_fclk, rate); 730 break; 731 default: 732 baudrate = UART_BRD(dc21285_fclk, 9600); 733 break; 734 } 735 736 h_ubrlcr = 0; 737 switch (mode & CSIZE) { 738 case CS5: 739 h_ubrlcr |= UART_DATA_BITS_5; 740 break; 741 case CS6: 742 h_ubrlcr |= UART_DATA_BITS_6; 743 break; 744 case CS7: 745 h_ubrlcr |= UART_DATA_BITS_7; 746 break; 747 case CS8: 748 h_ubrlcr |= UART_DATA_BITS_8; 749 break; 750 } 751 752 if (mode & PARENB) 753 h_ubrlcr |= UART_PARITY_ENABLE; 754 if (mode & PARODD) 755 h_ubrlcr |= UART_ODD_PARITY; 756 else 757 h_ubrlcr |= UART_EVEN_PARITY; 758 759 if (mode & CSTOPB) 760 h_ubrlcr |= UART_STOP_BITS_2; 761 762 m_ubrlcr = (baudrate >> 8) & 0xf; 763 l_ubrlcr = baudrate & 0xff; 764 765 bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr); 766 bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr); 767 bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr); 768 } 769 #if 0 770 /* 771 * Set UART for console use. Do normal init, then enable interrupts. 772 */ 773 void 774 fcominitcons(iot, ioh) 775 bus_space_tag_t iot; 776 bus_space_handle_t ioh; 777 { 778 int s = splserial(); 779 780 fcominit(iot, ioh, comcnspeed, comcnmode); 781 782 delay(10000); 783 784 (void)splx(s); 785 } 786 #endif 787 788 int 789 fcomcngetc(dev) 790 dev_t dev; 791 { 792 int s = splserial(); 793 bus_space_tag_t iot = fcomconstag; 794 bus_space_handle_t ioh = fcomconsioh; 795 u_char stat, c; 796 797 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_RX_FULL) != 0) 798 ; 799 c = bus_space_read_4(iot, ioh, UART_DATA); 800 stat = bus_space_read_4(iot, ioh, UART_RX_STAT); 801 (void)splx(s); 802 #if DDB_KEYCODE > 0 803 /* 804 * Temporary hack so that I can force the kernel into 805 * the debugger via the serial port 806 */ 807 if (c == DDB_KEYCODE) Debugger(); 808 #endif 809 810 return (c); 811 } 812 813 /* 814 * Console kernel output character routine. 815 */ 816 void 817 fcomcnputc(dev, c) 818 dev_t dev; 819 int c; 820 { 821 int s = splserial(); 822 bus_space_tag_t iot = fcomconstag; 823 bus_space_handle_t ioh = fcomconsioh; 824 int timo; 825 826 /* wait for any pending transmission to finish */ 827 timo = 50000; 828 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 829 ; 830 bus_space_write_4(iot, ioh, UART_DATA, c); 831 832 /* wait for this transmission to complete */ 833 timo = 1500000; 834 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 835 ; 836 /* Clear interrupt status here */ 837 (void)splx(s); 838 } 839 840 void 841 fcomcnpollc(dev, on) 842 dev_t dev; 843 int on; 844 { 845 } 846
Indexes created Wed Oct 01 07:09:59 GMT 2025