footbridge_com.c revision 1.30
1 /* $NetBSD: footbridge_com.c,v 1.30 2009/03/14 15:36:02 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 Mark Brinicombe 5 * Copyright (c) 1997 Causality Limited 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Mark Brinicombe 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * COM driver, using the footbridge UART 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: footbridge_com.c,v 1.30 2009/03/14 15:36:02 dsl Exp $"); 40 41 #include "opt_ddb.h" 42 #include "opt_ddbparam.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/ioctl.h> 47 #include <sys/select.h> 48 #include <sys/tty.h> 49 #include <sys/proc.h> 50 #include <sys/conf.h> 51 #include <sys/syslog.h> 52 #include <sys/device.h> 53 #include <sys/malloc.h> 54 #include <sys/termios.h> 55 #include <sys/kauth.h> 56 #include <machine/bus.h> 57 #include <machine/intr.h> 58 #include <arm/footbridge/dc21285mem.h> 59 #include <arm/footbridge/dc21285reg.h> 60 #include <arm/footbridge/footbridgevar.h> 61 #include <arm/footbridge/footbridge.h> 62 63 #include <dev/cons.h> 64 65 #include "fcom.h" 66 67 extern u_int dc21285_fclk; 68 69 70 #ifdef DDB 71 /* 72 * Define the keycode recognised as a request to call the debugger 73 * A value of 0 disables the feature when DDB is built in 74 */ 75 #ifndef DDB_KEYCODE 76 #define DDB_KEYCODE 0 77 #endif /* DDB_KEYCODE */ 78 #endif /* DDB */ 79 80 struct fcom_softc { 81 struct device sc_dev; 82 bus_space_tag_t sc_iot; 83 bus_space_handle_t sc_ioh; 84 void *sc_ih; 85 struct callout sc_softintr_ch; 86 int sc_rx_irq; 87 int sc_tx_irq; 88 int sc_hwflags; 89 #define HW_FLAG_CONSOLE 0x01 90 int sc_swflags; 91 int sc_l_ubrlcr; 92 int sc_m_ubrlcr; 93 int sc_h_ubrlcr; 94 char *sc_rxbuffer[2]; 95 char *sc_rxbuf; 96 int sc_rxpos; 97 int sc_rxcur; 98 struct tty *sc_tty; 99 }; 100 101 #define RX_BUFFER_SIZE 0x100 102 103 static int fcom_probe(struct device *, struct cfdata *, void *); 104 static void fcom_attach(struct device *, struct device *, void *); 105 static void fcom_softintr(void *); 106 107 static int fcom_rxintr(void *); 108 /*static int fcom_txintr(void *);*/ 109 110 /*struct consdev;*/ 111 /*void fcomcnprobe(struct consdev *); 112 void fcomcninit(struct consdev *);*/ 113 int fcomcngetc(dev_t); 114 void fcomcnputc(dev_t, int); 115 void fcomcnpollc(dev_t, int); 116 117 CFATTACH_DECL(fcom, sizeof(struct fcom_softc), 118 fcom_probe, fcom_attach, NULL, NULL); 119 120 extern struct cfdriver fcom_cd; 121 122 dev_type_open(fcomopen); 123 dev_type_close(fcomclose); 124 dev_type_read(fcomread); 125 dev_type_write(fcomwrite); 126 dev_type_ioctl(fcomioctl); 127 dev_type_tty(fcomtty); 128 dev_type_poll(fcompoll); 129 130 const struct cdevsw fcom_cdevsw = { 131 fcomopen, fcomclose, fcomread, fcomwrite, fcomioctl, 132 nostop, fcomtty, fcompoll, nommap, ttykqfilter, D_TTY 133 }; 134 135 void fcominit(bus_space_tag_t, bus_space_handle_t, int, int); 136 void fcominitcons(bus_space_tag_t, bus_space_handle_t); 137 138 bus_space_tag_t fcomconstag; 139 bus_space_handle_t fcomconsioh; 140 extern int comcnmode; 141 extern int comcnspeed; 142 143 #define COMUNIT(x) (minor(x)) 144 #ifndef CONUNIT 145 #define CONUNIT 0 146 #endif 147 148 /* 149 * The console is set up at init time, well in advance of the reset of the 150 * system and thus we have a private bus space tag for the console. 151 * 152 * The tag is provided by fcom_io.c and fcom_io_asm.S 153 */ 154 extern struct bus_space fcomcons_bs_tag; 155 156 /* 157 * int fcom_probe(struct device *parent, struct cfdata *cf, void *aux) 158 * 159 * Make sure we are trying to attach a com device and then 160 * probe for one. 161 */ 162 163 static int 164 fcom_probe(struct device *parent, struct cfdata *cf, void *aux) 165 { 166 union footbridge_attach_args *fba = aux; 167 168 if (strcmp(fba->fba_name, "fcom") == 0) 169 return(1); 170 return(0); 171 } 172 173 /* 174 * void fcom_attach(struct device *parent, struct device *self, void *aux) 175 * 176 * attach the com device 177 */ 178 179 static void 180 fcom_attach(parent, self, aux) 181 struct device *parent, *self; 182 void *aux; 183 { 184 union footbridge_attach_args *fba = aux; 185 struct fcom_softc *sc = (struct fcom_softc *)self; 186 187 /* Set up the softc */ 188 sc->sc_iot = fba->fba_fca.fca_iot; 189 sc->sc_ioh = fba->fba_fca.fca_ioh; 190 callout_init(&sc->sc_softintr_ch, 0); 191 sc->sc_rx_irq = fba->fba_fca.fca_rx_irq; 192 sc->sc_tx_irq = fba->fba_fca.fca_tx_irq; 193 sc->sc_hwflags = 0; 194 sc->sc_swflags = 0; 195 196 /* If we have a console tag then make a note of it */ 197 if (fcomconstag) 198 sc->sc_hwflags |= HW_FLAG_CONSOLE; 199 200 if (sc->sc_hwflags & HW_FLAG_CONSOLE) { 201 int major; 202 203 /* locate the major number */ 204 major = cdevsw_lookup_major(&fcom_cdevsw); 205 206 cn_tab->cn_dev = makedev(major, device_unit(&sc->sc_dev)); 207 printf(": console"); 208 } 209 printf("\n"); 210 211 sc->sc_ih = footbridge_intr_claim(sc->sc_rx_irq, IPL_SERIAL, 212 "serial rx", fcom_rxintr, sc); 213 if (sc->sc_ih == NULL) 214 panic("%s: Cannot install rx interrupt handler", 215 sc->sc_dev.dv_xname); 216 } 217 218 static void fcomstart(struct tty *); 219 static int fcomparam(struct tty *, struct termios *); 220 221 int 222 fcomopen(dev_t dev, int flag, int mode, struct lwp *l) 223 { 224 struct fcom_softc *sc; 225 struct tty *tp; 226 227 sc = device_lookup_private(&fcom_cd, minor(dev)); 228 if (!sc) 229 return ENXIO; 230 if (!(tp = sc->sc_tty)) 231 sc->sc_tty = tp = ttymalloc(); 232 if (!sc->sc_rxbuffer[0]) { 233 sc->sc_rxbuffer[0] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK); 234 sc->sc_rxbuffer[1] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK); 235 sc->sc_rxpos = 0; 236 sc->sc_rxcur = 0; 237 sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur]; 238 if (!sc->sc_rxbuf) 239 panic("%s: Cannot allocate rx buffer memory", 240 sc->sc_dev.dv_xname); 241 } 242 tp->t_oproc = fcomstart; 243 tp->t_param = fcomparam; 244 tp->t_dev = dev; 245 246 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 247 return (EBUSY); 248 249 if (!(tp->t_state & TS_ISOPEN && tp->t_wopen == 0)) { 250 ttychars(tp); 251 tp->t_cflag = TTYDEF_CFLAG; 252 tp->t_iflag = TTYDEF_IFLAG; 253 tp->t_oflag = TTYDEF_OFLAG; 254 tp->t_lflag = TTYDEF_LFLAG; 255 256 /* 257 * Initialize the termios status to the defaults. Add in the 258 * sticky bits from TIOCSFLAGS. 259 */ 260 tp->t_ispeed = 0; 261 if (ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE)) 262 tp->t_ospeed = comcnspeed; 263 else 264 tp->t_ospeed = TTYDEF_SPEED; 265 266 fcomparam(tp, &tp->t_termios); 267 ttsetwater(tp); 268 } 269 tp->t_state |= TS_CARR_ON; 270 271 return (*tp->t_linesw->l_open)(dev, tp); 272 } 273 274 int 275 fcomclose(dev_t dev, int flag, int mode, struct lwp *l) 276 { 277 struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(dev)); 278 struct tty *tp = sc->sc_tty; 279 /* XXX This is for cons.c. */ 280 if (!ISSET(tp->t_state, TS_ISOPEN)) 281 return (0); 282 283 (*tp->t_linesw->l_close)(tp, flag); 284 ttyclose(tp); 285 #ifdef DIAGNOSTIC 286 if (sc->sc_rxbuffer[0] == NULL) 287 panic("fcomclose: rx buffers not allocated"); 288 #endif /* DIAGNOSTIC */ 289 free(sc->sc_rxbuffer[0], M_DEVBUF); 290 free(sc->sc_rxbuffer[1], M_DEVBUF); 291 sc->sc_rxbuffer[0] = NULL; 292 sc->sc_rxbuffer[1] = NULL; 293 294 return 0; 295 } 296 297 int 298 fcomread(dev_t dev, struct uio *uio, int flag) 299 { 300 struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(dev)); 301 struct tty *tp = sc->sc_tty; 302 303 return (*tp->t_linesw->l_read)(tp, uio, flag); 304 } 305 306 int 307 fcomwrite(dev_t dev, struct uio *uio, int flag) 308 { 309 struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(dev)); 310 struct tty *tp = sc->sc_tty; 311 312 return (*tp->t_linesw->l_write)(tp, uio, flag); 313 } 314 315 int 316 fcompoll(dev_t dev, int events, struct lwp *l) 317 { 318 struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(dev)); 319 struct tty *tp = sc->sc_tty; 320 321 return ((*tp->t_linesw->l_poll)(tp, events, l)); 322 } 323 324 int 325 fcomioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 326 { 327 struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(dev)); 328 struct tty *tp = sc->sc_tty; 329 int error; 330 331 if ((error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l)) != 332 EPASSTHROUGH) 333 return error; 334 if ((error = ttioctl(tp, cmd, data, flag, l)) != EPASSTHROUGH) 335 return error; 336 337 switch (cmd) { 338 case TIOCGFLAGS: 339 *(int *)data = sc->sc_swflags; 340 break; 341 342 case TIOCSFLAGS: 343 error = kauth_authorize_device_tty(l->l_cred, 344 KAUTH_DEVICE_TTY_PRIVSET, tp); 345 if (error) 346 return (error); 347 sc->sc_swflags = *(int *)data; 348 break; 349 } 350 351 return EPASSTHROUGH; 352 } 353 354 struct tty * 355 fcomtty(dev_t dev) 356 { 357 struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(dev)); 358 359 return sc->sc_tty; 360 } 361 362 static void 363 fcomstart(struct tty *tp) 364 { 365 struct clist *cl; 366 int s, len; 367 u_char buf[64]; 368 int loop; 369 struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(tp->t_dev)); 370 bus_space_tag_t iot = sc->sc_iot; 371 bus_space_handle_t ioh = sc->sc_ioh; 372 int timo; 373 374 s = spltty(); 375 if (tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) { 376 (void)splx(s); 377 return; 378 } 379 tp->t_state |= TS_BUSY; 380 (void)splx(s); 381 382 /* s = splserial();*/ 383 /* wait for any pending transmission to finish */ 384 timo = 100000; 385 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 386 ; 387 388 s = splserial(); 389 if (bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) { 390 tp->t_state |= TS_TIMEOUT; 391 callout_schedule(&tp->t_rstrt_ch, 1); 392 (void)splx(s); 393 return; 394 } 395 396 (void)splx(s); 397 398 cl = &tp->t_outq; 399 len = q_to_b(cl, buf, 64); 400 for (loop = 0; loop < len; ++loop) { 401 /* s = splserial();*/ 402 403 bus_space_write_4(iot, ioh, UART_DATA, buf[loop]); 404 405 /* wait for this transmission to complete */ 406 timo = 100000; 407 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 408 ; 409 /* (void)splx(s);*/ 410 } 411 s = spltty(); 412 tp->t_state &= ~TS_BUSY; 413 if (ttypull(tp)) { 414 tp->t_state |= TS_TIMEOUT; 415 callout_schedule(&tp->t_rstrt_ch, 1); 416 } 417 (void)splx(s); 418 } 419 420 static int 421 fcomparam(struct tty *tp, struct termios *t) 422 { 423 struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(tp->t_dev)); 424 bus_space_tag_t iot = sc->sc_iot; 425 bus_space_handle_t ioh = sc->sc_ioh; 426 int baudrate; 427 int h_ubrlcr; 428 int m_ubrlcr; 429 int l_ubrlcr; 430 int s; 431 432 /* check requested parameters */ 433 if (t->c_ospeed < 0) 434 return (EINVAL); 435 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 436 return (EINVAL); 437 438 switch (t->c_ospeed) { 439 case B1200: 440 case B2400: 441 case B4800: 442 case B9600: 443 case B19200: 444 case B38400: 445 baudrate = UART_BRD(dc21285_fclk, t->c_ospeed); 446 break; 447 default: 448 baudrate = UART_BRD(dc21285_fclk, 9600); 449 break; 450 } 451 452 l_ubrlcr = baudrate & 0xff; 453 m_ubrlcr = (baudrate >> 8) & 0xf; 454 h_ubrlcr = 0; 455 456 switch (ISSET(t->c_cflag, CSIZE)) { 457 case CS5: 458 h_ubrlcr |= UART_DATA_BITS_5; 459 break; 460 case CS6: 461 h_ubrlcr |= UART_DATA_BITS_6; 462 break; 463 case CS7: 464 h_ubrlcr |= UART_DATA_BITS_7; 465 break; 466 case CS8: 467 h_ubrlcr |= UART_DATA_BITS_8; 468 break; 469 } 470 471 if (ISSET(t->c_cflag, PARENB)) { 472 h_ubrlcr |= UART_PARITY_ENABLE; 473 if (ISSET(t->c_cflag, PARODD)) 474 h_ubrlcr |= UART_ODD_PARITY; 475 else 476 h_ubrlcr |= UART_EVEN_PARITY; 477 } 478 479 if (ISSET(t->c_cflag, CSTOPB)) 480 h_ubrlcr |= UART_STOP_BITS_2; 481 482 bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr); 483 bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr); 484 bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr); 485 486 s = splserial(); 487 488 sc->sc_l_ubrlcr = l_ubrlcr; 489 sc->sc_m_ubrlcr = m_ubrlcr; 490 sc->sc_h_ubrlcr = h_ubrlcr; 491 492 /* 493 * For the console, always force CLOCAL and !HUPCL, so that the port 494 * is always active. 495 */ 496 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 497 ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE)) { 498 SET(t->c_cflag, CLOCAL); 499 CLR(t->c_cflag, HUPCL); 500 } 501 502 /* and copy to tty */ 503 tp->t_ispeed = 0; 504 tp->t_ospeed = t->c_ospeed; 505 tp->t_cflag = t->c_cflag; 506 507 bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr); 508 bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr); 509 bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr); 510 511 (void)splx(s); 512 513 return (0); 514 } 515 516 static int softint_scheduled = 0; 517 518 static void 519 fcom_softintr(void *arg) 520 { 521 struct fcom_softc *sc = arg; 522 struct tty *tp = sc->sc_tty; 523 int s; 524 int loop; 525 int len; 526 char *ptr; 527 528 s = spltty(); 529 ptr = sc->sc_rxbuf; 530 len = sc->sc_rxpos; 531 sc->sc_rxcur ^= 1; 532 sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur]; 533 sc->sc_rxpos = 0; 534 (void)splx(s); 535 536 for (loop = 0; loop < len; ++loop) 537 (*tp->t_linesw->l_rint)(ptr[loop], tp); 538 softint_scheduled = 0; 539 } 540 541 #if 0 542 static int 543 fcom_txintr(void *arg) 544 { 545 /* struct fcom_softc *sc = arg;*/ 546 547 printf("fcom_txintr()\n"); 548 return(0); 549 } 550 #endif 551 552 static int 553 fcom_rxintr(void *arg) 554 { 555 struct fcom_softc *sc = arg; 556 bus_space_tag_t iot = sc->sc_iot; 557 bus_space_handle_t ioh = sc->sc_ioh; 558 struct tty *tp = sc->sc_tty; 559 int status; 560 int byte; 561 562 do { 563 status = bus_space_read_4(iot, ioh, UART_FLAGS); 564 if ((status & UART_RX_FULL)) 565 break; 566 byte = bus_space_read_4(iot, ioh, UART_DATA); 567 status = bus_space_read_4(iot, ioh, UART_RX_STAT); 568 #if defined(DDB) && DDB_KEYCODE > 0 569 /* 570 * Temporary hack so that I can force the kernel into 571 * the debugger via the serial port 572 */ 573 if (byte == DDB_KEYCODE) Debugger(); 574 #endif 575 if (tp && (tp->t_state & TS_ISOPEN)) 576 if (sc->sc_rxpos < RX_BUFFER_SIZE) { 577 sc->sc_rxbuf[sc->sc_rxpos++] = byte; 578 if (!softint_scheduled) { 579 softint_scheduled = 1; 580 callout_reset(&sc->sc_softintr_ch, 581 1, fcom_softintr, sc); 582 } 583 } 584 } while (1); 585 return(0); 586 } 587 588 #if 0 589 void 590 fcom_iflush(struct fcom_softc *sc) 591 { 592 bus_space_tag_t iot = sc->sc_iot; 593 bus_space_handle_t ioh = sc->sc_ioh; 594 595 /* flush any pending I/O */ 596 while (!ISSET(bus_space_read_4(iot, ioh, UART_FLAGS), UART_RX_FULL)) 597 (void) bus_space_read_4(iot, ioh, UART_DATA); 598 } 599 #endif 600 601 /* 602 * Following are all routines needed for COM to act as console 603 */ 604 605 #if 0 606 void 607 fcomcnprobe(struct consdev *cp) 608 { 609 int major; 610 611 /* Serial console is always present so no probe */ 612 613 /* locate the major number */ 614 major = cdevsw_lookup_major(&fcom_cdevsw); 615 616 /* initialize required fields */ 617 cp->cn_dev = makedev(major, CONUNIT); 618 cp->cn_pri = CN_REMOTE; /* Force a serial port console */ 619 } 620 621 void 622 fcomcninit(struct consdev *cp) 623 { 624 fcomconstag = &fcomcons_bs_tag; 625 626 if (bus_space_map(fcomconstag, DC21285_ARMCSR_BASE, DC21285_ARMCSR_SIZE, 0, &fcomconsioh)) 627 panic("fcomcninit: mapping failed"); 628 629 fcominitcons(fcomconstag, fcomconsioh); 630 } 631 #endif 632 633 int 634 fcomcnattach(u_int iobase, int rate, tcflag_t cflag) 635 { 636 static struct consdev fcomcons = { 637 NULL, NULL, fcomcngetc, fcomcnputc, fcomcnpollc, NULL, 638 NULL, NULL, NODEV, CN_NORMAL 639 }; 640 641 fcomconstag = &fcomcons_bs_tag; 642 643 if (bus_space_map(fcomconstag, iobase, DC21285_ARMCSR_SIZE, 644 0, &fcomconsioh)) 645 panic("fcomcninit: mapping failed"); 646 647 fcominit(fcomconstag, fcomconsioh, rate, cflag); 648 649 cn_tab = &fcomcons; 650 651 /* comcnspeed = rate; 652 comcnmode = cflag;*/ 653 return (0); 654 } 655 656 int 657 fcomcndetach(void) 658 { 659 bus_space_unmap(fcomconstag, fcomconsioh, DC21285_ARMCSR_SIZE); 660 661 cn_tab = NULL; 662 return (0); 663 } 664 665 /* 666 * Initialize UART to known state. 667 */ 668 void 669 fcominit(bus_space_tag_t iot, bus_space_handle_t ioh, int rate, int mode) 670 { 671 int baudrate; 672 int h_ubrlcr; 673 int m_ubrlcr; 674 int l_ubrlcr; 675 676 switch (rate) { 677 case B1200: 678 case B2400: 679 case B4800: 680 case B9600: 681 case B19200: 682 case B38400: 683 baudrate = UART_BRD(dc21285_fclk, rate); 684 break; 685 default: 686 baudrate = UART_BRD(dc21285_fclk, 9600); 687 break; 688 } 689 690 h_ubrlcr = 0; 691 switch (mode & CSIZE) { 692 case CS5: 693 h_ubrlcr |= UART_DATA_BITS_5; 694 break; 695 case CS6: 696 h_ubrlcr |= UART_DATA_BITS_6; 697 break; 698 case CS7: 699 h_ubrlcr |= UART_DATA_BITS_7; 700 break; 701 case CS8: 702 h_ubrlcr |= UART_DATA_BITS_8; 703 break; 704 } 705 706 if (mode & PARENB) 707 h_ubrlcr |= UART_PARITY_ENABLE; 708 if (mode & PARODD) 709 h_ubrlcr |= UART_ODD_PARITY; 710 else 711 h_ubrlcr |= UART_EVEN_PARITY; 712 713 if (mode & CSTOPB) 714 h_ubrlcr |= UART_STOP_BITS_2; 715 716 m_ubrlcr = (baudrate >> 8) & 0xf; 717 l_ubrlcr = baudrate & 0xff; 718 719 bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr); 720 bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr); 721 bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr); 722 } 723 #if 0 724 /* 725 * Set UART for console use. Do normal init, then enable interrupts. 726 */ 727 void 728 fcominitcons(bus_space_tag_t iot, bus_space_handle_t ioh) 729 { 730 int s = splserial(); 731 732 fcominit(iot, ioh, comcnspeed, comcnmode); 733 734 delay(10000); 735 736 (void)splx(s); 737 } 738 #endif 739 740 int 741 fcomcngetc(dev_t dev) 742 { 743 int s = splserial(); 744 bus_space_tag_t iot = fcomconstag; 745 bus_space_handle_t ioh = fcomconsioh; 746 u_char stat, c; 747 748 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_RX_FULL) != 0) 749 ; 750 c = bus_space_read_4(iot, ioh, UART_DATA); 751 stat = bus_space_read_4(iot, ioh, UART_RX_STAT); 752 (void)splx(s); 753 #if defined(DDB) && DDB_KEYCODE > 0 754 /* 755 * Temporary hack so that I can force the kernel into 756 * the debugger via the serial port 757 */ 758 if (c == DDB_KEYCODE) Debugger(); 759 #endif 760 761 return (c); 762 } 763 764 /* 765 * Console kernel output character routine. 766 */ 767 void 768 fcomcnputc(dev_t dev, int c) 769 { 770 int s = splserial(); 771 bus_space_tag_t iot = fcomconstag; 772 bus_space_handle_t ioh = fcomconsioh; 773 int timo; 774 775 /* wait for any pending transmission to finish */ 776 timo = 50000; 777 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 778 ; 779 bus_space_write_4(iot, ioh, UART_DATA, c); 780 781 /* wait for this transmission to complete */ 782 timo = 1500000; 783 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 784 ; 785 /* Clear interrupt status here */ 786 (void)splx(s); 787 } 788 789 void 790 fcomcnpollc(dev_t dev, int on) 791 { 792 } 793
Indexes created Thu Oct 02 14:10:14 GMT 2025