footbridge_com.c revision 1.35
1 /* $NetBSD: footbridge_com.c,v 1.35 2012/10/10 21:53:09 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 Mark Brinicombe 5 * Copyright (c) 1997 Causality Limited 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Mark Brinicombe 18 * for the NetBSD Project. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * COM driver, using the footbridge UART 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: footbridge_com.c,v 1.35 2012/10/10 21:53:09 skrll Exp $"); 40 41 #include "opt_ddb.h" 42 #include "opt_ddbparam.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/ioctl.h> 47 #include <sys/select.h> 48 #include <sys/tty.h> 49 #include <sys/proc.h> 50 #include <sys/conf.h> 51 #include <sys/syslog.h> 52 #include <sys/device.h> 53 #include <sys/malloc.h> 54 #include <sys/termios.h> 55 #include <sys/kauth.h> 56 #include <sys/bus.h> 57 #include <machine/intr.h> 58 #include <arm/footbridge/dc21285mem.h> 59 #include <arm/footbridge/dc21285reg.h> 60 #include <arm/footbridge/footbridgevar.h> 61 #include <arm/footbridge/footbridge.h> 62 63 #include <dev/cons.h> 64 65 #include "fcom.h" 66 67 extern u_int dc21285_fclk; 68 69 70 #ifdef DDB 71 /* 72 * Define the keycode recognised as a request to call the debugger 73 * A value of 0 disables the feature when DDB is built in 74 */ 75 #ifndef DDB_KEYCODE 76 #define DDB_KEYCODE 0 77 #endif /* DDB_KEYCODE */ 78 #endif /* DDB */ 79 80 struct fcom_softc { 81 device_t sc_dev; 82 bus_space_tag_t sc_iot; 83 bus_space_handle_t sc_ioh; 84 void *sc_ih; 85 struct callout sc_softintr_ch; 86 int sc_rx_irq; 87 int sc_tx_irq; 88 int sc_hwflags; 89 #define HW_FLAG_CONSOLE 0x01 90 int sc_swflags; 91 int sc_l_ubrlcr; 92 int sc_m_ubrlcr; 93 int sc_h_ubrlcr; 94 char *sc_rxbuffer[2]; 95 char *sc_rxbuf; 96 int sc_rxpos; 97 int sc_rxcur; 98 struct tty *sc_tty; 99 }; 100 101 #define RX_BUFFER_SIZE 0x100 102 103 static int fcom_probe(device_t, cfdata_t, void *); 104 static void fcom_attach(device_t, device_t, void *); 105 static void fcom_softintr(void *); 106 107 static int fcom_rxintr(void *); 108 /*static int fcom_txintr(void *);*/ 109 110 /*struct consdev;*/ 111 /*void fcomcnprobe(struct consdev *); 112 void fcomcninit(struct consdev *);*/ 113 int fcomcngetc(dev_t); 114 void fcomcnputc(dev_t, int); 115 void fcomcnpollc(dev_t, int); 116 117 CFATTACH_DECL_NEW(fcom, sizeof(struct fcom_softc), 118 fcom_probe, fcom_attach, NULL, NULL); 119 120 extern struct cfdriver fcom_cd; 121 122 dev_type_open(fcomopen); 123 dev_type_close(fcomclose); 124 dev_type_read(fcomread); 125 dev_type_write(fcomwrite); 126 dev_type_ioctl(fcomioctl); 127 dev_type_tty(fcomtty); 128 dev_type_poll(fcompoll); 129 130 const struct cdevsw fcom_cdevsw = { 131 fcomopen, fcomclose, fcomread, fcomwrite, fcomioctl, 132 nostop, fcomtty, fcompoll, nommap, ttykqfilter, D_TTY 133 }; 134 135 void fcominit(bus_space_tag_t, bus_space_handle_t, int, int); 136 void fcominitcons(bus_space_tag_t, bus_space_handle_t); 137 138 bus_space_tag_t fcomconstag; 139 bus_space_handle_t fcomconsioh; 140 extern int comcnmode; 141 extern int comcnspeed; 142 143 #define COMUNIT(x) (minor(x)) 144 #ifndef CONUNIT 145 #define CONUNIT 0 146 #endif 147 148 /* 149 * The console is set up at init time, well in advance of the reset of the 150 * system and thus we have a private bus space tag for the console. 151 * 152 * The tag is provided by fcom_io.c and fcom_io_asm.S 153 */ 154 extern struct bus_space fcomcons_bs_tag; 155 156 /* 157 * int fcom_probe(device_t parent, cfdata_t cf, void *aux) 158 * 159 * Make sure we are trying to attach a com device and then 160 * probe for one. 161 */ 162 163 static int 164 fcom_probe(device_t parent, cfdata_t cf, void *aux) 165 { 166 union footbridge_attach_args *fba = aux; 167 168 if (strcmp(fba->fba_name, "fcom") == 0) 169 return(1); 170 return(0); 171 } 172 173 /* 174 * void fcom_attach(device_t parent, device_t self, void *aux) 175 * 176 * attach the com device 177 */ 178 179 static void 180 fcom_attach(device_t parent, device_t self, void *aux) 181 { 182 union footbridge_attach_args *fba = aux; 183 struct fcom_softc *sc = device_private(self); 184 185 /* Set up the softc */ 186 sc->sc_dev = self; 187 sc->sc_iot = fba->fba_fca.fca_iot; 188 sc->sc_ioh = fba->fba_fca.fca_ioh; 189 callout_init(&sc->sc_softintr_ch, 0); 190 sc->sc_rx_irq = fba->fba_fca.fca_rx_irq; 191 sc->sc_tx_irq = fba->fba_fca.fca_tx_irq; 192 sc->sc_hwflags = 0; 193 sc->sc_swflags = 0; 194 195 /* If we have a console tag then make a note of it */ 196 if (fcomconstag) 197 sc->sc_hwflags |= HW_FLAG_CONSOLE; 198 199 if (sc->sc_hwflags & HW_FLAG_CONSOLE) { 200 int major; 201 202 /* locate the major number */ 203 major = cdevsw_lookup_major(&fcom_cdevsw); 204 205 cn_tab->cn_dev = makedev(major, device_unit(sc->sc_dev)); 206 aprint_normal(": console"); 207 } 208 aprint_normal("\n"); 209 210 sc->sc_ih = footbridge_intr_claim(sc->sc_rx_irq, IPL_SERIAL, 211 "serial rx", fcom_rxintr, sc); 212 if (sc->sc_ih == NULL) 213 panic("%s: Cannot install rx interrupt handler", 214 device_xname(sc->sc_dev)); 215 } 216 217 static void fcomstart(struct tty *); 218 static int fcomparam(struct tty *, struct termios *); 219 220 int 221 fcomopen(dev_t dev, int flag, int mode, struct lwp *l) 222 { 223 struct fcom_softc *sc; 224 struct tty *tp; 225 226 sc = device_lookup_private(&fcom_cd, minor(dev)); 227 if (!sc) 228 return ENXIO; 229 if (!(tp = sc->sc_tty)) 230 sc->sc_tty = tp = tty_alloc(); 231 if (!sc->sc_rxbuffer[0]) { 232 sc->sc_rxbuffer[0] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK); 233 sc->sc_rxbuffer[1] = malloc(RX_BUFFER_SIZE, M_DEVBUF, M_WAITOK); 234 sc->sc_rxpos = 0; 235 sc->sc_rxcur = 0; 236 sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur]; 237 if (!sc->sc_rxbuf) 238 panic("%s: Cannot allocate rx buffer memory", 239 device_xname(sc->sc_dev)); 240 } 241 tp->t_oproc = fcomstart; 242 tp->t_param = fcomparam; 243 tp->t_dev = dev; 244 245 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 246 return (EBUSY); 247 248 if (!(tp->t_state & TS_ISOPEN && tp->t_wopen == 0)) { 249 ttychars(tp); 250 tp->t_cflag = TTYDEF_CFLAG; 251 tp->t_iflag = TTYDEF_IFLAG; 252 tp->t_oflag = TTYDEF_OFLAG; 253 tp->t_lflag = TTYDEF_LFLAG; 254 255 /* 256 * Initialize the termios status to the defaults. Add in the 257 * sticky bits from TIOCSFLAGS. 258 */ 259 tp->t_ispeed = 0; 260 if (ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE)) 261 tp->t_ospeed = comcnspeed; 262 else 263 tp->t_ospeed = TTYDEF_SPEED; 264 265 fcomparam(tp, &tp->t_termios); 266 ttsetwater(tp); 267 } 268 tp->t_state |= TS_CARR_ON; 269 270 return (*tp->t_linesw->l_open)(dev, tp); 271 } 272 273 int 274 fcomclose(dev_t dev, int flag, int mode, struct lwp *l) 275 { 276 struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(dev)); 277 struct tty *tp = sc->sc_tty; 278 /* XXX This is for cons.c. */ 279 if (!ISSET(tp->t_state, TS_ISOPEN)) 280 return (0); 281 282 (*tp->t_linesw->l_close)(tp, flag); 283 ttyclose(tp); 284 #ifdef DIAGNOSTIC 285 if (sc->sc_rxbuffer[0] == NULL) 286 panic("fcomclose: rx buffers not allocated"); 287 #endif /* DIAGNOSTIC */ 288 free(sc->sc_rxbuffer[0], M_DEVBUF); 289 free(sc->sc_rxbuffer[1], M_DEVBUF); 290 sc->sc_rxbuffer[0] = NULL; 291 sc->sc_rxbuffer[1] = NULL; 292 293 return 0; 294 } 295 296 int 297 fcomread(dev_t dev, struct uio *uio, int flag) 298 { 299 struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(dev)); 300 struct tty *tp = sc->sc_tty; 301 302 return (*tp->t_linesw->l_read)(tp, uio, flag); 303 } 304 305 int 306 fcomwrite(dev_t dev, struct uio *uio, int flag) 307 { 308 struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(dev)); 309 struct tty *tp = sc->sc_tty; 310 311 return (*tp->t_linesw->l_write)(tp, uio, flag); 312 } 313 314 int 315 fcompoll(dev_t dev, int events, struct lwp *l) 316 { 317 struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(dev)); 318 struct tty *tp = sc->sc_tty; 319 320 return ((*tp->t_linesw->l_poll)(tp, events, l)); 321 } 322 323 int 324 fcomioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 325 { 326 struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(dev)); 327 struct tty *tp = sc->sc_tty; 328 int error; 329 330 if ((error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l)) != 331 EPASSTHROUGH) 332 return error; 333 if ((error = ttioctl(tp, cmd, data, flag, l)) != EPASSTHROUGH) 334 return error; 335 336 switch (cmd) { 337 case TIOCGFLAGS: 338 *(int *)data = sc->sc_swflags; 339 break; 340 341 case TIOCSFLAGS: 342 error = kauth_authorize_device_tty(l->l_cred, 343 KAUTH_DEVICE_TTY_PRIVSET, tp); 344 if (error) 345 return (error); 346 sc->sc_swflags = *(int *)data; 347 break; 348 } 349 350 return EPASSTHROUGH; 351 } 352 353 struct tty * 354 fcomtty(dev_t dev) 355 { 356 struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(dev)); 357 358 return sc->sc_tty; 359 } 360 361 static void 362 fcomstart(struct tty *tp) 363 { 364 struct clist *cl; 365 int s, len; 366 u_char buf[64]; 367 int loop; 368 struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(tp->t_dev)); 369 bus_space_tag_t iot = sc->sc_iot; 370 bus_space_handle_t ioh = sc->sc_ioh; 371 int timo; 372 373 s = spltty(); 374 if (tp->t_state & (TS_TIMEOUT | TS_BUSY | TS_TTSTOP)) { 375 (void)splx(s); 376 return; 377 } 378 tp->t_state |= TS_BUSY; 379 (void)splx(s); 380 381 /* s = splserial();*/ 382 /* wait for any pending transmission to finish */ 383 timo = 100000; 384 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 385 ; 386 387 s = splserial(); 388 if (bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) { 389 tp->t_state |= TS_TIMEOUT; 390 callout_schedule(&tp->t_rstrt_ch, 1); 391 (void)splx(s); 392 return; 393 } 394 395 (void)splx(s); 396 397 cl = &tp->t_outq; 398 len = q_to_b(cl, buf, 64); 399 for (loop = 0; loop < len; ++loop) { 400 /* s = splserial();*/ 401 402 bus_space_write_4(iot, ioh, UART_DATA, buf[loop]); 403 404 /* wait for this transmission to complete */ 405 timo = 100000; 406 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 407 ; 408 /* (void)splx(s);*/ 409 } 410 s = spltty(); 411 tp->t_state &= ~TS_BUSY; 412 if (ttypull(tp)) { 413 tp->t_state |= TS_TIMEOUT; 414 callout_schedule(&tp->t_rstrt_ch, 1); 415 } 416 (void)splx(s); 417 } 418 419 static int 420 fcomparam(struct tty *tp, struct termios *t) 421 { 422 struct fcom_softc *sc = device_lookup_private(&fcom_cd, minor(tp->t_dev)); 423 bus_space_tag_t iot = sc->sc_iot; 424 bus_space_handle_t ioh = sc->sc_ioh; 425 int baudrate; 426 int h_ubrlcr; 427 int m_ubrlcr; 428 int l_ubrlcr; 429 int s; 430 431 /* check requested parameters */ 432 if (t->c_ospeed < 0) 433 return (EINVAL); 434 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 435 return (EINVAL); 436 437 switch (t->c_ospeed) { 438 case B1200: 439 case B2400: 440 case B4800: 441 case B9600: 442 case B19200: 443 case B38400: 444 baudrate = UART_BRD(dc21285_fclk, t->c_ospeed); 445 break; 446 default: 447 baudrate = UART_BRD(dc21285_fclk, 9600); 448 break; 449 } 450 451 l_ubrlcr = baudrate & 0xff; 452 m_ubrlcr = (baudrate >> 8) & 0xf; 453 h_ubrlcr = 0; 454 455 switch (ISSET(t->c_cflag, CSIZE)) { 456 case CS5: 457 h_ubrlcr |= UART_DATA_BITS_5; 458 break; 459 case CS6: 460 h_ubrlcr |= UART_DATA_BITS_6; 461 break; 462 case CS7: 463 h_ubrlcr |= UART_DATA_BITS_7; 464 break; 465 case CS8: 466 h_ubrlcr |= UART_DATA_BITS_8; 467 break; 468 } 469 470 if (ISSET(t->c_cflag, PARENB)) { 471 h_ubrlcr |= UART_PARITY_ENABLE; 472 if (ISSET(t->c_cflag, PARODD)) 473 h_ubrlcr |= UART_ODD_PARITY; 474 else 475 h_ubrlcr |= UART_EVEN_PARITY; 476 } 477 478 if (ISSET(t->c_cflag, CSTOPB)) 479 h_ubrlcr |= UART_STOP_BITS_2; 480 481 bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr); 482 bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr); 483 bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr); 484 485 s = splserial(); 486 487 sc->sc_l_ubrlcr = l_ubrlcr; 488 sc->sc_m_ubrlcr = m_ubrlcr; 489 sc->sc_h_ubrlcr = h_ubrlcr; 490 491 /* 492 * For the console, always force CLOCAL and !HUPCL, so that the port 493 * is always active. 494 */ 495 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 496 ISSET(sc->sc_hwflags, HW_FLAG_CONSOLE)) { 497 SET(t->c_cflag, CLOCAL); 498 CLR(t->c_cflag, HUPCL); 499 } 500 501 /* and copy to tty */ 502 tp->t_ispeed = 0; 503 tp->t_ospeed = t->c_ospeed; 504 tp->t_cflag = t->c_cflag; 505 506 bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr); 507 bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr); 508 bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr); 509 510 (void)splx(s); 511 512 return (0); 513 } 514 515 static int softint_scheduled = 0; 516 517 static void 518 fcom_softintr(void *arg) 519 { 520 struct fcom_softc *sc = arg; 521 struct tty *tp = sc->sc_tty; 522 int s; 523 int loop; 524 int len; 525 char *ptr; 526 527 s = spltty(); 528 ptr = sc->sc_rxbuf; 529 len = sc->sc_rxpos; 530 sc->sc_rxcur ^= 1; 531 sc->sc_rxbuf = sc->sc_rxbuffer[sc->sc_rxcur]; 532 sc->sc_rxpos = 0; 533 (void)splx(s); 534 535 for (loop = 0; loop < len; ++loop) 536 (*tp->t_linesw->l_rint)(ptr[loop], tp); 537 softint_scheduled = 0; 538 } 539 540 #if 0 541 static int 542 fcom_txintr(void *arg) 543 { 544 /* struct fcom_softc *sc = arg;*/ 545 546 printf("fcom_txintr()\n"); 547 return(0); 548 } 549 #endif 550 551 static int 552 fcom_rxintr(void *arg) 553 { 554 struct fcom_softc *sc = arg; 555 bus_space_tag_t iot = sc->sc_iot; 556 bus_space_handle_t ioh = sc->sc_ioh; 557 struct tty *tp = sc->sc_tty; 558 int status; 559 int byte; 560 561 do { 562 status = bus_space_read_4(iot, ioh, UART_FLAGS); 563 if ((status & UART_RX_FULL)) 564 break; 565 byte = bus_space_read_4(iot, ioh, UART_DATA); 566 status = bus_space_read_4(iot, ioh, UART_RX_STAT); 567 #if defined(DDB) && DDB_KEYCODE > 0 568 /* 569 * Temporary hack so that I can force the kernel into 570 * the debugger via the serial port 571 */ 572 if (byte == DDB_KEYCODE) Debugger(); 573 #endif 574 if (tp && (tp->t_state & TS_ISOPEN)) 575 if (sc->sc_rxpos < RX_BUFFER_SIZE) { 576 sc->sc_rxbuf[sc->sc_rxpos++] = byte; 577 if (!softint_scheduled) { 578 softint_scheduled = 1; 579 callout_reset(&sc->sc_softintr_ch, 580 1, fcom_softintr, sc); 581 } 582 } 583 } while (1); 584 return(0); 585 } 586 587 #if 0 588 void 589 fcom_iflush(struct fcom_softc *sc) 590 { 591 bus_space_tag_t iot = sc->sc_iot; 592 bus_space_handle_t ioh = sc->sc_ioh; 593 594 /* flush any pending I/O */ 595 while (!ISSET(bus_space_read_4(iot, ioh, UART_FLAGS), UART_RX_FULL)) 596 (void) bus_space_read_4(iot, ioh, UART_DATA); 597 } 598 #endif 599 600 /* 601 * Following are all routines needed for COM to act as console 602 */ 603 604 #if 0 605 void 606 fcomcnprobe(struct consdev *cp) 607 { 608 int major; 609 610 /* Serial console is always present so no probe */ 611 612 /* locate the major number */ 613 major = cdevsw_lookup_major(&fcom_cdevsw); 614 615 /* initialize required fields */ 616 cp->cn_dev = makedev(major, CONUNIT); 617 cp->cn_pri = CN_REMOTE; /* Force a serial port console */ 618 } 619 620 void 621 fcomcninit(struct consdev *cp) 622 { 623 fcomconstag = &fcomcons_bs_tag; 624 625 if (bus_space_map(fcomconstag, DC21285_ARMCSR_BASE, DC21285_ARMCSR_SIZE, 0, &fcomconsioh)) 626 panic("fcomcninit: mapping failed"); 627 628 fcominitcons(fcomconstag, fcomconsioh); 629 } 630 #endif 631 632 int 633 fcomcnattach(u_int iobase, int rate, tcflag_t cflag) 634 { 635 static struct consdev fcomcons = { 636 NULL, NULL, fcomcngetc, fcomcnputc, fcomcnpollc, NULL, 637 NULL, NULL, NODEV, CN_NORMAL 638 }; 639 640 fcomconstag = &fcomcons_bs_tag; 641 642 if (bus_space_map(fcomconstag, iobase, DC21285_ARMCSR_SIZE, 643 0, &fcomconsioh)) 644 panic("fcomcninit: mapping failed"); 645 646 fcominit(fcomconstag, fcomconsioh, rate, cflag); 647 648 cn_tab = &fcomcons; 649 650 /* comcnspeed = rate; 651 comcnmode = cflag;*/ 652 return (0); 653 } 654 655 int 656 fcomcndetach(void) 657 { 658 bus_space_unmap(fcomconstag, fcomconsioh, DC21285_ARMCSR_SIZE); 659 660 cn_tab = NULL; 661 return (0); 662 } 663 664 /* 665 * Initialize UART to known state. 666 */ 667 void 668 fcominit(bus_space_tag_t iot, bus_space_handle_t ioh, int rate, int mode) 669 { 670 int baudrate; 671 int h_ubrlcr; 672 int m_ubrlcr; 673 int l_ubrlcr; 674 675 switch (rate) { 676 case B1200: 677 case B2400: 678 case B4800: 679 case B9600: 680 case B19200: 681 case B38400: 682 baudrate = UART_BRD(dc21285_fclk, rate); 683 break; 684 default: 685 baudrate = UART_BRD(dc21285_fclk, 9600); 686 break; 687 } 688 689 h_ubrlcr = 0; 690 switch (mode & CSIZE) { 691 case CS5: 692 h_ubrlcr |= UART_DATA_BITS_5; 693 break; 694 case CS6: 695 h_ubrlcr |= UART_DATA_BITS_6; 696 break; 697 case CS7: 698 h_ubrlcr |= UART_DATA_BITS_7; 699 break; 700 case CS8: 701 h_ubrlcr |= UART_DATA_BITS_8; 702 break; 703 } 704 705 if (mode & PARENB) 706 h_ubrlcr |= UART_PARITY_ENABLE; 707 if (mode & PARODD) 708 h_ubrlcr |= UART_ODD_PARITY; 709 else 710 h_ubrlcr |= UART_EVEN_PARITY; 711 712 if (mode & CSTOPB) 713 h_ubrlcr |= UART_STOP_BITS_2; 714 715 m_ubrlcr = (baudrate >> 8) & 0xf; 716 l_ubrlcr = baudrate & 0xff; 717 718 bus_space_write_4(iot, ioh, UART_L_UBRLCR, l_ubrlcr); 719 bus_space_write_4(iot, ioh, UART_M_UBRLCR, m_ubrlcr); 720 bus_space_write_4(iot, ioh, UART_H_UBRLCR, h_ubrlcr); 721 } 722 #if 0 723 /* 724 * Set UART for console use. Do normal init, then enable interrupts. 725 */ 726 void 727 fcominitcons(bus_space_tag_t iot, bus_space_handle_t ioh) 728 { 729 int s = splserial(); 730 731 fcominit(iot, ioh, comcnspeed, comcnmode); 732 733 delay(10000); 734 735 (void)splx(s); 736 } 737 #endif 738 739 int 740 fcomcngetc(dev_t dev) 741 { 742 int s = splserial(); 743 bus_space_tag_t iot = fcomconstag; 744 bus_space_handle_t ioh = fcomconsioh; 745 u_char stat, c; 746 747 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_RX_FULL) != 0) 748 ; 749 c = bus_space_read_4(iot, ioh, UART_DATA); 750 stat = bus_space_read_4(iot, ioh, UART_RX_STAT); 751 (void)splx(s); 752 #if defined(DDB) && DDB_KEYCODE > 0 753 /* 754 * Temporary hack so that I can force the kernel into 755 * the debugger via the serial port 756 */ 757 if (c == DDB_KEYCODE) Debugger(); 758 #endif 759 760 return (c); 761 } 762 763 /* 764 * Console kernel output character routine. 765 */ 766 void 767 fcomcnputc(dev_t dev, int c) 768 { 769 int s = splserial(); 770 bus_space_tag_t iot = fcomconstag; 771 bus_space_handle_t ioh = fcomconsioh; 772 int timo; 773 774 /* wait for any pending transmission to finish */ 775 timo = 50000; 776 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 777 ; 778 bus_space_write_4(iot, ioh, UART_DATA, c); 779 780 /* wait for this transmission to complete */ 781 timo = 1500000; 782 while ((bus_space_read_4(iot, ioh, UART_FLAGS) & UART_TX_BUSY) && --timo) 783 ; 784 /* Clear interrupt status here */ 785 (void)splx(s); 786 } 787 788 void 789 fcomcnpollc(dev_t dev, int on) 790 { 791 } 792
Indexes created Thu Oct 02 01:09:59 GMT 2025