footbridge_pci.c revision 1.1
1 /* $NetBSD: footbridge_pci.c,v 1.1 2001/06/09 10:29:13 chris Exp $ */ 2 3 /* 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997,1998 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include "opt_ebsa285.h" 38 #include "opt_netwinder.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/conf.h> 43 #include <sys/malloc.h> 44 #include <sys/device.h> 45 46 #define _ARM32_BUS_DMA_PRIVATE 47 #include <machine/bus.h> 48 #include <machine/irqhandler.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 #include <arm/footbridge/dc21285reg.h> 54 #include <arm/footbridge/dc21285mem.h> 55 56 #include "isa.h" 57 #if NISA > 0 58 #include <dev/isa/isavar.h> 59 #endif 60 61 #ifdef NETWINDER 62 void netwinder_pci_attach_hook __P((struct device *, 63 struct device *, struct pcibus_attach_args *)); 64 #endif 65 void footbridge_pci_attach_hook __P((struct device *, 66 struct device *, struct pcibus_attach_args *)); 67 int footbridge_pci_bus_maxdevs __P((void *, int)); 68 pcitag_t footbridge_pci_make_tag __P((void *, int, int, int)); 69 void footbridge_pci_decompose_tag __P((void *, pcitag_t, int *, 70 int *, int *)); 71 pcireg_t footbridge_pci_conf_read __P((void *, pcitag_t, int)); 72 void footbridge_pci_conf_write __P((void *, pcitag_t, int, 73 pcireg_t)); 74 int footbridge_pci_intr_map __P((struct pci_attach_args *, 75 pci_intr_handle_t *)); 76 const char *footbridge_pci_intr_string __P((void *, pci_intr_handle_t)); 77 const struct evcnt *footbridge_pci_intr_evcnt __P((void *, pci_intr_handle_t)); 78 void *footbridge_pci_intr_establish __P((void *, pci_intr_handle_t, 79 int, int (*)(void *), void *)); 80 void footbridge_pci_intr_disestablish __P((void *, void *)); 81 82 83 struct arm32_pci_chipset footbridge_pci_chipset = { 84 NULL, /* conf_v */ 85 #ifdef NETWINDER 86 netwinder_pci_attach_hook, 87 #else 88 footbridge_pci_attach_hook, 89 #endif 90 footbridge_pci_bus_maxdevs, 91 footbridge_pci_make_tag, 92 footbridge_pci_decompose_tag, 93 footbridge_pci_conf_read, 94 footbridge_pci_conf_write, 95 NULL, /* intr_v */ 96 footbridge_pci_intr_map, 97 footbridge_pci_intr_string, 98 footbridge_pci_intr_evcnt, 99 footbridge_pci_intr_establish, 100 footbridge_pci_intr_disestablish 101 }; 102 103 /* 104 * PCI doesn't have any special needs; just use the generic versions 105 * of these functions. 106 */ 107 struct arm32_bus_dma_tag footbridge_pci_bus_dma_tag = { 108 0, 109 0, 110 _bus_dmamap_create, 111 _bus_dmamap_destroy, 112 _bus_dmamap_load, 113 _bus_dmamap_load_mbuf, 114 _bus_dmamap_load_uio, 115 _bus_dmamap_load_raw, 116 _bus_dmamap_unload, 117 _bus_dmamap_sync, 118 _bus_dmamem_alloc, 119 _bus_dmamem_free, 120 _bus_dmamem_map, 121 _bus_dmamem_unmap, 122 _bus_dmamem_mmap, 123 }; 124 125 /* 126 * Currently we only support 12 devices as we select directly in the 127 * type 0 config cycle 128 * (See conf_{read,write} for more detail 129 */ 130 #define MAX_PCI_DEVICES 21 131 132 /*static int 133 pci_intr(void *arg) 134 { 135 printf("pci int %x\n", (int)arg); 136 return(0); 137 }*/ 138 139 140 void 141 footbridge_pci_attach_hook(parent, self, pba) 142 struct device *parent, *self; 143 struct pcibus_attach_args *pba; 144 { 145 #ifdef PCI_DEBUG 146 printf("footbridge_pci_attach_hook()\n"); 147 #endif 148 149 /* intr_claim(18, IPL_NONE, "pci int 0", pci_intr, (void *)0x10000); 150 intr_claim(8, IPL_NONE, "pci int 1", pci_intr, (void *)0x10001); 151 intr_claim(9, IPL_NONE, "pci int 2", pci_intr, (void *)0x10002); 152 intr_claim(11, IPL_NONE, "pci int 3", pci_intr, (void *)0x10003);*/ 153 } 154 155 int 156 footbridge_pci_bus_maxdevs(pcv, busno) 157 void *pcv; 158 int busno; 159 { 160 #ifdef PCI_DEBUG 161 printf("footbridge_pci_bus_maxdevs(pcv=%p, busno=%d)\n", pcv, busno); 162 #endif 163 return(MAX_PCI_DEVICES); 164 } 165 166 pcitag_t 167 footbridge_pci_make_tag(pcv, bus, device, function) 168 void *pcv; 169 int bus, device, function; 170 { 171 #ifdef PCI_DEBUG 172 printf("footbridge_pci_make_tag(pcv=%p, bus=%d, device=%d, function=%d)\n", 173 pcv, bus, device, function); 174 #endif 175 return ((bus << 16) | (device << 11) | (function << 8)); 176 } 177 178 void 179 footbridge_pci_decompose_tag(pcv, tag, busp, devicep, functionp) 180 void *pcv; 181 pcitag_t tag; 182 int *busp, *devicep, *functionp; 183 { 184 #ifdef PCI_DEBUG 185 printf("footbridge_pci_decompose_tag(pcv=%p, tag=0x%08x, bp=%x, dp=%x, fp=%x)\n", 186 pcv, tag, busp, devicep, functionp); 187 #endif 188 189 if (busp != NULL) 190 *busp = (tag >> 16) & 0xff; 191 if (devicep != NULL) 192 *devicep = (tag >> 11) & 0x1f; 193 if (functionp != NULL) 194 *functionp = (tag >> 8) & 0x7; 195 } 196 197 pcireg_t 198 footbridge_pci_conf_read(pcv, tag, reg) 199 void *pcv; 200 pcitag_t tag; 201 int reg; 202 { 203 int bus, device, function; 204 u_int address; 205 pcireg_t data; 206 207 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 208 if (bus == 0) 209 /* Limited to 12 devices or we exceed type 0 config space */ 210 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 211 else 212 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 213 (bus << 16); 214 215 address |= (function << 8) | reg; 216 217 data = *((unsigned int *)address); 218 #ifdef PCI_DEBUG 219 printf("footbridge_pci_conf_read(pcv=%p tag=0x%08x reg=0x%02x)=0x%08x\n", 220 pcv, tag, reg, data); 221 #endif 222 return(data); 223 } 224 225 void 226 footbridge_pci_conf_write(pcv, tag, reg, data) 227 void *pcv; 228 pcitag_t tag; 229 int reg; 230 pcireg_t data; 231 { 232 int bus, device, function; 233 u_int address; 234 235 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 236 if (bus == 0) 237 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 238 else 239 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 240 (bus << 16); 241 242 address |= (function << 8) | reg; 243 244 #ifdef PCI_DEBUG 245 printf("footbridge_pci_conf_write(pcv=%p tag=0x%08x reg=0x%02x, 0x%08x)\n", 246 pcv, tag, reg, data); 247 #endif 248 249 *((unsigned int *)address) = data; 250 } 251 252 int 253 footbridge_pci_intr_map(pa, ihp) 254 struct pci_attach_args *pa; 255 pci_intr_handle_t *ihp; 256 { 257 int pin = pa->pa_intrpin, line = pa->pa_intrline; 258 int intr = -1; 259 260 #ifdef PCI_DEBUG 261 void *pcv = pa->pa_pc; 262 pcitag_t intrtag = pa->pa_intrtag; 263 int bus, device, function; 264 265 footbridge_pci_decompose_tag(pcv, intrtag, &bus, &device, &function); 266 printf("footbride_pci_intr_map: pcv=%p, tag=%08lx pin=%d line=%d dev=%d\n", 267 pcv, intrtag, pin, line, device); 268 #endif 269 270 /* 271 * Only the line is used to map the interrupt. 272 * The firmware is expected to setup up the interrupt 273 * line as seen from the CPU 274 * This means the firmware deals with the interrupt rotation 275 * between slots etc. 276 * 277 * Perhaps the firmware should also to the final mapping 278 * to a 21285 interrupt bit so the code below would be 279 * completely MI. 280 */ 281 282 switch (line) { 283 case PCI_INTERRUPT_PIN_NONE: 284 case 0xff: 285 /* No IRQ */ 286 printf("pci_intr_map: no mapping for pin %c\n", '@' + pin); 287 *ihp = -1; 288 return(1); 289 break; 290 #ifdef EBSA285 291 /* This is machine dependant and needs to be moved */ 292 case PCI_INTERRUPT_PIN_A: 293 intr = IRQ_PCI; 294 break; 295 case PCI_INTERRUPT_PIN_B: 296 intr = IRQ_IN_L0; 297 break; 298 case PCI_INTERRUPT_PIN_C: 299 intr = IRQ_IN_L1; 300 break; 301 case PCI_INTERRUPT_PIN_D: 302 intr = IRQ_IN_L3; 303 break; 304 #endif 305 default: 306 /* 307 * Experimental firmware feature ... 308 * 309 * If the interrupt line is in the range 0x80 to 0x8F 310 * then the lower 4 bits indicate the ISA interrupt 311 * bit that should be used. 312 * If the interrupt line is in the range 0x40 to 0x5F 313 * then the lower 5 bits indicate the actual DC21285 314 * interrupt bit that should be used. 315 */ 316 317 if (line >= 0x40 && line <= 0x5f) 318 intr = line & 0x1f; 319 else if (line >= 0x80 && line <= 0x8f) 320 intr = line; 321 else { 322 printf("footbridge_pci_intr_map: out of range interrupt" 323 "pin %d line %d (%#x)\n", pin, line, line); 324 *ihp = -1; 325 return(1); 326 } 327 break; 328 } 329 330 #ifdef PCI_DEBUG 331 printf("pin %d, line %d mapped to int %d\n", pin, line, intr); 332 #endif 333 334 *ihp = intr; 335 return(0); 336 } 337 338 const char * 339 footbridge_pci_intr_string(pcv, ih) 340 void *pcv; 341 pci_intr_handle_t ih; 342 { 343 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 344 345 #ifdef PCI_DEBUG 346 printf("footbridge_pci_intr_string(pcv=0x%p, ih=0x%lx)\n", pcv, ih); 347 #endif 348 if (ih == 0) 349 panic("footbridge_pci_intr_string: bogus handle 0x%lx\n", ih); 350 351 #if NISA > 0 352 if (ih >= 0x80 && ih <= 0x8f) { 353 sprintf(irqstr, "isairq %ld", (ih & 0x0f)); 354 return(irqstr); 355 } 356 #endif 357 sprintf(irqstr, "irq %ld", ih); 358 return(irqstr); 359 } 360 361 const struct evcnt * 362 footbridge_pci_intr_evcnt(pcv, ih) 363 void *pcv; 364 pci_intr_handle_t ih; 365 { 366 367 /* XXX for now, no evcnt parent reported */ 368 return NULL; 369 } 370 371 void * 372 footbridge_pci_intr_establish(pcv, ih, level, func, arg) 373 void *pcv; 374 pci_intr_handle_t ih; 375 int level, (*func) __P((void *)); 376 void *arg; 377 { 378 void *intr; 379 int length; 380 char *string; 381 382 #ifdef PCI_DEBUG 383 printf("footbridge_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, func=%p, arg=%p)\n", 384 pcv, ih, level, func, arg); 385 #endif 386 387 /* Copy the interrupt string to a private buffer */ 388 length = strlen(footbridge_pci_intr_string(pcv, ih)); 389 string = malloc(length + 1, M_DEVBUF, M_WAITOK); 390 strcpy(string, footbridge_pci_intr_string(pcv, ih)); 391 #if NISA > 0 392 /* 393 * XXX the IDE driver will attach the interrupts in compat mode and 394 * thus we need to fail this here. 395 * This assumes that the interrupts are 14 and 15 which they are for 396 * IDE compat mode. 397 * Really the firmware should make this clear in the interrupt reg. 398 */ 399 if (ih >= 0x80 && ih <= 0x8d) { 400 intr = isa_intr_establish(NULL, (ih & 0x0f), IST_EDGE, 401 level, func, arg); 402 } else 403 #endif 404 intr = intr_claim(ih, level, string, func, arg); 405 406 return(intr); 407 } 408 409 void 410 footbridge_pci_intr_disestablish(pcv, cookie) 411 void *pcv; 412 void *cookie; 413 { 414 #ifdef PCI_DEBUG 415 printf("footbridge_pci_intr_disestablish(pcv=%p, cookie=0x%x)\n", 416 pcv, cookie); 417 #endif 418 /* XXXX Need to free the string */ 419 420 intr_release(cookie); 421 } 422
Indexes created Mon Sep 29 21:09:56 GMT 2025