footbridge_pci.c revision 1.17
1 /* $NetBSD: footbridge_pci.c,v 1.17 2009/03/14 15:36:02 dsl Exp $ */ 2 3 /* 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997,1998 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: footbridge_pci.c,v 1.17 2009/03/14 15:36:02 dsl Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/conf.h> 43 #include <sys/malloc.h> 44 #include <sys/device.h> 45 46 #define _ARM32_BUS_DMA_PRIVATE 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 #include <arm/footbridge/dc21285reg.h> 54 #include <arm/footbridge/dc21285mem.h> 55 56 #include "isa.h" 57 #if NISA > 0 58 #include <dev/isa/isavar.h> 59 #endif 60 61 void footbridge_pci_attach_hook(struct device *, 62 struct device *, struct pcibus_attach_args *); 63 int footbridge_pci_bus_maxdevs(void *, int); 64 pcitag_t footbridge_pci_make_tag(void *, int, int, int); 65 void footbridge_pci_decompose_tag(void *, pcitag_t, int *, 66 int *, int *); 67 pcireg_t footbridge_pci_conf_read(void *, pcitag_t, int); 68 void footbridge_pci_conf_write(void *, pcitag_t, int, 69 pcireg_t); 70 int footbridge_pci_intr_map(struct pci_attach_args *, 71 pci_intr_handle_t *); 72 const char *footbridge_pci_intr_string(void *, pci_intr_handle_t); 73 void *footbridge_pci_intr_establish(void *, pci_intr_handle_t, 74 int, int (*)(void *), void *); 75 void footbridge_pci_intr_disestablish(void *, void *); 76 const struct evcnt *footbridge_pci_intr_evcnt(void *, pci_intr_handle_t); 77 78 struct arm32_pci_chipset footbridge_pci_chipset = { 79 NULL, /* conf_v */ 80 #ifdef netwinder 81 netwinder_pci_attach_hook, 82 #else 83 footbridge_pci_attach_hook, 84 #endif 85 footbridge_pci_bus_maxdevs, 86 footbridge_pci_make_tag, 87 footbridge_pci_decompose_tag, 88 footbridge_pci_conf_read, 89 footbridge_pci_conf_write, 90 NULL, /* intr_v */ 91 footbridge_pci_intr_map, 92 footbridge_pci_intr_string, 93 footbridge_pci_intr_evcnt, 94 footbridge_pci_intr_establish, 95 footbridge_pci_intr_disestablish 96 }; 97 98 struct arm32_dma_range footbridge_dma_ranges[1]; 99 100 /* 101 * PCI doesn't have any special needs; just use the generic versions 102 * of these functions. 103 */ 104 struct arm32_bus_dma_tag footbridge_pci_bus_dma_tag = { 105 footbridge_dma_ranges, 106 1, 107 NULL, 108 _bus_dmamap_create, 109 _bus_dmamap_destroy, 110 _bus_dmamap_load, 111 _bus_dmamap_load_mbuf, 112 _bus_dmamap_load_uio, 113 _bus_dmamap_load_raw, 114 _bus_dmamap_unload, 115 _bus_dmamap_sync, /* pre */ 116 NULL, /* post */ 117 _bus_dmamem_alloc, 118 _bus_dmamem_free, 119 _bus_dmamem_map, 120 _bus_dmamem_unmap, 121 _bus_dmamem_mmap, 122 }; 123 124 /* 125 * Currently we only support 12 devices as we select directly in the 126 * type 0 config cycle 127 * (See conf_{read,write} for more detail 128 */ 129 #define MAX_PCI_DEVICES 21 130 131 /*static int 132 pci_intr(void *arg) 133 { 134 printf("pci int %x\n", (int)arg); 135 return(0); 136 }*/ 137 138 139 void 140 footbridge_pci_attach_hook(parent, self, pba) 141 struct device *parent, *self; 142 struct pcibus_attach_args *pba; 143 { 144 #ifdef PCI_DEBUG 145 printf("footbridge_pci_attach_hook()\n"); 146 #endif 147 148 /* intr_claim(18, IPL_NONE, "pci int 0", pci_intr, (void *)0x10000); 149 intr_claim(8, IPL_NONE, "pci int 1", pci_intr, (void *)0x10001); 150 intr_claim(9, IPL_NONE, "pci int 2", pci_intr, (void *)0x10002); 151 intr_claim(11, IPL_NONE, "pci int 3", pci_intr, (void *)0x10003);*/ 152 } 153 154 int 155 footbridge_pci_bus_maxdevs(void *pcv, int busno) 156 { 157 #ifdef PCI_DEBUG 158 printf("footbridge_pci_bus_maxdevs(pcv=%p, busno=%d)\n", pcv, busno); 159 #endif 160 return(MAX_PCI_DEVICES); 161 } 162 163 pcitag_t 164 footbridge_pci_make_tag(pcv, bus, device, function) 165 void *pcv; 166 int bus, device, function; 167 { 168 #ifdef PCI_DEBUG 169 printf("footbridge_pci_make_tag(pcv=%p, bus=%d, device=%d, function=%d)\n", 170 pcv, bus, device, function); 171 #endif 172 return ((bus << 16) | (device << 11) | (function << 8)); 173 } 174 175 void 176 footbridge_pci_decompose_tag(pcv, tag, busp, devicep, functionp) 177 void *pcv; 178 pcitag_t tag; 179 int *busp, *devicep, *functionp; 180 { 181 #ifdef PCI_DEBUG 182 printf("footbridge_pci_decompose_tag(pcv=%p, tag=0x%08x, bp=%p, dp=%p, fp=%p)\n", 183 pcv, (uint32_t)tag, busp, devicep, functionp); 184 #endif 185 186 if (busp != NULL) 187 *busp = (tag >> 16) & 0xff; 188 if (devicep != NULL) 189 *devicep = (tag >> 11) & 0x1f; 190 if (functionp != NULL) 191 *functionp = (tag >> 8) & 0x7; 192 } 193 194 pcireg_t 195 footbridge_pci_conf_read(void *pcv, pcitag_t tag, int reg) 196 { 197 int bus, device, function; 198 u_int address; 199 pcireg_t data; 200 201 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 202 if (bus == 0) 203 /* Limited to 12 devices or we exceed type 0 config space */ 204 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 205 else 206 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 207 (bus << 16); 208 209 address |= (function << 8) | reg; 210 211 data = *((unsigned int *)address); 212 #ifdef PCI_DEBUG 213 printf("footbridge_pci_conf_read(pcv=%p tag=0x%08x reg=0x%02x)=0x%08x\n", 214 pcv, (uint32_t)tag, reg, data); 215 #endif 216 return(data); 217 } 218 219 void 220 footbridge_pci_conf_write(void *pcv, pcitag_t tag, int reg, pcireg_t data) 221 { 222 int bus, device, function; 223 u_int address; 224 225 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 226 if (bus == 0) 227 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 228 else 229 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 230 (bus << 16); 231 232 address |= (function << 8) | reg; 233 234 #ifdef PCI_DEBUG 235 printf("footbridge_pci_conf_write(pcv=%p tag=0x%08x reg=0x%02x, 0x%08x)\n", 236 pcv, (uint32_t)tag, reg, data); 237 #endif 238 239 *((unsigned int *)address) = data; 240 } 241 242 int 243 footbridge_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 244 { 245 int pin = pa->pa_intrpin, line = pa->pa_intrline; 246 int intr = -1; 247 248 #ifdef PCI_DEBUG 249 void *pcv = pa->pa_pc; 250 pcitag_t intrtag = pa->pa_intrtag; 251 int bus, device, function; 252 253 footbridge_pci_decompose_tag(pcv, intrtag, &bus, &device, &function); 254 printf("footbridge_pci_intr_map: pcv=%p, tag=%08x pin=%d line=%d dev=%d\n", 255 pcv, (uint32_t)intrtag, pin, line, device); 256 #endif 257 258 /* 259 * Only the line is used to map the interrupt. 260 * The firmware is expected to setup up the interrupt 261 * line as seen from the CPU 262 * This means the firmware deals with the interrupt rotation 263 * between slots etc. 264 * 265 * Perhaps the firmware should also to the final mapping 266 * to a 21285 interrupt bit so the code below would be 267 * completely MI. 268 */ 269 270 switch (line) { 271 case PCI_INTERRUPT_PIN_NONE: 272 case 0xff: 273 /* No IRQ */ 274 printf("pci_intr_map: no mapping for pin %c\n", '@' + pin); 275 *ihp = -1; 276 return(1); 277 break; 278 #ifdef cats 279 /* This is machine dependant and needs to be moved */ 280 case PCI_INTERRUPT_PIN_A: 281 intr = IRQ_PCI; 282 break; 283 case PCI_INTERRUPT_PIN_B: 284 intr = IRQ_IN_L0; 285 break; 286 case PCI_INTERRUPT_PIN_C: 287 intr = IRQ_IN_L1; 288 break; 289 case PCI_INTERRUPT_PIN_D: 290 intr = IRQ_IN_L3; 291 break; 292 #endif 293 default: 294 /* 295 * Experimental firmware feature ... 296 * 297 * If the interrupt line is in the range 0x80 to 0x8F 298 * then the lower 4 bits indicate the ISA interrupt 299 * bit that should be used. 300 * If the interrupt line is in the range 0x40 to 0x5F 301 * then the lower 5 bits indicate the actual DC21285 302 * interrupt bit that should be used. 303 */ 304 305 if (line >= 0x40 && line <= 0x5f) 306 intr = line & 0x1f; 307 else if (line >= 0x80 && line <= 0x8f) 308 intr = line; 309 else { 310 printf("footbridge_pci_intr_map: out of range interrupt" 311 "pin %d line %d (%#x)\n", pin, line, line); 312 *ihp = -1; 313 return(1); 314 } 315 break; 316 } 317 318 #ifdef PCI_DEBUG 319 printf("pin %d, line %d mapped to int %d\n", pin, line, intr); 320 #endif 321 322 *ihp = intr; 323 return(0); 324 } 325 326 const char * 327 footbridge_pci_intr_string(void *pcv, pci_intr_handle_t ih) 328 { 329 static char irqstr[7+2+3]; /* "isairq dd" + NULL + sanity */ 330 331 #ifdef PCI_DEBUG 332 printf("footbridge_pci_intr_string(pcv=%p, ih=0x%lx)\n", pcv, ih); 333 #endif 334 if (ih == 0) 335 panic("footbridge_pci_intr_string: bogus handle 0x%lx", ih); 336 337 #if NISA > 0 338 if (ih >= 0x80 && ih <= 0x8f) { 339 sprintf(irqstr, "isairq %ld", (ih & 0x0f)); 340 return(irqstr); 341 } 342 #endif 343 sprintf(irqstr, "irq %ld", ih); 344 return(irqstr); 345 } 346 347 void * 348 footbridge_pci_intr_establish(pcv, ih, level, func, arg) 349 void *pcv; 350 pci_intr_handle_t ih; 351 int level, (*func)(void *); 352 void *arg; 353 { 354 void *intr; 355 int length; 356 char *string; 357 358 #ifdef PCI_DEBUG 359 printf("footbridge_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, func=%p, arg=%p)\n", 360 pcv, ih, level, func, arg); 361 #endif 362 363 /* Copy the interrupt string to a private buffer */ 364 length = strlen(footbridge_pci_intr_string(pcv, ih)); 365 string = malloc(length + 1, M_DEVBUF, M_WAITOK); 366 strcpy(string, footbridge_pci_intr_string(pcv, ih)); 367 #if NISA > 0 368 /* 369 * XXX the IDE driver will attach the interrupts in compat mode and 370 * thus we need to fail this here. 371 * This assumes that the interrupts are 14 and 15 which they are for 372 * IDE compat mode. 373 * Really the firmware should make this clear in the interrupt reg. 374 */ 375 if (ih >= 0x80 && ih <= 0x8d) { 376 intr = isa_intr_establish(NULL, (ih & 0x0f), IST_EDGE, 377 level, func, arg); 378 } else 379 #endif 380 intr = footbridge_intr_claim(ih, level, string, func, arg); 381 382 return(intr); 383 } 384 385 void 386 footbridge_pci_intr_disestablish(void *pcv, void *cookie) 387 { 388 #ifdef PCI_DEBUG 389 printf("footbridge_pci_intr_disestablish(pcv=%p, cookie=0x%p)\n", 390 pcv, cookie); 391 #endif 392 /* XXXX Need to free the string */ 393 footbridge_intr_disestablish(cookie); 394 } 395
Indexes created Mon Sep 29 21:09:56 GMT 2025