footbridge_pci.c revision 1.2
1 /* $NetBSD: footbridge_pci.c,v 1.2 2001/06/12 17:10:26 matt Exp $ */ 2 3 /* 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997,1998 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include "opt_ebsa285.h" 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/conf.h> 42 #include <sys/malloc.h> 43 #include <sys/device.h> 44 45 #define _ARM32_BUS_DMA_PRIVATE 46 #include <machine/bus.h> 47 #include <machine/irqhandler.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 52 #include <arm/footbridge/dc21285reg.h> 53 #include <arm/footbridge/dc21285mem.h> 54 55 #include "isa.h" 56 #if NISA > 0 57 #include <dev/isa/isavar.h> 58 #endif 59 60 #ifdef netwinder 61 void netwinder_pci_attach_hook __P((struct device *, 62 struct device *, struct pcibus_attach_args *)); 63 #endif 64 void footbridge_pci_attach_hook __P((struct device *, 65 struct device *, struct pcibus_attach_args *)); 66 int footbridge_pci_bus_maxdevs __P((void *, int)); 67 pcitag_t footbridge_pci_make_tag __P((void *, int, int, int)); 68 void footbridge_pci_decompose_tag __P((void *, pcitag_t, int *, 69 int *, int *)); 70 pcireg_t footbridge_pci_conf_read __P((void *, pcitag_t, int)); 71 void footbridge_pci_conf_write __P((void *, pcitag_t, int, 72 pcireg_t)); 73 int footbridge_pci_intr_map __P((struct pci_attach_args *, 74 pci_intr_handle_t *)); 75 const char *footbridge_pci_intr_string __P((void *, pci_intr_handle_t)); 76 const struct evcnt *footbridge_pci_intr_evcnt __P((void *, pci_intr_handle_t)); 77 void *footbridge_pci_intr_establish __P((void *, pci_intr_handle_t, 78 int, int (*)(void *), void *)); 79 void footbridge_pci_intr_disestablish __P((void *, void *)); 80 81 82 struct arm32_pci_chipset footbridge_pci_chipset = { 83 NULL, /* conf_v */ 84 #ifdef netwinder 85 netwinder_pci_attach_hook, 86 #else 87 footbridge_pci_attach_hook, 88 #endif 89 footbridge_pci_bus_maxdevs, 90 footbridge_pci_make_tag, 91 footbridge_pci_decompose_tag, 92 footbridge_pci_conf_read, 93 footbridge_pci_conf_write, 94 NULL, /* intr_v */ 95 footbridge_pci_intr_map, 96 footbridge_pci_intr_string, 97 footbridge_pci_intr_evcnt, 98 footbridge_pci_intr_establish, 99 footbridge_pci_intr_disestablish 100 }; 101 102 /* 103 * PCI doesn't have any special needs; just use the generic versions 104 * of these functions. 105 */ 106 struct arm32_bus_dma_tag footbridge_pci_bus_dma_tag = { 107 0, 108 0, 109 _bus_dmamap_create, 110 _bus_dmamap_destroy, 111 _bus_dmamap_load, 112 _bus_dmamap_load_mbuf, 113 _bus_dmamap_load_uio, 114 _bus_dmamap_load_raw, 115 _bus_dmamap_unload, 116 _bus_dmamap_sync, 117 _bus_dmamem_alloc, 118 _bus_dmamem_free, 119 _bus_dmamem_map, 120 _bus_dmamem_unmap, 121 _bus_dmamem_mmap, 122 }; 123 124 /* 125 * Currently we only support 12 devices as we select directly in the 126 * type 0 config cycle 127 * (See conf_{read,write} for more detail 128 */ 129 #define MAX_PCI_DEVICES 21 130 131 /*static int 132 pci_intr(void *arg) 133 { 134 printf("pci int %x\n", (int)arg); 135 return(0); 136 }*/ 137 138 139 void 140 footbridge_pci_attach_hook(parent, self, pba) 141 struct device *parent, *self; 142 struct pcibus_attach_args *pba; 143 { 144 #ifdef PCI_DEBUG 145 printf("footbridge_pci_attach_hook()\n"); 146 #endif 147 148 /* intr_claim(18, IPL_NONE, "pci int 0", pci_intr, (void *)0x10000); 149 intr_claim(8, IPL_NONE, "pci int 1", pci_intr, (void *)0x10001); 150 intr_claim(9, IPL_NONE, "pci int 2", pci_intr, (void *)0x10002); 151 intr_claim(11, IPL_NONE, "pci int 3", pci_intr, (void *)0x10003);*/ 152 } 153 154 int 155 footbridge_pci_bus_maxdevs(pcv, busno) 156 void *pcv; 157 int busno; 158 { 159 #ifdef PCI_DEBUG 160 printf("footbridge_pci_bus_maxdevs(pcv=%p, busno=%d)\n", pcv, busno); 161 #endif 162 return(MAX_PCI_DEVICES); 163 } 164 165 pcitag_t 166 footbridge_pci_make_tag(pcv, bus, device, function) 167 void *pcv; 168 int bus, device, function; 169 { 170 #ifdef PCI_DEBUG 171 printf("footbridge_pci_make_tag(pcv=%p, bus=%d, device=%d, function=%d)\n", 172 pcv, bus, device, function); 173 #endif 174 return ((bus << 16) | (device << 11) | (function << 8)); 175 } 176 177 void 178 footbridge_pci_decompose_tag(pcv, tag, busp, devicep, functionp) 179 void *pcv; 180 pcitag_t tag; 181 int *busp, *devicep, *functionp; 182 { 183 #ifdef PCI_DEBUG 184 printf("footbridge_pci_decompose_tag(pcv=%p, tag=0x%08x, bp=%x, dp=%x, fp=%x)\n", 185 pcv, tag, busp, devicep, functionp); 186 #endif 187 188 if (busp != NULL) 189 *busp = (tag >> 16) & 0xff; 190 if (devicep != NULL) 191 *devicep = (tag >> 11) & 0x1f; 192 if (functionp != NULL) 193 *functionp = (tag >> 8) & 0x7; 194 } 195 196 pcireg_t 197 footbridge_pci_conf_read(pcv, tag, reg) 198 void *pcv; 199 pcitag_t tag; 200 int reg; 201 { 202 int bus, device, function; 203 u_int address; 204 pcireg_t data; 205 206 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 207 if (bus == 0) 208 /* Limited to 12 devices or we exceed type 0 config space */ 209 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 210 else 211 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 212 (bus << 16); 213 214 address |= (function << 8) | reg; 215 216 data = *((unsigned int *)address); 217 #ifdef PCI_DEBUG 218 printf("footbridge_pci_conf_read(pcv=%p tag=0x%08x reg=0x%02x)=0x%08x\n", 219 pcv, tag, reg, data); 220 #endif 221 return(data); 222 } 223 224 void 225 footbridge_pci_conf_write(pcv, tag, reg, data) 226 void *pcv; 227 pcitag_t tag; 228 int reg; 229 pcireg_t data; 230 { 231 int bus, device, function; 232 u_int address; 233 234 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 235 if (bus == 0) 236 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 237 else 238 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 239 (bus << 16); 240 241 address |= (function << 8) | reg; 242 243 #ifdef PCI_DEBUG 244 printf("footbridge_pci_conf_write(pcv=%p tag=0x%08x reg=0x%02x, 0x%08x)\n", 245 pcv, tag, reg, data); 246 #endif 247 248 *((unsigned int *)address) = data; 249 } 250 251 int 252 footbridge_pci_intr_map(pa, ihp) 253 struct pci_attach_args *pa; 254 pci_intr_handle_t *ihp; 255 { 256 int pin = pa->pa_intrpin, line = pa->pa_intrline; 257 int intr = -1; 258 259 #ifdef PCI_DEBUG 260 void *pcv = pa->pa_pc; 261 pcitag_t intrtag = pa->pa_intrtag; 262 int bus, device, function; 263 264 footbridge_pci_decompose_tag(pcv, intrtag, &bus, &device, &function); 265 printf("footbride_pci_intr_map: pcv=%p, tag=%08lx pin=%d line=%d dev=%d\n", 266 pcv, intrtag, pin, line, device); 267 #endif 268 269 /* 270 * Only the line is used to map the interrupt. 271 * The firmware is expected to setup up the interrupt 272 * line as seen from the CPU 273 * This means the firmware deals with the interrupt rotation 274 * between slots etc. 275 * 276 * Perhaps the firmware should also to the final mapping 277 * to a 21285 interrupt bit so the code below would be 278 * completely MI. 279 */ 280 281 switch (line) { 282 case PCI_INTERRUPT_PIN_NONE: 283 case 0xff: 284 /* No IRQ */ 285 printf("pci_intr_map: no mapping for pin %c\n", '@' + pin); 286 *ihp = -1; 287 return(1); 288 break; 289 #ifdef EBSA285 290 /* This is machine dependant and needs to be moved */ 291 case PCI_INTERRUPT_PIN_A: 292 intr = IRQ_PCI; 293 break; 294 case PCI_INTERRUPT_PIN_B: 295 intr = IRQ_IN_L0; 296 break; 297 case PCI_INTERRUPT_PIN_C: 298 intr = IRQ_IN_L1; 299 break; 300 case PCI_INTERRUPT_PIN_D: 301 intr = IRQ_IN_L3; 302 break; 303 #endif 304 default: 305 /* 306 * Experimental firmware feature ... 307 * 308 * If the interrupt line is in the range 0x80 to 0x8F 309 * then the lower 4 bits indicate the ISA interrupt 310 * bit that should be used. 311 * If the interrupt line is in the range 0x40 to 0x5F 312 * then the lower 5 bits indicate the actual DC21285 313 * interrupt bit that should be used. 314 */ 315 316 if (line >= 0x40 && line <= 0x5f) 317 intr = line & 0x1f; 318 else if (line >= 0x80 && line <= 0x8f) 319 intr = line; 320 else { 321 printf("footbridge_pci_intr_map: out of range interrupt" 322 "pin %d line %d (%#x)\n", pin, line, line); 323 *ihp = -1; 324 return(1); 325 } 326 break; 327 } 328 329 #ifdef PCI_DEBUG 330 printf("pin %d, line %d mapped to int %d\n", pin, line, intr); 331 #endif 332 333 *ihp = intr; 334 return(0); 335 } 336 337 const char * 338 footbridge_pci_intr_string(pcv, ih) 339 void *pcv; 340 pci_intr_handle_t ih; 341 { 342 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 343 344 #ifdef PCI_DEBUG 345 printf("footbridge_pci_intr_string(pcv=0x%p, ih=0x%lx)\n", pcv, ih); 346 #endif 347 if (ih == 0) 348 panic("footbridge_pci_intr_string: bogus handle 0x%lx\n", ih); 349 350 #if NISA > 0 351 if (ih >= 0x80 && ih <= 0x8f) { 352 sprintf(irqstr, "isairq %ld", (ih & 0x0f)); 353 return(irqstr); 354 } 355 #endif 356 sprintf(irqstr, "irq %ld", ih); 357 return(irqstr); 358 } 359 360 const struct evcnt * 361 footbridge_pci_intr_evcnt(pcv, ih) 362 void *pcv; 363 pci_intr_handle_t ih; 364 { 365 366 /* XXX for now, no evcnt parent reported */ 367 return NULL; 368 } 369 370 void * 371 footbridge_pci_intr_establish(pcv, ih, level, func, arg) 372 void *pcv; 373 pci_intr_handle_t ih; 374 int level, (*func) __P((void *)); 375 void *arg; 376 { 377 void *intr; 378 int length; 379 char *string; 380 381 #ifdef PCI_DEBUG 382 printf("footbridge_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, func=%p, arg=%p)\n", 383 pcv, ih, level, func, arg); 384 #endif 385 386 /* Copy the interrupt string to a private buffer */ 387 length = strlen(footbridge_pci_intr_string(pcv, ih)); 388 string = malloc(length + 1, M_DEVBUF, M_WAITOK); 389 strcpy(string, footbridge_pci_intr_string(pcv, ih)); 390 #if NISA > 0 391 /* 392 * XXX the IDE driver will attach the interrupts in compat mode and 393 * thus we need to fail this here. 394 * This assumes that the interrupts are 14 and 15 which they are for 395 * IDE compat mode. 396 * Really the firmware should make this clear in the interrupt reg. 397 */ 398 if (ih >= 0x80 && ih <= 0x8d) { 399 intr = isa_intr_establish(NULL, (ih & 0x0f), IST_EDGE, 400 level, func, arg); 401 } else 402 #endif 403 intr = intr_claim(ih, level, string, func, arg); 404 405 return(intr); 406 } 407 408 void 409 footbridge_pci_intr_disestablish(pcv, cookie) 410 void *pcv; 411 void *cookie; 412 { 413 #ifdef PCI_DEBUG 414 printf("footbridge_pci_intr_disestablish(pcv=%p, cookie=0x%x)\n", 415 pcv, cookie); 416 #endif 417 /* XXXX Need to free the string */ 418 419 intr_release(cookie); 420 } 421
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