footbridge_pci.c revision 1.24.2.1
1 /* $NetBSD: footbridge_pci.c,v 1.24.2.1 2014/05/18 17:44:57 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997,1998 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: footbridge_pci.c,v 1.24.2.1 2014/05/18 17:44:57 rmind Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/conf.h> 43 #include <sys/malloc.h> 44 #include <sys/device.h> 45 46 #define _ARM32_BUS_DMA_PRIVATE 47 #include <sys/bus.h> 48 #include <machine/intr.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 #include <arm/footbridge/dc21285reg.h> 54 #include <arm/footbridge/dc21285mem.h> 55 56 #include "isa.h" 57 #if NISA > 0 58 #include <dev/isa/isavar.h> 59 #endif 60 61 void footbridge_pci_attach_hook(device_t, device_t, 62 struct pcibus_attach_args *); 63 int footbridge_pci_bus_maxdevs(void *, int); 64 pcitag_t footbridge_pci_make_tag(void *, int, int, int); 65 void footbridge_pci_decompose_tag(void *, pcitag_t, int *, 66 int *, int *); 67 pcireg_t footbridge_pci_conf_read(void *, pcitag_t, int); 68 void footbridge_pci_conf_write(void *, pcitag_t, int, 69 pcireg_t); 70 int footbridge_pci_intr_map(const struct pci_attach_args *, 71 pci_intr_handle_t *); 72 const char *footbridge_pci_intr_string(void *, pci_intr_handle_t, 73 char *, size_t); 74 void *footbridge_pci_intr_establish(void *, pci_intr_handle_t, 75 int, int (*)(void *), void *); 76 void footbridge_pci_intr_disestablish(void *, void *); 77 const struct evcnt *footbridge_pci_intr_evcnt(void *, pci_intr_handle_t); 78 79 struct arm32_pci_chipset footbridge_pci_chipset = { 80 NULL, /* conf_v */ 81 #ifdef netwinder 82 netwinder_pci_attach_hook, 83 #else 84 footbridge_pci_attach_hook, 85 #endif 86 footbridge_pci_bus_maxdevs, 87 footbridge_pci_make_tag, 88 footbridge_pci_decompose_tag, 89 footbridge_pci_conf_read, 90 footbridge_pci_conf_write, 91 NULL, /* intr_v */ 92 footbridge_pci_intr_map, 93 footbridge_pci_intr_string, 94 footbridge_pci_intr_evcnt, 95 footbridge_pci_intr_establish, 96 footbridge_pci_intr_disestablish 97 }; 98 99 struct arm32_dma_range footbridge_dma_ranges[1]; 100 101 /* 102 * PCI doesn't have any special needs; just use the generic versions 103 * of these functions. 104 */ 105 struct arm32_bus_dma_tag footbridge_pci_bus_dma_tag = { 106 ._ranges = footbridge_dma_ranges, 107 ._nranges = 1, 108 _BUS_DMAMAP_FUNCS, 109 _BUS_DMAMEM_FUNCS, 110 _BUS_DMATAG_FUNCS, 111 }; 112 113 /* 114 * Currently we only support 12 devices as we select directly in the 115 * type 0 config cycle 116 * (See conf_{read,write} for more detail 117 */ 118 #define MAX_PCI_DEVICES 21 119 120 /*static int 121 pci_intr(void *arg) 122 { 123 printf("pci int %x\n", (int)arg); 124 return(0); 125 }*/ 126 127 128 void 129 footbridge_pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 130 { 131 #ifdef PCI_DEBUG 132 printf("footbridge_pci_attach_hook()\n"); 133 #endif 134 135 /* intr_claim(18, IPL_NONE, "pci int 0", pci_intr, (void *)0x10000); 136 intr_claim(8, IPL_NONE, "pci int 1", pci_intr, (void *)0x10001); 137 intr_claim(9, IPL_NONE, "pci int 2", pci_intr, (void *)0x10002); 138 intr_claim(11, IPL_NONE, "pci int 3", pci_intr, (void *)0x10003);*/ 139 } 140 141 int 142 footbridge_pci_bus_maxdevs(void *pcv, int busno) 143 { 144 #ifdef PCI_DEBUG 145 printf("footbridge_pci_bus_maxdevs(pcv=%p, busno=%d)\n", pcv, busno); 146 #endif 147 return(MAX_PCI_DEVICES); 148 } 149 150 pcitag_t 151 footbridge_pci_make_tag(void *pcv, int bus, int device, int function) 152 { 153 #ifdef PCI_DEBUG 154 printf("footbridge_pci_make_tag(pcv=%p, bus=%d, device=%d, function=%d)\n", 155 pcv, bus, device, function); 156 #endif 157 return ((bus << 16) | (device << 11) | (function << 8)); 158 } 159 160 void 161 footbridge_pci_decompose_tag(void *pcv, pcitag_t tag, int *busp, int *devicep, int *functionp) 162 { 163 #ifdef PCI_DEBUG 164 printf("footbridge_pci_decompose_tag(pcv=%p, tag=0x%08x, bp=%p, dp=%p, fp=%p)\n", 165 pcv, (uint32_t)tag, busp, devicep, functionp); 166 #endif 167 168 if (busp != NULL) 169 *busp = (tag >> 16) & 0xff; 170 if (devicep != NULL) 171 *devicep = (tag >> 11) & 0x1f; 172 if (functionp != NULL) 173 *functionp = (tag >> 8) & 0x7; 174 } 175 176 pcireg_t 177 footbridge_pci_conf_read(void *pcv, pcitag_t tag, int reg) 178 { 179 int bus, device, function; 180 u_int address; 181 pcireg_t data; 182 183 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 184 if (bus == 0) 185 /* Limited to 12 devices or we exceed type 0 config space */ 186 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 187 else 188 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 189 (bus << 16); 190 191 address |= (function << 8) | reg; 192 193 data = *((unsigned int *)address); 194 #ifdef PCI_DEBUG 195 printf("footbridge_pci_conf_read(pcv=%p tag=0x%08x reg=0x%02x)=0x%08x\n", 196 pcv, (uint32_t)tag, reg, data); 197 #endif 198 return(data); 199 } 200 201 void 202 footbridge_pci_conf_write(void *pcv, pcitag_t tag, int reg, pcireg_t data) 203 { 204 int bus, device, function; 205 u_int address; 206 207 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 208 if (bus == 0) 209 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 210 else 211 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 212 (bus << 16); 213 214 address |= (function << 8) | reg; 215 216 #ifdef PCI_DEBUG 217 printf("footbridge_pci_conf_write(pcv=%p tag=0x%08x reg=0x%02x, 0x%08x)\n", 218 pcv, (uint32_t)tag, reg, data); 219 #endif 220 221 *((unsigned int *)address) = data; 222 } 223 224 int 225 footbridge_pci_intr_map(const struct pci_attach_args *pa, 226 pci_intr_handle_t *ihp) 227 { 228 int pin = pa->pa_intrpin, line = pa->pa_intrline; 229 int intr = -1; 230 231 #ifdef PCI_DEBUG 232 void *pcv = pa->pa_pc; 233 pcitag_t intrtag = pa->pa_intrtag; 234 int bus, device, function; 235 236 footbridge_pci_decompose_tag(pcv, intrtag, &bus, &device, &function); 237 printf("footbridge_pci_intr_map: pcv=%p, tag=%08x pin=%d line=%d dev=%d\n", 238 pcv, (uint32_t)intrtag, pin, line, device); 239 #endif 240 241 /* 242 * Only the line is used to map the interrupt. 243 * The firmware is expected to setup up the interrupt 244 * line as seen from the CPU 245 * This means the firmware deals with the interrupt rotation 246 * between slots etc. 247 * 248 * Perhaps the firmware should also to the final mapping 249 * to a 21285 interrupt bit so the code below would be 250 * completely MI. 251 */ 252 253 switch (line) { 254 case PCI_INTERRUPT_PIN_NONE: 255 case 0xff: 256 /* No IRQ */ 257 printf("pci_intr_map: no mapping for pin %c\n", '@' + pin); 258 *ihp = -1; 259 return(1); 260 break; 261 #ifdef cats 262 /* This is machine dependent and needs to be moved */ 263 case PCI_INTERRUPT_PIN_A: 264 intr = IRQ_PCI; 265 break; 266 case PCI_INTERRUPT_PIN_B: 267 intr = IRQ_IN_L0; 268 break; 269 case PCI_INTERRUPT_PIN_C: 270 intr = IRQ_IN_L1; 271 break; 272 case PCI_INTERRUPT_PIN_D: 273 intr = IRQ_IN_L3; 274 break; 275 #endif 276 default: 277 /* 278 * Experimental firmware feature ... 279 * 280 * If the interrupt line is in the range 0x80 to 0x8F 281 * then the lower 4 bits indicate the ISA interrupt 282 * bit that should be used. 283 * If the interrupt line is in the range 0x40 to 0x5F 284 * then the lower 5 bits indicate the actual DC21285 285 * interrupt bit that should be used. 286 */ 287 288 if (line >= 0x40 && line <= 0x5f) 289 intr = line & 0x1f; 290 else if (line >= 0x80 && line <= 0x8f) 291 intr = line; 292 else { 293 printf("footbridge_pci_intr_map: out of range interrupt" 294 "pin %d line %d (%#x)\n", pin, line, line); 295 *ihp = -1; 296 return(1); 297 } 298 break; 299 } 300 301 #ifdef PCI_DEBUG 302 printf("pin %d, line %d mapped to int %d\n", pin, line, intr); 303 #endif 304 305 *ihp = intr; 306 return(0); 307 } 308 309 const char * 310 footbridge_pci_intr_string(void *pcv, pci_intr_handle_t ih, char *buf, size_t len) 311 { 312 #ifdef PCI_DEBUG 313 printf("footbridge_pci_intr_string(pcv=%p, ih=0x%lx)\n", pcv, ih); 314 #endif 315 if (ih == 0) 316 panic("footbridge_pci_intr_string: bogus handle 0x%lx", ih); 317 318 #if NISA > 0 319 if (ih >= 0x80 && ih <= 0x8f) { 320 snprintf(buf, len, "isairq %ld", (ih & 0x0f)); 321 return buf; 322 } 323 #endif 324 snprintf(buf, len, "irq %ld", ih); 325 return buf; 326 } 327 328 void * 329 footbridge_pci_intr_establish( 330 void *pcv, 331 pci_intr_handle_t ih, 332 int level, 333 int (*func)(void *), 334 void *arg) 335 { 336 void *intr; 337 char buf[PCI_INTRSTR_LEN]; 338 const char *intrstr; 339 340 #ifdef PCI_DEBUG 341 printf("footbridge_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, func=%p, arg=%p)\n", 342 pcv, ih, level, func, arg); 343 #endif 344 345 /* Copy the interrupt string to a private buffer */ 346 intrstr = footbridge_pci_intr_string(pcv, ih, buf, sizeof(buf)); 347 #if NISA > 0 348 /* 349 * XXX the IDE driver will attach the interrupts in compat mode and 350 * thus we need to fail this here. 351 * This assumes that the interrupts are 14 and 15 which they are for 352 * IDE compat mode. 353 * Really the firmware should make this clear in the interrupt reg. 354 */ 355 if (ih >= 0x80 && ih <= 0x8d) { 356 intr = isa_intr_establish(NULL, (ih & 0x0f), IST_EDGE, 357 level, func, arg); 358 } else 359 #endif 360 intr = footbridge_intr_claim(ih, level, intrstr, func, arg); 361 362 return(intr); 363 } 364 365 void 366 footbridge_pci_intr_disestablish(void *pcv, void *cookie) 367 { 368 #ifdef PCI_DEBUG 369 printf("footbridge_pci_intr_disestablish(pcv=%p, cookie=0x%p)\n", 370 pcv, cookie); 371 #endif 372 /* XXXX Need to free the string */ 373 footbridge_intr_disestablish(cookie); 374 } 375
Indexes created Wed Oct 22 13:09:56 GMT 2025