footbridge_pci.c revision 1.28
1 /* $NetBSD: footbridge_pci.c,v 1.28 2015/10/02 05:22:49 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997,1998 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: footbridge_pci.c,v 1.28 2015/10/02 05:22:49 msaitoh Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/conf.h> 43 #include <sys/malloc.h> 44 #include <sys/device.h> 45 46 #define _ARM32_BUS_DMA_PRIVATE 47 #include <sys/bus.h> 48 #include <machine/intr.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 #include <arm/footbridge/dc21285reg.h> 54 #include <arm/footbridge/dc21285mem.h> 55 56 #include "isa.h" 57 #if NISA > 0 58 #include <dev/isa/isavar.h> 59 #endif 60 61 void footbridge_pci_attach_hook(device_t, device_t, 62 struct pcibus_attach_args *); 63 int footbridge_pci_bus_maxdevs(void *, int); 64 pcitag_t footbridge_pci_make_tag(void *, int, int, int); 65 void footbridge_pci_decompose_tag(void *, pcitag_t, int *, 66 int *, int *); 67 pcireg_t footbridge_pci_conf_read(void *, pcitag_t, int); 68 void footbridge_pci_conf_write(void *, pcitag_t, int, 69 pcireg_t); 70 int footbridge_pci_intr_map(const struct pci_attach_args *, 71 pci_intr_handle_t *); 72 const char *footbridge_pci_intr_string(void *, pci_intr_handle_t, 73 char *, size_t); 74 void *footbridge_pci_intr_establish(void *, pci_intr_handle_t, 75 int, int (*)(void *), void *); 76 void footbridge_pci_intr_disestablish(void *, void *); 77 const struct evcnt *footbridge_pci_intr_evcnt(void *, pci_intr_handle_t); 78 79 struct arm32_pci_chipset footbridge_pci_chipset = { 80 NULL, /* conf_v */ 81 #ifdef netwinder 82 netwinder_pci_attach_hook, 83 #else 84 footbridge_pci_attach_hook, 85 #endif 86 footbridge_pci_bus_maxdevs, 87 footbridge_pci_make_tag, 88 footbridge_pci_decompose_tag, 89 footbridge_pci_conf_read, 90 footbridge_pci_conf_write, 91 NULL, /* intr_v */ 92 footbridge_pci_intr_map, 93 footbridge_pci_intr_string, 94 footbridge_pci_intr_evcnt, 95 footbridge_pci_intr_establish, 96 footbridge_pci_intr_disestablish 97 }; 98 99 struct arm32_dma_range footbridge_dma_ranges[1]; 100 101 /* 102 * PCI doesn't have any special needs; just use the generic versions 103 * of these functions. 104 */ 105 struct arm32_bus_dma_tag footbridge_pci_bus_dma_tag = { 106 ._ranges = footbridge_dma_ranges, 107 ._nranges = 1, 108 _BUS_DMAMAP_FUNCS, 109 _BUS_DMAMEM_FUNCS, 110 _BUS_DMATAG_FUNCS, 111 }; 112 113 /* 114 * Currently we only support 12 devices as we select directly in the 115 * type 0 config cycle 116 * (See conf_{read,write} for more detail 117 */ 118 #define MAX_PCI_DEVICES 21 119 120 /*static int 121 pci_intr(void *arg) 122 { 123 printf("pci int %x\n", (int)arg); 124 return(0); 125 }*/ 126 127 128 void 129 footbridge_pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 130 { 131 #ifdef PCI_DEBUG 132 printf("footbridge_pci_attach_hook()\n"); 133 #endif 134 135 /* intr_claim(18, IPL_NONE, "pci int 0", pci_intr, (void *)0x10000); 136 intr_claim(8, IPL_NONE, "pci int 1", pci_intr, (void *)0x10001); 137 intr_claim(9, IPL_NONE, "pci int 2", pci_intr, (void *)0x10002); 138 intr_claim(11, IPL_NONE, "pci int 3", pci_intr, (void *)0x10003);*/ 139 } 140 141 int 142 footbridge_pci_bus_maxdevs(void *pcv, int busno) 143 { 144 #ifdef PCI_DEBUG 145 printf("footbridge_pci_bus_maxdevs(pcv=%p, busno=%d)\n", pcv, busno); 146 #endif 147 return(MAX_PCI_DEVICES); 148 } 149 150 pcitag_t 151 footbridge_pci_make_tag(void *pcv, int bus, int device, int function) 152 { 153 #ifdef PCI_DEBUG 154 printf("footbridge_pci_make_tag(pcv=%p, bus=%d, device=%d, function=%d)\n", 155 pcv, bus, device, function); 156 #endif 157 return ((bus << 16) | (device << 11) | (function << 8)); 158 } 159 160 void 161 footbridge_pci_decompose_tag(void *pcv, pcitag_t tag, int *busp, int *devicep, int *functionp) 162 { 163 #ifdef PCI_DEBUG 164 printf("footbridge_pci_decompose_tag(pcv=%p, tag=0x%08x, bp=%p, dp=%p, fp=%p)\n", 165 pcv, (uint32_t)tag, busp, devicep, functionp); 166 #endif 167 168 if (busp != NULL) 169 *busp = (tag >> 16) & 0xff; 170 if (devicep != NULL) 171 *devicep = (tag >> 11) & 0x1f; 172 if (functionp != NULL) 173 *functionp = (tag >> 8) & 0x7; 174 } 175 176 pcireg_t 177 footbridge_pci_conf_read(void *pcv, pcitag_t tag, int reg) 178 { 179 int bus, device, function; 180 u_int address; 181 pcireg_t data; 182 183 if ((unsigned int)reg >= PCI_CONF_SIZE) 184 return ((pcireg_t) -1); 185 186 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 187 if (bus == 0) 188 /* Limited to 12 devices or we exceed type 0 config space */ 189 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 190 else 191 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 192 (bus << 16); 193 194 address |= (function << 8) | reg; 195 196 data = *((unsigned int *)address); 197 #ifdef PCI_DEBUG 198 printf("footbridge_pci_conf_read(pcv=%p tag=0x%08x reg=0x%02x)=0x%08x\n", 199 pcv, (uint32_t)tag, reg, data); 200 #endif 201 return(data); 202 } 203 204 void 205 footbridge_pci_conf_write(void *pcv, pcitag_t tag, int reg, pcireg_t data) 206 { 207 int bus, device, function; 208 u_int address; 209 210 if ((unsigned int)reg >= PCI_CONF_SIZE) 211 return; 212 213 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 214 if (bus == 0) 215 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 216 else 217 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 218 (bus << 16); 219 220 address |= (function << 8) | reg; 221 222 #ifdef PCI_DEBUG 223 printf("footbridge_pci_conf_write(pcv=%p tag=0x%08x reg=0x%02x, 0x%08x)\n", 224 pcv, (uint32_t)tag, reg, data); 225 #endif 226 227 *((unsigned int *)address) = data; 228 } 229 230 int 231 footbridge_pci_intr_map(const struct pci_attach_args *pa, 232 pci_intr_handle_t *ihp) 233 { 234 int pin = pa->pa_intrpin, line = pa->pa_intrline; 235 int intr = -1; 236 237 #ifdef PCI_DEBUG 238 void *pcv = pa->pa_pc; 239 pcitag_t intrtag = pa->pa_intrtag; 240 int bus, device, function; 241 242 footbridge_pci_decompose_tag(pcv, intrtag, &bus, &device, &function); 243 printf("footbridge_pci_intr_map: pcv=%p, tag=%08x pin=%d line=%d dev=%d\n", 244 pcv, (uint32_t)intrtag, pin, line, device); 245 #endif 246 247 /* 248 * Only the line is used to map the interrupt. 249 * The firmware is expected to setup up the interrupt 250 * line as seen from the CPU 251 * This means the firmware deals with the interrupt rotation 252 * between slots etc. 253 * 254 * Perhaps the firmware should also to the final mapping 255 * to a 21285 interrupt bit so the code below would be 256 * completely MI. 257 */ 258 259 switch (line) { 260 case PCI_INTERRUPT_PIN_NONE: 261 case 0xff: 262 /* No IRQ */ 263 printf("pci_intr_map: no mapping for pin %c\n", '@' + pin); 264 *ihp = -1; 265 return(1); 266 break; 267 #ifdef cats 268 /* This is machine dependent and needs to be moved */ 269 case PCI_INTERRUPT_PIN_A: 270 intr = IRQ_PCI; 271 break; 272 case PCI_INTERRUPT_PIN_B: 273 intr = IRQ_IN_L0; 274 break; 275 case PCI_INTERRUPT_PIN_C: 276 intr = IRQ_IN_L1; 277 break; 278 case PCI_INTERRUPT_PIN_D: 279 intr = IRQ_IN_L3; 280 break; 281 #endif 282 default: 283 /* 284 * Experimental firmware feature ... 285 * 286 * If the interrupt line is in the range 0x80 to 0x8F 287 * then the lower 4 bits indicate the ISA interrupt 288 * bit that should be used. 289 * If the interrupt line is in the range 0x40 to 0x5F 290 * then the lower 5 bits indicate the actual DC21285 291 * interrupt bit that should be used. 292 */ 293 294 if (line >= 0x40 && line <= 0x5f) 295 intr = line & 0x1f; 296 else if (line >= 0x80 && line <= 0x8f) 297 intr = line; 298 else { 299 printf("footbridge_pci_intr_map: out of range interrupt" 300 "pin %d line %d (%#x)\n", pin, line, line); 301 *ihp = -1; 302 return(1); 303 } 304 break; 305 } 306 307 #ifdef PCI_DEBUG 308 printf("pin %d, line %d mapped to int %d\n", pin, line, intr); 309 #endif 310 311 *ihp = intr; 312 return(0); 313 } 314 315 const char * 316 footbridge_pci_intr_string(void *pcv, pci_intr_handle_t ih, char *buf, size_t len) 317 { 318 #ifdef PCI_DEBUG 319 printf("footbridge_pci_intr_string(pcv=%p, ih=0x%lx)\n", pcv, ih); 320 #endif 321 if (ih == 0) 322 panic("footbridge_pci_intr_string: bogus handle 0x%lx", ih); 323 324 #if NISA > 0 325 if (ih >= 0x80 && ih <= 0x8f) { 326 snprintf(buf, len, "isairq %ld", (ih & 0x0f)); 327 return buf; 328 } 329 #endif 330 snprintf(buf, len, "irq %ld", ih); 331 return buf; 332 } 333 334 void * 335 footbridge_pci_intr_establish( 336 void *pcv, 337 pci_intr_handle_t ih, 338 int level, 339 int (*func)(void *), 340 void *arg) 341 { 342 void *intr; 343 char buf[PCI_INTRSTR_LEN]; 344 const char *intrstr; 345 346 #ifdef PCI_DEBUG 347 printf("footbridge_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, func=%p, arg=%p)\n", 348 pcv, ih, level, func, arg); 349 #endif 350 351 /* Copy the interrupt string to a private buffer */ 352 intrstr = footbridge_pci_intr_string(pcv, ih, buf, sizeof(buf)); 353 #if NISA > 0 354 /* 355 * XXX the IDE driver will attach the interrupts in compat mode and 356 * thus we need to fail this here. 357 * This assumes that the interrupts are 14 and 15 which they are for 358 * IDE compat mode. 359 * Really the firmware should make this clear in the interrupt reg. 360 */ 361 if (ih >= 0x80 && ih <= 0x8d) { 362 intr = isa_intr_establish(NULL, (ih & 0x0f), IST_EDGE, 363 level, func, arg); 364 } else 365 #endif 366 intr = footbridge_intr_claim(ih, level, intrstr, func, arg); 367 368 return(intr); 369 } 370 371 void 372 footbridge_pci_intr_disestablish(void *pcv, void *cookie) 373 { 374 #ifdef PCI_DEBUG 375 printf("footbridge_pci_intr_disestablish(pcv=%p, cookie=0x%p)\n", 376 pcv, cookie); 377 #endif 378 /* XXXX Need to free the string */ 379 footbridge_intr_disestablish(cookie); 380 } 381
Indexes created Tue Sep 30 11:09:46 GMT 2025