footbridge_pci.c revision 1.29
1 /* $NetBSD: footbridge_pci.c,v 1.29 2017/04/19 08:30:00 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997,1998 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: footbridge_pci.c,v 1.29 2017/04/19 08:30:00 skrll Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/conf.h> 43 #include <sys/malloc.h> 44 #include <sys/device.h> 45 46 #define _ARM32_BUS_DMA_PRIVATE 47 #include <sys/bus.h> 48 #include <machine/intr.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 #include <arm/footbridge/dc21285reg.h> 54 #include <arm/footbridge/dc21285mem.h> 55 56 #include "isa.h" 57 #if NISA > 0 58 #include <dev/isa/isavar.h> 59 #endif 60 61 void footbridge_pci_attach_hook(device_t, device_t, 62 struct pcibus_attach_args *); 63 int footbridge_pci_bus_maxdevs(void *, int); 64 pcitag_t footbridge_pci_make_tag(void *, int, int, int); 65 void footbridge_pci_decompose_tag(void *, pcitag_t, int *, 66 int *, int *); 67 pcireg_t footbridge_pci_conf_read(void *, pcitag_t, int); 68 void footbridge_pci_conf_write(void *, pcitag_t, int, 69 pcireg_t); 70 int footbridge_pci_intr_map(const struct pci_attach_args *, 71 pci_intr_handle_t *); 72 const char *footbridge_pci_intr_string(void *, pci_intr_handle_t, 73 char *, size_t); 74 void *footbridge_pci_intr_establish(void *, pci_intr_handle_t, 75 int, int (*)(void *), void *); 76 void footbridge_pci_intr_disestablish(void *, void *); 77 const struct evcnt *footbridge_pci_intr_evcnt(void *, pci_intr_handle_t); 78 79 struct arm32_pci_chipset footbridge_pci_chipset = { 80 #ifdef netwinder 81 .pc_attach_hook = netwinder_pci_attach_hook, 82 #else 83 .pc_attach_hook = footbridge_pci_attach_hook, 84 #endif 85 .pc_bus_maxdevs = footbridge_pci_bus_maxdevs, 86 .pc_make_tag = footbridge_pci_make_tag, 87 .pc_decompose_tag = footbridge_pci_decompose_tag, 88 .pc_conf_read = footbridge_pci_conf_read, 89 .pc_conf_write = footbridge_pci_conf_write, 90 .pc_intr_map = footbridge_pci_intr_map, 91 .pc_intr_string = footbridge_pci_intr_string, 92 .pc_intr_evcnt = footbridge_pci_intr_evcnt, 93 .pc_intr_establish = footbridge_pci_intr_establish, 94 .pc_intr_disestablish = footbridge_pci_intr_disestablish 95 }; 96 97 struct arm32_dma_range footbridge_dma_ranges[1]; 98 99 /* 100 * PCI doesn't have any special needs; just use the generic versions 101 * of these functions. 102 */ 103 struct arm32_bus_dma_tag footbridge_pci_bus_dma_tag = { 104 ._ranges = footbridge_dma_ranges, 105 ._nranges = 1, 106 _BUS_DMAMAP_FUNCS, 107 _BUS_DMAMEM_FUNCS, 108 _BUS_DMATAG_FUNCS, 109 }; 110 111 /* 112 * Currently we only support 12 devices as we select directly in the 113 * type 0 config cycle 114 * (See conf_{read,write} for more detail 115 */ 116 #define MAX_PCI_DEVICES 21 117 118 /*static int 119 pci_intr(void *arg) 120 { 121 printf("pci int %x\n", (int)arg); 122 return(0); 123 }*/ 124 125 126 void 127 footbridge_pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 128 { 129 #ifdef PCI_DEBUG 130 printf("footbridge_pci_attach_hook()\n"); 131 #endif 132 133 /* intr_claim(18, IPL_NONE, "pci int 0", pci_intr, (void *)0x10000); 134 intr_claim(8, IPL_NONE, "pci int 1", pci_intr, (void *)0x10001); 135 intr_claim(9, IPL_NONE, "pci int 2", pci_intr, (void *)0x10002); 136 intr_claim(11, IPL_NONE, "pci int 3", pci_intr, (void *)0x10003);*/ 137 } 138 139 int 140 footbridge_pci_bus_maxdevs(void *pcv, int busno) 141 { 142 #ifdef PCI_DEBUG 143 printf("footbridge_pci_bus_maxdevs(pcv=%p, busno=%d)\n", pcv, busno); 144 #endif 145 return(MAX_PCI_DEVICES); 146 } 147 148 pcitag_t 149 footbridge_pci_make_tag(void *pcv, int bus, int device, int function) 150 { 151 #ifdef PCI_DEBUG 152 printf("footbridge_pci_make_tag(pcv=%p, bus=%d, device=%d, function=%d)\n", 153 pcv, bus, device, function); 154 #endif 155 return ((bus << 16) | (device << 11) | (function << 8)); 156 } 157 158 void 159 footbridge_pci_decompose_tag(void *pcv, pcitag_t tag, int *busp, int *devicep, int *functionp) 160 { 161 #ifdef PCI_DEBUG 162 printf("footbridge_pci_decompose_tag(pcv=%p, tag=0x%08x, bp=%p, dp=%p, fp=%p)\n", 163 pcv, (uint32_t)tag, busp, devicep, functionp); 164 #endif 165 166 if (busp != NULL) 167 *busp = (tag >> 16) & 0xff; 168 if (devicep != NULL) 169 *devicep = (tag >> 11) & 0x1f; 170 if (functionp != NULL) 171 *functionp = (tag >> 8) & 0x7; 172 } 173 174 pcireg_t 175 footbridge_pci_conf_read(void *pcv, pcitag_t tag, int reg) 176 { 177 int bus, device, function; 178 u_int address; 179 pcireg_t data; 180 181 if ((unsigned int)reg >= PCI_CONF_SIZE) 182 return ((pcireg_t) -1); 183 184 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 185 if (bus == 0) 186 /* Limited to 12 devices or we exceed type 0 config space */ 187 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 188 else 189 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 190 (bus << 16); 191 192 address |= (function << 8) | reg; 193 194 data = *((unsigned int *)address); 195 #ifdef PCI_DEBUG 196 printf("footbridge_pci_conf_read(pcv=%p tag=0x%08x reg=0x%02x)=0x%08x\n", 197 pcv, (uint32_t)tag, reg, data); 198 #endif 199 return(data); 200 } 201 202 void 203 footbridge_pci_conf_write(void *pcv, pcitag_t tag, int reg, pcireg_t data) 204 { 205 int bus, device, function; 206 u_int address; 207 208 if ((unsigned int)reg >= PCI_CONF_SIZE) 209 return; 210 211 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 212 if (bus == 0) 213 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 214 else 215 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 216 (bus << 16); 217 218 address |= (function << 8) | reg; 219 220 #ifdef PCI_DEBUG 221 printf("footbridge_pci_conf_write(pcv=%p tag=0x%08x reg=0x%02x, 0x%08x)\n", 222 pcv, (uint32_t)tag, reg, data); 223 #endif 224 225 *((unsigned int *)address) = data; 226 } 227 228 int 229 footbridge_pci_intr_map(const struct pci_attach_args *pa, 230 pci_intr_handle_t *ihp) 231 { 232 int pin = pa->pa_intrpin, line = pa->pa_intrline; 233 int intr = -1; 234 235 #ifdef PCI_DEBUG 236 void *pcv = pa->pa_pc; 237 pcitag_t intrtag = pa->pa_intrtag; 238 int bus, device, function; 239 240 footbridge_pci_decompose_tag(pcv, intrtag, &bus, &device, &function); 241 printf("footbridge_pci_intr_map: pcv=%p, tag=%08x pin=%d line=%d dev=%d\n", 242 pcv, (uint32_t)intrtag, pin, line, device); 243 #endif 244 245 /* 246 * Only the line is used to map the interrupt. 247 * The firmware is expected to setup up the interrupt 248 * line as seen from the CPU 249 * This means the firmware deals with the interrupt rotation 250 * between slots etc. 251 * 252 * Perhaps the firmware should also to the final mapping 253 * to a 21285 interrupt bit so the code below would be 254 * completely MI. 255 */ 256 257 switch (line) { 258 case PCI_INTERRUPT_PIN_NONE: 259 case 0xff: 260 /* No IRQ */ 261 printf("pci_intr_map: no mapping for pin %c\n", '@' + pin); 262 *ihp = -1; 263 return(1); 264 break; 265 #ifdef cats 266 /* This is machine dependent and needs to be moved */ 267 case PCI_INTERRUPT_PIN_A: 268 intr = IRQ_PCI; 269 break; 270 case PCI_INTERRUPT_PIN_B: 271 intr = IRQ_IN_L0; 272 break; 273 case PCI_INTERRUPT_PIN_C: 274 intr = IRQ_IN_L1; 275 break; 276 case PCI_INTERRUPT_PIN_D: 277 intr = IRQ_IN_L3; 278 break; 279 #endif 280 default: 281 /* 282 * Experimental firmware feature ... 283 * 284 * If the interrupt line is in the range 0x80 to 0x8F 285 * then the lower 4 bits indicate the ISA interrupt 286 * bit that should be used. 287 * If the interrupt line is in the range 0x40 to 0x5F 288 * then the lower 5 bits indicate the actual DC21285 289 * interrupt bit that should be used. 290 */ 291 292 if (line >= 0x40 && line <= 0x5f) 293 intr = line & 0x1f; 294 else if (line >= 0x80 && line <= 0x8f) 295 intr = line; 296 else { 297 printf("footbridge_pci_intr_map: out of range interrupt" 298 "pin %d line %d (%#x)\n", pin, line, line); 299 *ihp = -1; 300 return(1); 301 } 302 break; 303 } 304 305 #ifdef PCI_DEBUG 306 printf("pin %d, line %d mapped to int %d\n", pin, line, intr); 307 #endif 308 309 *ihp = intr; 310 return(0); 311 } 312 313 const char * 314 footbridge_pci_intr_string(void *pcv, pci_intr_handle_t ih, char *buf, size_t len) 315 { 316 #ifdef PCI_DEBUG 317 printf("footbridge_pci_intr_string(pcv=%p, ih=0x%lx)\n", pcv, ih); 318 #endif 319 if (ih == 0) 320 panic("footbridge_pci_intr_string: bogus handle 0x%lx", ih); 321 322 #if NISA > 0 323 if (ih >= 0x80 && ih <= 0x8f) { 324 snprintf(buf, len, "isairq %ld", (ih & 0x0f)); 325 return buf; 326 } 327 #endif 328 snprintf(buf, len, "irq %ld", ih); 329 return buf; 330 } 331 332 void * 333 footbridge_pci_intr_establish( 334 void *pcv, 335 pci_intr_handle_t ih, 336 int level, 337 int (*func)(void *), 338 void *arg) 339 { 340 void *intr; 341 char buf[PCI_INTRSTR_LEN]; 342 const char *intrstr; 343 344 #ifdef PCI_DEBUG 345 printf("footbridge_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, func=%p, arg=%p)\n", 346 pcv, ih, level, func, arg); 347 #endif 348 349 /* Copy the interrupt string to a private buffer */ 350 intrstr = footbridge_pci_intr_string(pcv, ih, buf, sizeof(buf)); 351 #if NISA > 0 352 /* 353 * XXX the IDE driver will attach the interrupts in compat mode and 354 * thus we need to fail this here. 355 * This assumes that the interrupts are 14 and 15 which they are for 356 * IDE compat mode. 357 * Really the firmware should make this clear in the interrupt reg. 358 */ 359 if (ih >= 0x80 && ih <= 0x8d) { 360 intr = isa_intr_establish(NULL, (ih & 0x0f), IST_EDGE, 361 level, func, arg); 362 } else 363 #endif 364 intr = footbridge_intr_claim(ih, level, intrstr, func, arg); 365 366 return(intr); 367 } 368 369 void 370 footbridge_pci_intr_disestablish(void *pcv, void *cookie) 371 { 372 #ifdef PCI_DEBUG 373 printf("footbridge_pci_intr_disestablish(pcv=%p, cookie=0x%p)\n", 374 pcv, cookie); 375 #endif 376 /* XXXX Need to free the string */ 377 footbridge_intr_disestablish(cookie); 378 } 379
Indexes created Sun Sep 28 16:09:52 GMT 2025