footbridge_pci.c revision 1.3
1 /* $NetBSD: footbridge_pci.c,v 1.3 2001/06/20 22:14:33 chris Exp $ */ 2 3 /* 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997,1998 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/conf.h> 40 #include <sys/malloc.h> 41 #include <sys/device.h> 42 43 #define _ARM32_BUS_DMA_PRIVATE 44 #include <machine/bus.h> 45 #include <machine/irqhandler.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 50 #include <arm/footbridge/dc21285reg.h> 51 #include <arm/footbridge/dc21285mem.h> 52 53 #include "isa.h" 54 #if NISA > 0 55 #include <dev/isa/isavar.h> 56 #endif 57 58 #ifdef netwinder 59 void netwinder_pci_attach_hook __P((struct device *, 60 struct device *, struct pcibus_attach_args *)); 61 #endif 62 void footbridge_pci_attach_hook __P((struct device *, 63 struct device *, struct pcibus_attach_args *)); 64 int footbridge_pci_bus_maxdevs __P((void *, int)); 65 pcitag_t footbridge_pci_make_tag __P((void *, int, int, int)); 66 void footbridge_pci_decompose_tag __P((void *, pcitag_t, int *, 67 int *, int *)); 68 pcireg_t footbridge_pci_conf_read __P((void *, pcitag_t, int)); 69 void footbridge_pci_conf_write __P((void *, pcitag_t, int, 70 pcireg_t)); 71 int footbridge_pci_intr_map __P((struct pci_attach_args *, 72 pci_intr_handle_t *)); 73 const char *footbridge_pci_intr_string __P((void *, pci_intr_handle_t)); 74 const struct evcnt *footbridge_pci_intr_evcnt __P((void *, pci_intr_handle_t)); 75 void *footbridge_pci_intr_establish __P((void *, pci_intr_handle_t, 76 int, int (*)(void *), void *)); 77 void footbridge_pci_intr_disestablish __P((void *, void *)); 78 79 80 struct arm32_pci_chipset footbridge_pci_chipset = { 81 NULL, /* conf_v */ 82 #ifdef netwinder 83 netwinder_pci_attach_hook, 84 #else 85 footbridge_pci_attach_hook, 86 #endif 87 footbridge_pci_bus_maxdevs, 88 footbridge_pci_make_tag, 89 footbridge_pci_decompose_tag, 90 footbridge_pci_conf_read, 91 footbridge_pci_conf_write, 92 NULL, /* intr_v */ 93 footbridge_pci_intr_map, 94 footbridge_pci_intr_string, 95 footbridge_pci_intr_evcnt, 96 footbridge_pci_intr_establish, 97 footbridge_pci_intr_disestablish 98 }; 99 100 /* 101 * PCI doesn't have any special needs; just use the generic versions 102 * of these functions. 103 */ 104 struct arm32_bus_dma_tag footbridge_pci_bus_dma_tag = { 105 0, 106 0, 107 _bus_dmamap_create, 108 _bus_dmamap_destroy, 109 _bus_dmamap_load, 110 _bus_dmamap_load_mbuf, 111 _bus_dmamap_load_uio, 112 _bus_dmamap_load_raw, 113 _bus_dmamap_unload, 114 _bus_dmamap_sync, 115 _bus_dmamem_alloc, 116 _bus_dmamem_free, 117 _bus_dmamem_map, 118 _bus_dmamem_unmap, 119 _bus_dmamem_mmap, 120 }; 121 122 /* 123 * Currently we only support 12 devices as we select directly in the 124 * type 0 config cycle 125 * (See conf_{read,write} for more detail 126 */ 127 #define MAX_PCI_DEVICES 21 128 129 /*static int 130 pci_intr(void *arg) 131 { 132 printf("pci int %x\n", (int)arg); 133 return(0); 134 }*/ 135 136 137 void 138 footbridge_pci_attach_hook(parent, self, pba) 139 struct device *parent, *self; 140 struct pcibus_attach_args *pba; 141 { 142 #ifdef PCI_DEBUG 143 printf("footbridge_pci_attach_hook()\n"); 144 #endif 145 146 /* intr_claim(18, IPL_NONE, "pci int 0", pci_intr, (void *)0x10000); 147 intr_claim(8, IPL_NONE, "pci int 1", pci_intr, (void *)0x10001); 148 intr_claim(9, IPL_NONE, "pci int 2", pci_intr, (void *)0x10002); 149 intr_claim(11, IPL_NONE, "pci int 3", pci_intr, (void *)0x10003);*/ 150 } 151 152 int 153 footbridge_pci_bus_maxdevs(pcv, busno) 154 void *pcv; 155 int busno; 156 { 157 #ifdef PCI_DEBUG 158 printf("footbridge_pci_bus_maxdevs(pcv=%p, busno=%d)\n", pcv, busno); 159 #endif 160 return(MAX_PCI_DEVICES); 161 } 162 163 pcitag_t 164 footbridge_pci_make_tag(pcv, bus, device, function) 165 void *pcv; 166 int bus, device, function; 167 { 168 #ifdef PCI_DEBUG 169 printf("footbridge_pci_make_tag(pcv=%p, bus=%d, device=%d, function=%d)\n", 170 pcv, bus, device, function); 171 #endif 172 return ((bus << 16) | (device << 11) | (function << 8)); 173 } 174 175 void 176 footbridge_pci_decompose_tag(pcv, tag, busp, devicep, functionp) 177 void *pcv; 178 pcitag_t tag; 179 int *busp, *devicep, *functionp; 180 { 181 #ifdef PCI_DEBUG 182 printf("footbridge_pci_decompose_tag(pcv=%p, tag=0x%08x, bp=%x, dp=%x, fp=%x)\n", 183 pcv, tag, busp, devicep, functionp); 184 #endif 185 186 if (busp != NULL) 187 *busp = (tag >> 16) & 0xff; 188 if (devicep != NULL) 189 *devicep = (tag >> 11) & 0x1f; 190 if (functionp != NULL) 191 *functionp = (tag >> 8) & 0x7; 192 } 193 194 pcireg_t 195 footbridge_pci_conf_read(pcv, tag, reg) 196 void *pcv; 197 pcitag_t tag; 198 int reg; 199 { 200 int bus, device, function; 201 u_int address; 202 pcireg_t data; 203 204 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 205 if (bus == 0) 206 /* Limited to 12 devices or we exceed type 0 config space */ 207 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 208 else 209 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 210 (bus << 16); 211 212 address |= (function << 8) | reg; 213 214 data = *((unsigned int *)address); 215 #ifdef PCI_DEBUG 216 printf("footbridge_pci_conf_read(pcv=%p tag=0x%08x reg=0x%02x)=0x%08x\n", 217 pcv, tag, reg, data); 218 #endif 219 return(data); 220 } 221 222 void 223 footbridge_pci_conf_write(pcv, tag, reg, data) 224 void *pcv; 225 pcitag_t tag; 226 int reg; 227 pcireg_t data; 228 { 229 int bus, device, function; 230 u_int address; 231 232 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 233 if (bus == 0) 234 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 235 else 236 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 237 (bus << 16); 238 239 address |= (function << 8) | reg; 240 241 #ifdef PCI_DEBUG 242 printf("footbridge_pci_conf_write(pcv=%p tag=0x%08x reg=0x%02x, 0x%08x)\n", 243 pcv, tag, reg, data); 244 #endif 245 246 *((unsigned int *)address) = data; 247 } 248 249 int 250 footbridge_pci_intr_map(pa, ihp) 251 struct pci_attach_args *pa; 252 pci_intr_handle_t *ihp; 253 { 254 int pin = pa->pa_intrpin, line = pa->pa_intrline; 255 int intr = -1; 256 257 #ifdef PCI_DEBUG 258 void *pcv = pa->pa_pc; 259 pcitag_t intrtag = pa->pa_intrtag; 260 int bus, device, function; 261 262 footbridge_pci_decompose_tag(pcv, intrtag, &bus, &device, &function); 263 printf("footbride_pci_intr_map: pcv=%p, tag=%08lx pin=%d line=%d dev=%d\n", 264 pcv, intrtag, pin, line, device); 265 #endif 266 267 /* 268 * Only the line is used to map the interrupt. 269 * The firmware is expected to setup up the interrupt 270 * line as seen from the CPU 271 * This means the firmware deals with the interrupt rotation 272 * between slots etc. 273 * 274 * Perhaps the firmware should also to the final mapping 275 * to a 21285 interrupt bit so the code below would be 276 * completely MI. 277 */ 278 279 switch (line) { 280 case PCI_INTERRUPT_PIN_NONE: 281 case 0xff: 282 /* No IRQ */ 283 printf("pci_intr_map: no mapping for pin %c\n", '@' + pin); 284 *ihp = -1; 285 return(1); 286 break; 287 #ifdef cats 288 /* This is machine dependant and needs to be moved */ 289 case PCI_INTERRUPT_PIN_A: 290 intr = IRQ_PCI; 291 break; 292 case PCI_INTERRUPT_PIN_B: 293 intr = IRQ_IN_L0; 294 break; 295 case PCI_INTERRUPT_PIN_C: 296 intr = IRQ_IN_L1; 297 break; 298 case PCI_INTERRUPT_PIN_D: 299 intr = IRQ_IN_L3; 300 break; 301 #endif 302 default: 303 /* 304 * Experimental firmware feature ... 305 * 306 * If the interrupt line is in the range 0x80 to 0x8F 307 * then the lower 4 bits indicate the ISA interrupt 308 * bit that should be used. 309 * If the interrupt line is in the range 0x40 to 0x5F 310 * then the lower 5 bits indicate the actual DC21285 311 * interrupt bit that should be used. 312 */ 313 314 if (line >= 0x40 && line <= 0x5f) 315 intr = line & 0x1f; 316 else if (line >= 0x80 && line <= 0x8f) 317 intr = line; 318 else { 319 printf("footbridge_pci_intr_map: out of range interrupt" 320 "pin %d line %d (%#x)\n", pin, line, line); 321 *ihp = -1; 322 return(1); 323 } 324 break; 325 } 326 327 #ifdef PCI_DEBUG 328 printf("pin %d, line %d mapped to int %d\n", pin, line, intr); 329 #endif 330 331 *ihp = intr; 332 return(0); 333 } 334 335 const char * 336 footbridge_pci_intr_string(pcv, ih) 337 void *pcv; 338 pci_intr_handle_t ih; 339 { 340 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 341 342 #ifdef PCI_DEBUG 343 printf("footbridge_pci_intr_string(pcv=0x%p, ih=0x%lx)\n", pcv, ih); 344 #endif 345 if (ih == 0) 346 panic("footbridge_pci_intr_string: bogus handle 0x%lx\n", ih); 347 348 #if NISA > 0 349 if (ih >= 0x80 && ih <= 0x8f) { 350 sprintf(irqstr, "isairq %ld", (ih & 0x0f)); 351 return(irqstr); 352 } 353 #endif 354 sprintf(irqstr, "irq %ld", ih); 355 return(irqstr); 356 } 357 358 const struct evcnt * 359 footbridge_pci_intr_evcnt(pcv, ih) 360 void *pcv; 361 pci_intr_handle_t ih; 362 { 363 364 /* XXX for now, no evcnt parent reported */ 365 return NULL; 366 } 367 368 void * 369 footbridge_pci_intr_establish(pcv, ih, level, func, arg) 370 void *pcv; 371 pci_intr_handle_t ih; 372 int level, (*func) __P((void *)); 373 void *arg; 374 { 375 void *intr; 376 int length; 377 char *string; 378 379 #ifdef PCI_DEBUG 380 printf("footbridge_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, func=%p, arg=%p)\n", 381 pcv, ih, level, func, arg); 382 #endif 383 384 /* Copy the interrupt string to a private buffer */ 385 length = strlen(footbridge_pci_intr_string(pcv, ih)); 386 string = malloc(length + 1, M_DEVBUF, M_WAITOK); 387 strcpy(string, footbridge_pci_intr_string(pcv, ih)); 388 #if NISA > 0 389 /* 390 * XXX the IDE driver will attach the interrupts in compat mode and 391 * thus we need to fail this here. 392 * This assumes that the interrupts are 14 and 15 which they are for 393 * IDE compat mode. 394 * Really the firmware should make this clear in the interrupt reg. 395 */ 396 if (ih >= 0x80 && ih <= 0x8d) { 397 intr = isa_intr_establish(NULL, (ih & 0x0f), IST_EDGE, 398 level, func, arg); 399 } else 400 #endif 401 intr = intr_claim(ih, level, string, func, arg); 402 403 return(intr); 404 } 405 406 void 407 footbridge_pci_intr_disestablish(pcv, cookie) 408 void *pcv; 409 void *cookie; 410 { 411 #ifdef PCI_DEBUG 412 printf("footbridge_pci_intr_disestablish(pcv=%p, cookie=0x%x)\n", 413 pcv, cookie); 414 #endif 415 /* XXXX Need to free the string */ 416 417 intr_release(cookie); 418 } 419
Indexes created Mon Sep 29 03:10:08 GMT 2025