footbridge_pci.c revision 1.6
1 /* $NetBSD: footbridge_pci.c,v 1.6 2002/09/27 15:35:44 provos Exp $ */ 2 3 /* 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997,1998 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/conf.h> 40 #include <sys/malloc.h> 41 #include <sys/device.h> 42 43 #define _ARM32_BUS_DMA_PRIVATE 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 50 #include <arm/footbridge/dc21285reg.h> 51 #include <arm/footbridge/dc21285mem.h> 52 53 #include "isa.h" 54 #if NISA > 0 55 #include <dev/isa/isavar.h> 56 #endif 57 58 #ifdef netwinder 59 void netwinder_pci_attach_hook __P((struct device *, 60 struct device *, struct pcibus_attach_args *)); 61 #endif 62 void footbridge_pci_attach_hook __P((struct device *, 63 struct device *, struct pcibus_attach_args *)); 64 int footbridge_pci_bus_maxdevs __P((void *, int)); 65 pcitag_t footbridge_pci_make_tag __P((void *, int, int, int)); 66 void footbridge_pci_decompose_tag __P((void *, pcitag_t, int *, 67 int *, int *)); 68 pcireg_t footbridge_pci_conf_read __P((void *, pcitag_t, int)); 69 void footbridge_pci_conf_write __P((void *, pcitag_t, int, 70 pcireg_t)); 71 int footbridge_pci_intr_map __P((struct pci_attach_args *, 72 pci_intr_handle_t *)); 73 const char *footbridge_pci_intr_string __P((void *, pci_intr_handle_t)); 74 const struct evcnt *footbridge_pci_intr_evcnt __P((void *, pci_intr_handle_t)); 75 void *footbridge_pci_intr_establish __P((void *, pci_intr_handle_t, 76 int, int (*)(void *), void *)); 77 void footbridge_pci_intr_disestablish __P((void *, void *)); 78 79 80 struct arm32_pci_chipset footbridge_pci_chipset = { 81 NULL, /* conf_v */ 82 #ifdef netwinder 83 netwinder_pci_attach_hook, 84 #else 85 footbridge_pci_attach_hook, 86 #endif 87 footbridge_pci_bus_maxdevs, 88 footbridge_pci_make_tag, 89 footbridge_pci_decompose_tag, 90 footbridge_pci_conf_read, 91 footbridge_pci_conf_write, 92 NULL, /* intr_v */ 93 footbridge_pci_intr_map, 94 footbridge_pci_intr_string, 95 footbridge_pci_intr_evcnt, 96 footbridge_pci_intr_establish, 97 footbridge_pci_intr_disestablish 98 }; 99 100 /* 101 * PCI doesn't have any special needs; just use the generic versions 102 * of these functions. 103 */ 104 struct arm32_bus_dma_tag footbridge_pci_bus_dma_tag = { 105 0, 106 0, 107 _bus_dmamap_create, 108 _bus_dmamap_destroy, 109 _bus_dmamap_load, 110 _bus_dmamap_load_mbuf, 111 _bus_dmamap_load_uio, 112 _bus_dmamap_load_raw, 113 _bus_dmamap_unload, 114 _bus_dmamap_sync, /* pre */ 115 NULL, /* post */ 116 _bus_dmamem_alloc, 117 _bus_dmamem_free, 118 _bus_dmamem_map, 119 _bus_dmamem_unmap, 120 _bus_dmamem_mmap, 121 }; 122 123 /* 124 * Currently we only support 12 devices as we select directly in the 125 * type 0 config cycle 126 * (See conf_{read,write} for more detail 127 */ 128 #define MAX_PCI_DEVICES 21 129 130 /*static int 131 pci_intr(void *arg) 132 { 133 printf("pci int %x\n", (int)arg); 134 return(0); 135 }*/ 136 137 138 void 139 footbridge_pci_attach_hook(parent, self, pba) 140 struct device *parent, *self; 141 struct pcibus_attach_args *pba; 142 { 143 #ifdef PCI_DEBUG 144 printf("footbridge_pci_attach_hook()\n"); 145 #endif 146 147 /* intr_claim(18, IPL_NONE, "pci int 0", pci_intr, (void *)0x10000); 148 intr_claim(8, IPL_NONE, "pci int 1", pci_intr, (void *)0x10001); 149 intr_claim(9, IPL_NONE, "pci int 2", pci_intr, (void *)0x10002); 150 intr_claim(11, IPL_NONE, "pci int 3", pci_intr, (void *)0x10003);*/ 151 } 152 153 int 154 footbridge_pci_bus_maxdevs(pcv, busno) 155 void *pcv; 156 int busno; 157 { 158 #ifdef PCI_DEBUG 159 printf("footbridge_pci_bus_maxdevs(pcv=%p, busno=%d)\n", pcv, busno); 160 #endif 161 return(MAX_PCI_DEVICES); 162 } 163 164 pcitag_t 165 footbridge_pci_make_tag(pcv, bus, device, function) 166 void *pcv; 167 int bus, device, function; 168 { 169 #ifdef PCI_DEBUG 170 printf("footbridge_pci_make_tag(pcv=%p, bus=%d, device=%d, function=%d)\n", 171 pcv, bus, device, function); 172 #endif 173 return ((bus << 16) | (device << 11) | (function << 8)); 174 } 175 176 void 177 footbridge_pci_decompose_tag(pcv, tag, busp, devicep, functionp) 178 void *pcv; 179 pcitag_t tag; 180 int *busp, *devicep, *functionp; 181 { 182 #ifdef PCI_DEBUG 183 printf("footbridge_pci_decompose_tag(pcv=%p, tag=0x%08x, bp=%x, dp=%x, fp=%x)\n", 184 pcv, tag, busp, devicep, functionp); 185 #endif 186 187 if (busp != NULL) 188 *busp = (tag >> 16) & 0xff; 189 if (devicep != NULL) 190 *devicep = (tag >> 11) & 0x1f; 191 if (functionp != NULL) 192 *functionp = (tag >> 8) & 0x7; 193 } 194 195 pcireg_t 196 footbridge_pci_conf_read(pcv, tag, reg) 197 void *pcv; 198 pcitag_t tag; 199 int reg; 200 { 201 int bus, device, function; 202 u_int address; 203 pcireg_t data; 204 205 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 206 if (bus == 0) 207 /* Limited to 12 devices or we exceed type 0 config space */ 208 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 209 else 210 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 211 (bus << 16); 212 213 address |= (function << 8) | reg; 214 215 data = *((unsigned int *)address); 216 #ifdef PCI_DEBUG 217 printf("footbridge_pci_conf_read(pcv=%p tag=0x%08x reg=0x%02x)=0x%08x\n", 218 pcv, tag, reg, data); 219 #endif 220 return(data); 221 } 222 223 void 224 footbridge_pci_conf_write(pcv, tag, reg, data) 225 void *pcv; 226 pcitag_t tag; 227 int reg; 228 pcireg_t data; 229 { 230 int bus, device, function; 231 u_int address; 232 233 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 234 if (bus == 0) 235 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 236 else 237 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 238 (bus << 16); 239 240 address |= (function << 8) | reg; 241 242 #ifdef PCI_DEBUG 243 printf("footbridge_pci_conf_write(pcv=%p tag=0x%08x reg=0x%02x, 0x%08x)\n", 244 pcv, tag, reg, data); 245 #endif 246 247 *((unsigned int *)address) = data; 248 } 249 250 int 251 footbridge_pci_intr_map(pa, ihp) 252 struct pci_attach_args *pa; 253 pci_intr_handle_t *ihp; 254 { 255 int pin = pa->pa_intrpin, line = pa->pa_intrline; 256 int intr = -1; 257 258 #ifdef PCI_DEBUG 259 void *pcv = pa->pa_pc; 260 pcitag_t intrtag = pa->pa_intrtag; 261 int bus, device, function; 262 263 footbridge_pci_decompose_tag(pcv, intrtag, &bus, &device, &function); 264 printf("footbride_pci_intr_map: pcv=%p, tag=%08lx pin=%d line=%d dev=%d\n", 265 pcv, intrtag, pin, line, device); 266 #endif 267 268 /* 269 * Only the line is used to map the interrupt. 270 * The firmware is expected to setup up the interrupt 271 * line as seen from the CPU 272 * This means the firmware deals with the interrupt rotation 273 * between slots etc. 274 * 275 * Perhaps the firmware should also to the final mapping 276 * to a 21285 interrupt bit so the code below would be 277 * completely MI. 278 */ 279 280 switch (line) { 281 case PCI_INTERRUPT_PIN_NONE: 282 case 0xff: 283 /* No IRQ */ 284 printf("pci_intr_map: no mapping for pin %c\n", '@' + pin); 285 *ihp = -1; 286 return(1); 287 break; 288 #ifdef cats 289 /* This is machine dependant and needs to be moved */ 290 case PCI_INTERRUPT_PIN_A: 291 intr = IRQ_PCI; 292 break; 293 case PCI_INTERRUPT_PIN_B: 294 intr = IRQ_IN_L0; 295 break; 296 case PCI_INTERRUPT_PIN_C: 297 intr = IRQ_IN_L1; 298 break; 299 case PCI_INTERRUPT_PIN_D: 300 intr = IRQ_IN_L3; 301 break; 302 #endif 303 default: 304 /* 305 * Experimental firmware feature ... 306 * 307 * If the interrupt line is in the range 0x80 to 0x8F 308 * then the lower 4 bits indicate the ISA interrupt 309 * bit that should be used. 310 * If the interrupt line is in the range 0x40 to 0x5F 311 * then the lower 5 bits indicate the actual DC21285 312 * interrupt bit that should be used. 313 */ 314 315 if (line >= 0x40 && line <= 0x5f) 316 intr = line & 0x1f; 317 else if (line >= 0x80 && line <= 0x8f) 318 intr = line; 319 else { 320 printf("footbridge_pci_intr_map: out of range interrupt" 321 "pin %d line %d (%#x)\n", pin, line, line); 322 *ihp = -1; 323 return(1); 324 } 325 break; 326 } 327 328 #ifdef PCI_DEBUG 329 printf("pin %d, line %d mapped to int %d\n", pin, line, intr); 330 #endif 331 332 *ihp = intr; 333 return(0); 334 } 335 336 const char * 337 footbridge_pci_intr_string(pcv, ih) 338 void *pcv; 339 pci_intr_handle_t ih; 340 { 341 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 342 343 #ifdef PCI_DEBUG 344 printf("footbridge_pci_intr_string(pcv=0x%p, ih=0x%lx)\n", pcv, ih); 345 #endif 346 if (ih == 0) 347 panic("footbridge_pci_intr_string: bogus handle 0x%lx", ih); 348 349 #if NISA > 0 350 if (ih >= 0x80 && ih <= 0x8f) { 351 sprintf(irqstr, "isairq %ld", (ih & 0x0f)); 352 return(irqstr); 353 } 354 #endif 355 sprintf(irqstr, "irq %ld", ih); 356 return(irqstr); 357 } 358 359 const struct evcnt * 360 footbridge_pci_intr_evcnt(pcv, ih) 361 void *pcv; 362 pci_intr_handle_t ih; 363 { 364 365 /* XXX for now, no evcnt parent reported */ 366 return NULL; 367 } 368 369 void * 370 footbridge_pci_intr_establish(pcv, ih, level, func, arg) 371 void *pcv; 372 pci_intr_handle_t ih; 373 int level, (*func) __P((void *)); 374 void *arg; 375 { 376 void *intr; 377 int length; 378 char *string; 379 380 #ifdef PCI_DEBUG 381 printf("footbridge_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, func=%p, arg=%p)\n", 382 pcv, ih, level, func, arg); 383 #endif 384 385 /* Copy the interrupt string to a private buffer */ 386 length = strlen(footbridge_pci_intr_string(pcv, ih)); 387 string = malloc(length + 1, M_DEVBUF, M_WAITOK); 388 strcpy(string, footbridge_pci_intr_string(pcv, ih)); 389 #if NISA > 0 390 /* 391 * XXX the IDE driver will attach the interrupts in compat mode and 392 * thus we need to fail this here. 393 * This assumes that the interrupts are 14 and 15 which they are for 394 * IDE compat mode. 395 * Really the firmware should make this clear in the interrupt reg. 396 */ 397 if (ih >= 0x80 && ih <= 0x8d) { 398 intr = isa_intr_establish(NULL, (ih & 0x0f), IST_EDGE, 399 level, func, arg); 400 } else 401 #endif 402 intr = intr_claim(ih, level, string, func, arg); 403 404 return(intr); 405 } 406 407 void 408 footbridge_pci_intr_disestablish(pcv, cookie) 409 void *pcv; 410 void *cookie; 411 { 412 #ifdef PCI_DEBUG 413 printf("footbridge_pci_intr_disestablish(pcv=%p, cookie=0x%x)\n", 414 pcv, cookie); 415 #endif 416 /* XXXX Need to free the string */ 417 418 intr_release(cookie); 419 } 420
Indexes created Mon Sep 29 03:10:08 GMT 2025