footbridge_pci.c revision 1.8
1 /* $NetBSD: footbridge_pci.c,v 1.8 2002/11/03 21:43:31 chris Exp $ */ 2 3 /* 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997,1998 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/conf.h> 40 #include <sys/malloc.h> 41 #include <sys/device.h> 42 43 #define _ARM32_BUS_DMA_PRIVATE 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 47 #include <dev/pci/pcireg.h> 48 #include <dev/pci/pcivar.h> 49 50 #include <arm/footbridge/dc21285reg.h> 51 #include <arm/footbridge/dc21285mem.h> 52 53 #include "isa.h" 54 #if NISA > 0 55 #include <dev/isa/isavar.h> 56 #endif 57 58 void footbridge_pci_attach_hook __P((struct device *, 59 struct device *, struct pcibus_attach_args *)); 60 int footbridge_pci_bus_maxdevs __P((void *, int)); 61 pcitag_t footbridge_pci_make_tag __P((void *, int, int, int)); 62 void footbridge_pci_decompose_tag __P((void *, pcitag_t, int *, 63 int *, int *)); 64 pcireg_t footbridge_pci_conf_read __P((void *, pcitag_t, int)); 65 void footbridge_pci_conf_write __P((void *, pcitag_t, int, 66 pcireg_t)); 67 int footbridge_pci_intr_map __P((struct pci_attach_args *, 68 pci_intr_handle_t *)); 69 const char *footbridge_pci_intr_string __P((void *, pci_intr_handle_t)); 70 void *footbridge_pci_intr_establish __P((void *, pci_intr_handle_t, 71 int, int (*)(void *), void *)); 72 void footbridge_pci_intr_disestablish __P((void *, void *)); 73 const struct evcnt *footbridge_pci_intr_evcnt __P((void *, pci_intr_handle_t)); 74 75 struct arm32_pci_chipset footbridge_pci_chipset = { 76 NULL, /* conf_v */ 77 #ifdef netwinder 78 netwinder_pci_attach_hook, 79 #else 80 footbridge_pci_attach_hook, 81 #endif 82 footbridge_pci_bus_maxdevs, 83 footbridge_pci_make_tag, 84 footbridge_pci_decompose_tag, 85 footbridge_pci_conf_read, 86 footbridge_pci_conf_write, 87 NULL, /* intr_v */ 88 footbridge_pci_intr_map, 89 footbridge_pci_intr_string, 90 footbridge_pci_intr_evcnt, 91 footbridge_pci_intr_establish, 92 footbridge_pci_intr_disestablish 93 }; 94 95 /* 96 * PCI doesn't have any special needs; just use the generic versions 97 * of these functions. 98 */ 99 struct arm32_bus_dma_tag footbridge_pci_bus_dma_tag = { 100 0, 101 0, 102 _bus_dmamap_create, 103 _bus_dmamap_destroy, 104 _bus_dmamap_load, 105 _bus_dmamap_load_mbuf, 106 _bus_dmamap_load_uio, 107 _bus_dmamap_load_raw, 108 _bus_dmamap_unload, 109 _bus_dmamap_sync, /* pre */ 110 NULL, /* post */ 111 _bus_dmamem_alloc, 112 _bus_dmamem_free, 113 _bus_dmamem_map, 114 _bus_dmamem_unmap, 115 _bus_dmamem_mmap, 116 }; 117 118 /* 119 * Currently we only support 12 devices as we select directly in the 120 * type 0 config cycle 121 * (See conf_{read,write} for more detail 122 */ 123 #define MAX_PCI_DEVICES 21 124 125 /*static int 126 pci_intr(void *arg) 127 { 128 printf("pci int %x\n", (int)arg); 129 return(0); 130 }*/ 131 132 133 void 134 footbridge_pci_attach_hook(parent, self, pba) 135 struct device *parent, *self; 136 struct pcibus_attach_args *pba; 137 { 138 #ifdef PCI_DEBUG 139 printf("footbridge_pci_attach_hook()\n"); 140 #endif 141 142 /* intr_claim(18, IPL_NONE, "pci int 0", pci_intr, (void *)0x10000); 143 intr_claim(8, IPL_NONE, "pci int 1", pci_intr, (void *)0x10001); 144 intr_claim(9, IPL_NONE, "pci int 2", pci_intr, (void *)0x10002); 145 intr_claim(11, IPL_NONE, "pci int 3", pci_intr, (void *)0x10003);*/ 146 } 147 148 int 149 footbridge_pci_bus_maxdevs(pcv, busno) 150 void *pcv; 151 int busno; 152 { 153 #ifdef PCI_DEBUG 154 printf("footbridge_pci_bus_maxdevs(pcv=%p, busno=%d)\n", pcv, busno); 155 #endif 156 return(MAX_PCI_DEVICES); 157 } 158 159 pcitag_t 160 footbridge_pci_make_tag(pcv, bus, device, function) 161 void *pcv; 162 int bus, device, function; 163 { 164 #ifdef PCI_DEBUG 165 printf("footbridge_pci_make_tag(pcv=%p, bus=%d, device=%d, function=%d)\n", 166 pcv, bus, device, function); 167 #endif 168 return ((bus << 16) | (device << 11) | (function << 8)); 169 } 170 171 void 172 footbridge_pci_decompose_tag(pcv, tag, busp, devicep, functionp) 173 void *pcv; 174 pcitag_t tag; 175 int *busp, *devicep, *functionp; 176 { 177 #ifdef PCI_DEBUG 178 printf("footbridge_pci_decompose_tag(pcv=%p, tag=0x%08x, bp=%x, dp=%x, fp=%x)\n", 179 pcv, tag, busp, devicep, functionp); 180 #endif 181 182 if (busp != NULL) 183 *busp = (tag >> 16) & 0xff; 184 if (devicep != NULL) 185 *devicep = (tag >> 11) & 0x1f; 186 if (functionp != NULL) 187 *functionp = (tag >> 8) & 0x7; 188 } 189 190 pcireg_t 191 footbridge_pci_conf_read(pcv, tag, reg) 192 void *pcv; 193 pcitag_t tag; 194 int reg; 195 { 196 int bus, device, function; 197 u_int address; 198 pcireg_t data; 199 200 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 201 if (bus == 0) 202 /* Limited to 12 devices or we exceed type 0 config space */ 203 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 204 else 205 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 206 (bus << 16); 207 208 address |= (function << 8) | reg; 209 210 data = *((unsigned int *)address); 211 #ifdef PCI_DEBUG 212 printf("footbridge_pci_conf_read(pcv=%p tag=0x%08x reg=0x%02x)=0x%08x\n", 213 pcv, tag, reg, data); 214 #endif 215 return(data); 216 } 217 218 void 219 footbridge_pci_conf_write(pcv, tag, reg, data) 220 void *pcv; 221 pcitag_t tag; 222 int reg; 223 pcireg_t data; 224 { 225 int bus, device, function; 226 u_int address; 227 228 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 229 if (bus == 0) 230 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 231 else 232 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 233 (bus << 16); 234 235 address |= (function << 8) | reg; 236 237 #ifdef PCI_DEBUG 238 printf("footbridge_pci_conf_write(pcv=%p tag=0x%08x reg=0x%02x, 0x%08x)\n", 239 pcv, tag, reg, data); 240 #endif 241 242 *((unsigned int *)address) = data; 243 } 244 245 int 246 footbridge_pci_intr_map(pa, ihp) 247 struct pci_attach_args *pa; 248 pci_intr_handle_t *ihp; 249 { 250 int pin = pa->pa_intrpin, line = pa->pa_intrline; 251 int intr = -1; 252 253 #ifdef PCI_DEBUG 254 void *pcv = pa->pa_pc; 255 pcitag_t intrtag = pa->pa_intrtag; 256 int bus, device, function; 257 258 footbridge_pci_decompose_tag(pcv, intrtag, &bus, &device, &function); 259 printf("footbride_pci_intr_map: pcv=%p, tag=%08lx pin=%d line=%d dev=%d\n", 260 pcv, intrtag, pin, line, device); 261 #endif 262 263 /* 264 * Only the line is used to map the interrupt. 265 * The firmware is expected to setup up the interrupt 266 * line as seen from the CPU 267 * This means the firmware deals with the interrupt rotation 268 * between slots etc. 269 * 270 * Perhaps the firmware should also to the final mapping 271 * to a 21285 interrupt bit so the code below would be 272 * completely MI. 273 */ 274 275 switch (line) { 276 case PCI_INTERRUPT_PIN_NONE: 277 case 0xff: 278 /* No IRQ */ 279 printf("pci_intr_map: no mapping for pin %c\n", '@' + pin); 280 *ihp = -1; 281 return(1); 282 break; 283 #ifdef cats 284 /* This is machine dependant and needs to be moved */ 285 case PCI_INTERRUPT_PIN_A: 286 intr = IRQ_PCI; 287 break; 288 case PCI_INTERRUPT_PIN_B: 289 intr = IRQ_IN_L0; 290 break; 291 case PCI_INTERRUPT_PIN_C: 292 intr = IRQ_IN_L1; 293 break; 294 case PCI_INTERRUPT_PIN_D: 295 intr = IRQ_IN_L3; 296 break; 297 #endif 298 default: 299 /* 300 * Experimental firmware feature ... 301 * 302 * If the interrupt line is in the range 0x80 to 0x8F 303 * then the lower 4 bits indicate the ISA interrupt 304 * bit that should be used. 305 * If the interrupt line is in the range 0x40 to 0x5F 306 * then the lower 5 bits indicate the actual DC21285 307 * interrupt bit that should be used. 308 */ 309 310 if (line >= 0x40 && line <= 0x5f) 311 intr = line & 0x1f; 312 else if (line >= 0x80 && line <= 0x8f) 313 intr = line; 314 else { 315 printf("footbridge_pci_intr_map: out of range interrupt" 316 "pin %d line %d (%#x)\n", pin, line, line); 317 *ihp = -1; 318 return(1); 319 } 320 break; 321 } 322 323 #ifdef PCI_DEBUG 324 printf("pin %d, line %d mapped to int %d\n", pin, line, intr); 325 #endif 326 327 *ihp = intr; 328 return(0); 329 } 330 331 const char * 332 footbridge_pci_intr_string(pcv, ih) 333 void *pcv; 334 pci_intr_handle_t ih; 335 { 336 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 337 338 #ifdef PCI_DEBUG 339 printf("footbridge_pci_intr_string(pcv=0x%p, ih=0x%lx)\n", pcv, ih); 340 #endif 341 if (ih == 0) 342 panic("footbridge_pci_intr_string: bogus handle 0x%lx", ih); 343 344 #if NISA > 0 345 if (ih >= 0x80 && ih <= 0x8f) { 346 sprintf(irqstr, "isairq %ld", (ih & 0x0f)); 347 return(irqstr); 348 } 349 #endif 350 sprintf(irqstr, "irq %ld", ih); 351 return(irqstr); 352 } 353 354 void * 355 footbridge_pci_intr_establish(pcv, ih, level, func, arg) 356 void *pcv; 357 pci_intr_handle_t ih; 358 int level, (*func) __P((void *)); 359 void *arg; 360 { 361 void *intr; 362 int length; 363 char *string; 364 365 #ifdef PCI_DEBUG 366 printf("footbridge_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, func=%p, arg=%p)\n", 367 pcv, ih, level, func, arg); 368 #endif 369 370 /* Copy the interrupt string to a private buffer */ 371 length = strlen(footbridge_pci_intr_string(pcv, ih)); 372 string = malloc(length + 1, M_DEVBUF, M_WAITOK); 373 strcpy(string, footbridge_pci_intr_string(pcv, ih)); 374 #if NISA > 0 375 /* 376 * XXX the IDE driver will attach the interrupts in compat mode and 377 * thus we need to fail this here. 378 * This assumes that the interrupts are 14 and 15 which they are for 379 * IDE compat mode. 380 * Really the firmware should make this clear in the interrupt reg. 381 */ 382 if (ih >= 0x80 && ih <= 0x8d) { 383 intr = isa_intr_establish(NULL, (ih & 0x0f), IST_EDGE, 384 level, func, arg); 385 } else 386 #endif 387 intr = footbridge_intr_claim(ih, level, string, func, arg); 388 389 return(intr); 390 } 391 392 void 393 footbridge_pci_intr_disestablish(pcv, cookie) 394 void *pcv; 395 void *cookie; 396 { 397 #ifdef PCI_DEBUG 398 printf("footbridge_pci_intr_disestablish(pcv=%p, cookie=0x%x)\n", 399 pcv, cookie); 400 #endif 401 /* XXXX Need to free the string */ 402 footbridge_intr_disestablish(cookie); 403 } 404
Indexes created Mon Sep 29 21:09:56 GMT 2025