footbridge_pci.c revision 1.9
1 /* $NetBSD: footbridge_pci.c,v 1.9 2003/03/23 14:12:25 chris Exp $ */ 2 3 /* 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997,1998 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe 19 * for the NetBSD Project. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: footbridge_pci.c,v 1.9 2003/03/23 14:12:25 chris Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/conf.h> 43 #include <sys/malloc.h> 44 #include <sys/device.h> 45 46 #define _ARM32_BUS_DMA_PRIVATE 47 #include <machine/bus.h> 48 #include <machine/intr.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 #include <arm/footbridge/dc21285reg.h> 54 #include <arm/footbridge/dc21285mem.h> 55 56 #include "isa.h" 57 #if NISA > 0 58 #include <dev/isa/isavar.h> 59 #endif 60 61 void footbridge_pci_attach_hook __P((struct device *, 62 struct device *, struct pcibus_attach_args *)); 63 int footbridge_pci_bus_maxdevs __P((void *, int)); 64 pcitag_t footbridge_pci_make_tag __P((void *, int, int, int)); 65 void footbridge_pci_decompose_tag __P((void *, pcitag_t, int *, 66 int *, int *)); 67 pcireg_t footbridge_pci_conf_read __P((void *, pcitag_t, int)); 68 void footbridge_pci_conf_write __P((void *, pcitag_t, int, 69 pcireg_t)); 70 int footbridge_pci_intr_map __P((struct pci_attach_args *, 71 pci_intr_handle_t *)); 72 const char *footbridge_pci_intr_string __P((void *, pci_intr_handle_t)); 73 void *footbridge_pci_intr_establish __P((void *, pci_intr_handle_t, 74 int, int (*)(void *), void *)); 75 void footbridge_pci_intr_disestablish __P((void *, void *)); 76 const struct evcnt *footbridge_pci_intr_evcnt __P((void *, pci_intr_handle_t)); 77 78 struct arm32_pci_chipset footbridge_pci_chipset = { 79 NULL, /* conf_v */ 80 #ifdef netwinder 81 netwinder_pci_attach_hook, 82 #else 83 footbridge_pci_attach_hook, 84 #endif 85 footbridge_pci_bus_maxdevs, 86 footbridge_pci_make_tag, 87 footbridge_pci_decompose_tag, 88 footbridge_pci_conf_read, 89 footbridge_pci_conf_write, 90 NULL, /* intr_v */ 91 footbridge_pci_intr_map, 92 footbridge_pci_intr_string, 93 footbridge_pci_intr_evcnt, 94 footbridge_pci_intr_establish, 95 footbridge_pci_intr_disestablish 96 }; 97 98 /* 99 * PCI doesn't have any special needs; just use the generic versions 100 * of these functions. 101 */ 102 struct arm32_bus_dma_tag footbridge_pci_bus_dma_tag = { 103 0, 104 0, 105 _bus_dmamap_create, 106 _bus_dmamap_destroy, 107 _bus_dmamap_load, 108 _bus_dmamap_load_mbuf, 109 _bus_dmamap_load_uio, 110 _bus_dmamap_load_raw, 111 _bus_dmamap_unload, 112 _bus_dmamap_sync, /* pre */ 113 NULL, /* post */ 114 _bus_dmamem_alloc, 115 _bus_dmamem_free, 116 _bus_dmamem_map, 117 _bus_dmamem_unmap, 118 _bus_dmamem_mmap, 119 }; 120 121 /* 122 * Currently we only support 12 devices as we select directly in the 123 * type 0 config cycle 124 * (See conf_{read,write} for more detail 125 */ 126 #define MAX_PCI_DEVICES 21 127 128 /*static int 129 pci_intr(void *arg) 130 { 131 printf("pci int %x\n", (int)arg); 132 return(0); 133 }*/ 134 135 136 void 137 footbridge_pci_attach_hook(parent, self, pba) 138 struct device *parent, *self; 139 struct pcibus_attach_args *pba; 140 { 141 #ifdef PCI_DEBUG 142 printf("footbridge_pci_attach_hook()\n"); 143 #endif 144 145 /* intr_claim(18, IPL_NONE, "pci int 0", pci_intr, (void *)0x10000); 146 intr_claim(8, IPL_NONE, "pci int 1", pci_intr, (void *)0x10001); 147 intr_claim(9, IPL_NONE, "pci int 2", pci_intr, (void *)0x10002); 148 intr_claim(11, IPL_NONE, "pci int 3", pci_intr, (void *)0x10003);*/ 149 } 150 151 int 152 footbridge_pci_bus_maxdevs(pcv, busno) 153 void *pcv; 154 int busno; 155 { 156 #ifdef PCI_DEBUG 157 printf("footbridge_pci_bus_maxdevs(pcv=%p, busno=%d)\n", pcv, busno); 158 #endif 159 return(MAX_PCI_DEVICES); 160 } 161 162 pcitag_t 163 footbridge_pci_make_tag(pcv, bus, device, function) 164 void *pcv; 165 int bus, device, function; 166 { 167 #ifdef PCI_DEBUG 168 printf("footbridge_pci_make_tag(pcv=%p, bus=%d, device=%d, function=%d)\n", 169 pcv, bus, device, function); 170 #endif 171 return ((bus << 16) | (device << 11) | (function << 8)); 172 } 173 174 void 175 footbridge_pci_decompose_tag(pcv, tag, busp, devicep, functionp) 176 void *pcv; 177 pcitag_t tag; 178 int *busp, *devicep, *functionp; 179 { 180 #ifdef PCI_DEBUG 181 printf("footbridge_pci_decompose_tag(pcv=%p, tag=0x%08x, bp=%x, dp=%x, fp=%x)\n", 182 pcv, tag, busp, devicep, functionp); 183 #endif 184 185 if (busp != NULL) 186 *busp = (tag >> 16) & 0xff; 187 if (devicep != NULL) 188 *devicep = (tag >> 11) & 0x1f; 189 if (functionp != NULL) 190 *functionp = (tag >> 8) & 0x7; 191 } 192 193 pcireg_t 194 footbridge_pci_conf_read(pcv, tag, reg) 195 void *pcv; 196 pcitag_t tag; 197 int reg; 198 { 199 int bus, device, function; 200 u_int address; 201 pcireg_t data; 202 203 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 204 if (bus == 0) 205 /* Limited to 12 devices or we exceed type 0 config space */ 206 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 207 else 208 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 209 (bus << 16); 210 211 address |= (function << 8) | reg; 212 213 data = *((unsigned int *)address); 214 #ifdef PCI_DEBUG 215 printf("footbridge_pci_conf_read(pcv=%p tag=0x%08x reg=0x%02x)=0x%08x\n", 216 pcv, tag, reg, data); 217 #endif 218 return(data); 219 } 220 221 void 222 footbridge_pci_conf_write(pcv, tag, reg, data) 223 void *pcv; 224 pcitag_t tag; 225 int reg; 226 pcireg_t data; 227 { 228 int bus, device, function; 229 u_int address; 230 231 footbridge_pci_decompose_tag(pcv, tag, &bus, &device, &function); 232 if (bus == 0) 233 address = DC21285_PCI_TYPE_0_CONFIG_VBASE | (3 << 22) | (device << 11); 234 else 235 address = DC21285_PCI_TYPE_1_CONFIG_VBASE | (device << 11) | 236 (bus << 16); 237 238 address |= (function << 8) | reg; 239 240 #ifdef PCI_DEBUG 241 printf("footbridge_pci_conf_write(pcv=%p tag=0x%08x reg=0x%02x, 0x%08x)\n", 242 pcv, tag, reg, data); 243 #endif 244 245 *((unsigned int *)address) = data; 246 } 247 248 int 249 footbridge_pci_intr_map(pa, ihp) 250 struct pci_attach_args *pa; 251 pci_intr_handle_t *ihp; 252 { 253 int pin = pa->pa_intrpin, line = pa->pa_intrline; 254 int intr = -1; 255 256 #ifdef PCI_DEBUG 257 void *pcv = pa->pa_pc; 258 pcitag_t intrtag = pa->pa_intrtag; 259 int bus, device, function; 260 261 footbridge_pci_decompose_tag(pcv, intrtag, &bus, &device, &function); 262 printf("footbride_pci_intr_map: pcv=%p, tag=%08lx pin=%d line=%d dev=%d\n", 263 pcv, intrtag, pin, line, device); 264 #endif 265 266 /* 267 * Only the line is used to map the interrupt. 268 * The firmware is expected to setup up the interrupt 269 * line as seen from the CPU 270 * This means the firmware deals with the interrupt rotation 271 * between slots etc. 272 * 273 * Perhaps the firmware should also to the final mapping 274 * to a 21285 interrupt bit so the code below would be 275 * completely MI. 276 */ 277 278 switch (line) { 279 case PCI_INTERRUPT_PIN_NONE: 280 case 0xff: 281 /* No IRQ */ 282 printf("pci_intr_map: no mapping for pin %c\n", '@' + pin); 283 *ihp = -1; 284 return(1); 285 break; 286 #ifdef cats 287 /* This is machine dependant and needs to be moved */ 288 case PCI_INTERRUPT_PIN_A: 289 intr = IRQ_PCI; 290 break; 291 case PCI_INTERRUPT_PIN_B: 292 intr = IRQ_IN_L0; 293 break; 294 case PCI_INTERRUPT_PIN_C: 295 intr = IRQ_IN_L1; 296 break; 297 case PCI_INTERRUPT_PIN_D: 298 intr = IRQ_IN_L3; 299 break; 300 #endif 301 default: 302 /* 303 * Experimental firmware feature ... 304 * 305 * If the interrupt line is in the range 0x80 to 0x8F 306 * then the lower 4 bits indicate the ISA interrupt 307 * bit that should be used. 308 * If the interrupt line is in the range 0x40 to 0x5F 309 * then the lower 5 bits indicate the actual DC21285 310 * interrupt bit that should be used. 311 */ 312 313 if (line >= 0x40 && line <= 0x5f) 314 intr = line & 0x1f; 315 else if (line >= 0x80 && line <= 0x8f) 316 intr = line; 317 else { 318 printf("footbridge_pci_intr_map: out of range interrupt" 319 "pin %d line %d (%#x)\n", pin, line, line); 320 *ihp = -1; 321 return(1); 322 } 323 break; 324 } 325 326 #ifdef PCI_DEBUG 327 printf("pin %d, line %d mapped to int %d\n", pin, line, intr); 328 #endif 329 330 *ihp = intr; 331 return(0); 332 } 333 334 const char * 335 footbridge_pci_intr_string(pcv, ih) 336 void *pcv; 337 pci_intr_handle_t ih; 338 { 339 static char irqstr[8]; /* 4 + 2 + NULL + sanity */ 340 341 #ifdef PCI_DEBUG 342 printf("footbridge_pci_intr_string(pcv=0x%p, ih=0x%lx)\n", pcv, ih); 343 #endif 344 if (ih == 0) 345 panic("footbridge_pci_intr_string: bogus handle 0x%lx", ih); 346 347 #if NISA > 0 348 if (ih >= 0x80 && ih <= 0x8f) { 349 sprintf(irqstr, "isairq %ld", (ih & 0x0f)); 350 return(irqstr); 351 } 352 #endif 353 sprintf(irqstr, "irq %ld", ih); 354 return(irqstr); 355 } 356 357 void * 358 footbridge_pci_intr_establish(pcv, ih, level, func, arg) 359 void *pcv; 360 pci_intr_handle_t ih; 361 int level, (*func) __P((void *)); 362 void *arg; 363 { 364 void *intr; 365 int length; 366 char *string; 367 368 #ifdef PCI_DEBUG 369 printf("footbridge_pci_intr_establish(pcv=%p, ih=0x%lx, level=%d, func=%p, arg=%p)\n", 370 pcv, ih, level, func, arg); 371 #endif 372 373 /* Copy the interrupt string to a private buffer */ 374 length = strlen(footbridge_pci_intr_string(pcv, ih)); 375 string = malloc(length + 1, M_DEVBUF, M_WAITOK); 376 strcpy(string, footbridge_pci_intr_string(pcv, ih)); 377 #if NISA > 0 378 /* 379 * XXX the IDE driver will attach the interrupts in compat mode and 380 * thus we need to fail this here. 381 * This assumes that the interrupts are 14 and 15 which they are for 382 * IDE compat mode. 383 * Really the firmware should make this clear in the interrupt reg. 384 */ 385 if (ih >= 0x80 && ih <= 0x8d) { 386 intr = isa_intr_establish(NULL, (ih & 0x0f), IST_EDGE, 387 level, func, arg); 388 } else 389 #endif 390 intr = footbridge_intr_claim(ih, level, string, func, arg); 391 392 return(intr); 393 } 394 395 void 396 footbridge_pci_intr_disestablish(pcv, cookie) 397 void *pcv; 398 void *cookie; 399 { 400 #ifdef PCI_DEBUG 401 printf("footbridge_pci_intr_disestablish(pcv=%p, cookie=0x%x)\n", 402 pcv, cookie); 403 #endif 404 /* XXXX Need to free the string */ 405 footbridge_intr_disestablish(cookie); 406 } 407
Indexes created Mon Sep 29 21:09:56 GMT 2025