isa_machdep.c revision 1.10
1 /* $NetBSD: isa_machdep.c,v 1.10 2009/03/14 15:36:02 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1996-1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Mark Brinicombe, Charles M. Hannum and by Jason R. Thorpe of the 9 * Numerical Aerospace Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1991 The Regents of the University of California. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to Berkeley by 38 * William Jolitz. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. Neither the name of the University nor the names of its contributors 49 * may be used to endorse or promote products derived from this software 50 * without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 * 64 * @(#)isa.c 7.2 (Berkeley) 5/13/91 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: isa_machdep.c,v 1.10 2009/03/14 15:36:02 dsl Exp $"); 69 70 #include "opt_irqstats.h" 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/kernel.h> 75 #include <sys/syslog.h> 76 #include <sys/device.h> 77 #include <sys/malloc.h> 78 #include <sys/proc.h> 79 80 #define _ARM32_BUS_DMA_PRIVATE 81 #include <machine/bus.h> 82 83 #include <machine/intr.h> 84 #include <machine/pio.h> 85 #include <machine/bootconfig.h> 86 #include <machine/isa_machdep.h> 87 88 #include <dev/isa/isareg.h> 89 #include <dev/isa/isavar.h> 90 #include <dev/isa/isadmareg.h> 91 #include <dev/isa/isadmavar.h> 92 #include <arm/footbridge/isa/icu.h> 93 #include <arm/footbridge/dc21285reg.h> 94 #include <arm/footbridge/dc21285mem.h> 95 96 #include <uvm/uvm_extern.h> 97 98 #include "isadma.h" 99 100 /* prototypes */ 101 static void isa_icu_init(void); 102 103 struct arm32_isa_chipset isa_chipset_tag; 104 105 void isa_strayintr(int); 106 void intr_calculatemasks(void); 107 int fakeintr(void *); 108 109 int isa_irqdispatch(void *arg); 110 111 u_int imask[NIPL]; 112 unsigned imen; 113 114 #define AUTO_EOI_1 115 #define AUTO_EOI_2 116 117 /* 118 * Fill in default interrupt table (in case of spuruious interrupt 119 * during configuration of kernel, setup interrupt control unit 120 */ 121 static void 122 isa_icu_init(void) 123 { 124 /* initialize 8259's */ 125 outb(IO_ICU1, 0x11); /* reset; program device, four bytes */ 126 outb(IO_ICU1+1, ICU_OFFSET); /* starting at this vector index */ 127 outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */ 128 #ifdef AUTO_EOI_1 129 outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */ 130 #else 131 outb(IO_ICU1+1, 1); /* 8086 mode */ 132 #endif 133 outb(IO_ICU1+1, 0xff); /* leave interrupts masked */ 134 outb(IO_ICU1, 0x68); /* special mask mode (if available) */ 135 outb(IO_ICU1, 0x0a); /* Read IRR by default. */ 136 #ifdef REORDER_IRQ 137 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */ 138 #endif 139 140 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ 141 outb(IO_ICU2+1, ICU_OFFSET+8); /* staring at this vector index */ 142 outb(IO_ICU2+1, IRQ_SLAVE); 143 #ifdef AUTO_EOI_2 144 outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */ 145 #else 146 outb(IO_ICU2+1, 1); /* 8086 mode */ 147 #endif 148 outb(IO_ICU2+1, 0xff); /* leave interrupts masked */ 149 outb(IO_ICU2, 0x68); /* special mask mode (if available) */ 150 outb(IO_ICU2, 0x0a); /* Read IRR by default. */ 151 } 152 153 /* 154 * Caught a stray interrupt, notify 155 */ 156 void 157 isa_strayintr(int irq) 158 { 159 static u_long strays; 160 161 /* 162 * Stray interrupts on irq 7 occur when an interrupt line is raised 163 * and then lowered before the CPU acknowledges it. This generally 164 * means either the device is screwed or something is cli'ing too 165 * long and it's timing out. 166 */ 167 if (++strays <= 5) 168 log(LOG_ERR, "stray interrupt %d%s\n", irq, 169 strays >= 5 ? "; stopped logging" : ""); 170 } 171 172 static struct intrq isa_intrq[ICU_LEN]; 173 174 /* 175 * Recalculate the interrupt masks from scratch. 176 * We could code special registry and deregistry versions of this function that 177 * would be faster, but the code would be nastier, and we don't expect this to 178 * happen very much anyway. 179 */ 180 void 181 intr_calculatemasks() 182 { 183 int irq, level; 184 struct intrq *iq; 185 struct intrhand *ih; 186 187 /* First, figure out which levels each IRQ uses. */ 188 for (irq = 0; irq < ICU_LEN; irq++) { 189 int levels = 0; 190 iq = &isa_intrq[irq]; 191 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 192 ih = TAILQ_NEXT(ih, ih_list)) 193 levels |= (1U << ih->ih_ipl); 194 iq->iq_levels = levels; 195 } 196 197 /* Then figure out which IRQs use each level. */ 198 for (level = 0; level < NIPL; level++) { 199 int irqs = 0; 200 for (irq = 0; irq < ICU_LEN; irq++) 201 if (isa_intrq[irq].iq_levels & (1U << level)) 202 irqs |= (1U << irq); 203 imask[level] = irqs; 204 } 205 206 imask[IPL_NONE] = 0; 207 imask[IPL_SOFTCLOCK] |= imask[IPL_NONE]; 208 imask[IPL_SOFTBIO] |= imask[IPL_SOFTCLOCK]; 209 imask[IPL_SOFTNET] |= imask[IPL_SOFTBIO]; 210 imask[IPL_SOFTSERIAL] |= imask[IPL_SOFTNET]; 211 imask[IPL_VM] |= imask[IPL_SOFTSERIAL]; 212 imask[IPL_SCHED] |= imask[IPL_VM]; 213 imask[IPL_HIGH] |= imask[IPL_SCHED]; 214 215 /* And eventually calculate the complete masks. */ 216 for (irq = 0; irq < ICU_LEN; irq++) { 217 int irqs = 1 << irq; 218 iq = &isa_intrq[irq]; 219 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 220 ih = TAILQ_NEXT(ih, ih_list)) 221 irqs |= imask[ih->ih_ipl]; 222 iq->iq_mask = irqs; 223 } 224 225 /* Lastly, determine which IRQs are actually in use. */ 226 { 227 int irqs = 0; 228 for (irq = 0; irq < ICU_LEN; irq++) 229 if (!TAILQ_EMPTY(&isa_intrq[irq].iq_list)) 230 irqs |= (1U << irq); 231 if (irqs >= 0x100) /* any IRQs >= 8 in use */ 232 irqs |= 1 << IRQ_SLAVE; 233 imen = ~irqs; 234 SET_ICUS(); 235 } 236 #if 0 237 printf("type\tmask\tlevel\thand\n"); 238 for (irq = 0; irq < ICU_LEN; irq++) { 239 printf("%x\t%04x\t%x\t%p\n", intrtype[irq], intrmask[irq], 240 intrlevel[irq], intrhand[irq]); 241 } 242 for (level = 0; level < IPL_LEVELS; ++level) 243 printf("%d: %08x\n", level, imask[level]); 244 #endif 245 } 246 247 int 248 fakeintr(void *arg) 249 { 250 251 return 0; 252 } 253 254 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2) 255 256 int 257 isa_intr_alloc(isa_chipset_tag_t ic, int mask, int type, int *irq) 258 { 259 int i, tmp, bestirq, count; 260 struct intrq *iq; 261 struct intrhand *ih; 262 263 if (type == IST_NONE) 264 panic("intr_alloc: bogus type"); 265 266 bestirq = -1; 267 count = -1; 268 269 /* some interrupts should never be dynamically allocated */ 270 mask &= 0xdef8; 271 272 /* 273 * XXX some interrupts will be used later (6 for fdc, 12 for pms). 274 * the right answer is to do "breadth-first" searching of devices. 275 */ 276 mask &= 0xefbf; 277 278 for (i = 0; i < ICU_LEN; i++) { 279 if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0) 280 continue; 281 282 iq = &isa_intrq[i]; 283 switch(iq->iq_ist) { 284 case IST_NONE: 285 /* 286 * if nothing's using the irq, just return it 287 */ 288 *irq = i; 289 return (0); 290 291 case IST_EDGE: 292 case IST_LEVEL: 293 if (type != iq->iq_ist) 294 continue; 295 /* 296 * if the irq is shareable, count the number of other 297 * handlers, and if it's smaller than the last irq like 298 * this, remember it 299 * 300 * XXX We should probably also consider the 301 * interrupt level and stick IPL_TTY with other 302 * IPL_TTY, etc. 303 */ 304 tmp = 0; 305 TAILQ_FOREACH(ih, &(iq->iq_list), ih_list) 306 tmp++; 307 if ((bestirq == -1) || (count > tmp)) { 308 bestirq = i; 309 count = tmp; 310 } 311 break; 312 313 case IST_PULSE: 314 /* this just isn't shareable */ 315 continue; 316 } 317 } 318 319 if (bestirq == -1) 320 return (1); 321 322 *irq = bestirq; 323 324 return (0); 325 } 326 327 const struct evcnt * 328 isa_intr_evcnt(isa_chipset_tag_t ic, int irq) 329 { 330 return &isa_intrq[irq].iq_ev; 331 } 332 333 /* 334 * Set up an interrupt handler to start being called. 335 * XXX PRONE TO RACE CONDITIONS, UGLY, 'INTERESTING' INSERTION ALGORITHM. 336 */ 337 void * 338 isa_intr_establish(ic, irq, type, level, ih_fun, ih_arg) 339 isa_chipset_tag_t ic; 340 int irq; 341 int type; 342 int level; 343 int (*ih_fun)(void *); 344 void *ih_arg; 345 { 346 struct intrq *iq; 347 struct intrhand *ih; 348 u_int oldirqstate; 349 350 #if 0 351 printf("isa_intr_establish(%d, %d, %d)\n", irq, type, level); 352 #endif 353 /* no point in sleeping unless someone can free memory. */ 354 ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 355 if (ih == NULL) 356 return (NULL); 357 358 if (!LEGAL_IRQ(irq) || type == IST_NONE) 359 panic("intr_establish: bogus irq or type"); 360 361 iq = &isa_intrq[irq]; 362 363 switch (iq->iq_ist) { 364 case IST_NONE: 365 iq->iq_ist = type; 366 #if 0 367 printf("Setting irq %d to type %d - ", irq, type); 368 #endif 369 if (irq < 8) { 370 outb(0x4d0, (inb(0x4d0) & ~(1 << irq)) 371 | ((type == IST_LEVEL) ? (1 << irq) : 0)); 372 /* printf("%02x\n", inb(0x4d0));*/ 373 } else { 374 outb(0x4d1, (inb(0x4d1) & ~(1 << irq)) 375 | ((type == IST_LEVEL) ? (1 << irq) : 0)); 376 /* printf("%02x\n", inb(0x4d1));*/ 377 } 378 break; 379 case IST_EDGE: 380 case IST_LEVEL: 381 if (iq->iq_ist == type) 382 break; 383 case IST_PULSE: 384 if (type != IST_NONE) 385 panic("intr_establish: can't share %s with %s", 386 isa_intr_typename(iq->iq_ist), 387 isa_intr_typename(type)); 388 break; 389 } 390 391 ih->ih_func = ih_fun; 392 ih->ih_arg = ih_arg; 393 ih->ih_ipl = level; 394 ih->ih_irq = irq; 395 396 /* do not stop us */ 397 oldirqstate = disable_interrupts(I32_bit); 398 399 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 400 401 intr_calculatemasks(); 402 restore_interrupts(oldirqstate); 403 404 return (ih); 405 } 406 407 /* 408 * Deregister an interrupt handler. 409 */ 410 void 411 isa_intr_disestablish(isa_chipset_tag_t ic, void *arg) 412 { 413 struct intrhand *ih = arg; 414 struct intrq *iq = &isa_intrq[ih->ih_irq]; 415 int irq = ih->ih_irq; 416 u_int oldirqstate; 417 418 if (!LEGAL_IRQ(irq)) 419 panic("intr_disestablish: bogus irq"); 420 421 oldirqstate = disable_interrupts(I32_bit); 422 423 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 424 425 intr_calculatemasks(); 426 427 restore_interrupts(oldirqstate); 428 429 free(ih, M_DEVBUF); 430 431 if (TAILQ_EMPTY(&(iq->iq_list))) 432 iq->iq_ist = IST_NONE; 433 } 434 435 /* 436 * isa_intr_init() 437 * 438 * Initialise the ISA ICU and attach an ISA interrupt handler to the 439 * ISA interrupt line on the footbridge. 440 */ 441 void 442 isa_intr_init(void) 443 { 444 static void *isa_ih; 445 struct intrq *iq; 446 int i; 447 448 /* 449 * should get the parent here, but initialisation order being so 450 * strange I need to check if it's available 451 */ 452 for (i = 0; i < ICU_LEN; i++) { 453 iq = &isa_intrq[i]; 454 TAILQ_INIT(&iq->iq_list); 455 456 sprintf(iq->iq_name, "irq %d", i); 457 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 458 NULL, "isa", iq->iq_name); 459 } 460 461 isa_icu_init(); 462 intr_calculatemasks(); 463 /* something to break the build in an informative way */ 464 #ifndef ISA_FOOTBRIDGE_IRQ 465 #warning Before using isa with footbridge you must define ISA_FOOTBRIDGE_IRQ 466 #endif 467 isa_ih = footbridge_intr_claim(ISA_FOOTBRIDGE_IRQ, IPL_BIO, "isabus", 468 isa_irqdispatch, NULL); 469 470 } 471 472 /* Static array of ISA DMA segments. We only have one on CATS */ 473 #if NISADMA > 0 474 struct arm32_dma_range machdep_isa_dma_ranges[1]; 475 #endif 476 477 void 478 isa_footbridge_init(iobase, membase) 479 u_int iobase, membase; 480 { 481 #if NISADMA > 0 482 extern struct arm32_dma_range *footbridge_isa_dma_ranges; 483 extern int footbridge_isa_dma_nranges; 484 485 machdep_isa_dma_ranges[0].dr_sysbase = bootconfig.dram[0].address; 486 machdep_isa_dma_ranges[0].dr_busbase = bootconfig.dram[0].address; 487 machdep_isa_dma_ranges[0].dr_len = (16 * 1024 * 1024); 488 489 footbridge_isa_dma_ranges = machdep_isa_dma_ranges; 490 footbridge_isa_dma_nranges = 1; 491 #endif 492 493 isa_io_init(iobase, membase); 494 } 495 496 void 497 isa_attach_hook(parent, self, iba) 498 struct device *parent, *self; 499 struct isabus_attach_args *iba; 500 { 501 /* 502 * Since we can only have one ISA bus, we just use a single 503 * statically allocated ISA chipset structure. Pass it up 504 * now. 505 */ 506 iba->iba_ic = &isa_chipset_tag; 507 #if NISADMA > 0 508 isa_dma_init(); 509 #endif 510 } 511 512 int 513 isa_irqdispatch(void *arg) 514 { 515 struct clockframe *frame = arg; 516 int irq; 517 struct intrq *iq; 518 struct intrhand *ih; 519 u_int iack; 520 int res = 0; 521 522 iack = *((u_int *)(DC21285_PCI_IACK_VBASE)); 523 iack &= 0xff; 524 if (iack < 0x20 || iack > 0x2f) { 525 printf("isa_irqdispatch: %x\n", iack); 526 return(0); 527 } 528 529 irq = iack & 0x0f; 530 iq = &isa_intrq[irq]; 531 iq->iq_ev.ev_count++; 532 for (ih = TAILQ_FIRST(&iq->iq_list); res != 1 && ih != NULL; 533 ih = TAILQ_NEXT(ih, ih_list)) { 534 res = (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 535 } 536 return res; 537 } 538 539 540 void 541 isa_fillw(u_int val, void *addr, size_t len) 542 { 543 if ((u_int)addr >= isa_mem_data_vaddr() 544 && (u_int)addr < isa_mem_data_vaddr() + 0x100000) { 545 bus_size_t offset = ((u_int)addr) & 0xfffff; 546 bus_space_set_region_2(&isa_mem_bs_tag, 547 (bus_space_handle_t)isa_mem_bs_tag.bs_cookie, offset, 548 val, len); 549 } else { 550 u_short *ptr = addr; 551 552 while (len > 0) { 553 *ptr++ = val; 554 --len; 555 } 556 } 557 } 558
Indexes created Tue Sep 30 20:09:53 GMT 2025