isa_machdep.c revision 1.3
1 /* $NetBSD: isa_machdep.c,v 1.3 2003/03/23 14:12:26 chris Exp $ */ 2 3 /*- 4 * Copyright (c) 1996-1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Mark Brinicombe, Charles M. Hannum and by Jason R. Thorpe of the 9 * Numerical Aerospace Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /*- 41 * Copyright (c) 1991 The Regents of the University of California. 42 * All rights reserved. 43 * 44 * This code is derived from software contributed to Berkeley by 45 * William Jolitz. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that the following conditions 49 * are met: 50 * 1. Redistributions of source code must retain the above copyright 51 * notice, this list of conditions and the following disclaimer. 52 * 2. Redistributions in binary form must reproduce the above copyright 53 * notice, this list of conditions and the following disclaimer in the 54 * documentation and/or other materials provided with the distribution. 55 * 3. All advertising materials mentioning features or use of this software 56 * must display the following acknowledgement: 57 * This product includes software developed by the University of 58 * California, Berkeley and its contributors. 59 * 4. Neither the name of the University nor the names of its contributors 60 * may be used to endorse or promote products derived from this software 61 * without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 64 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 65 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 66 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 67 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 68 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 69 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 70 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 71 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 72 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 73 * SUCH DAMAGE. 74 * 75 * @(#)isa.c 7.2 (Berkeley) 5/13/91 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: isa_machdep.c,v 1.3 2003/03/23 14:12:26 chris Exp $"); 80 81 #include "opt_irqstats.h" 82 83 #include <sys/param.h> 84 #include <sys/systm.h> 85 #include <sys/kernel.h> 86 #include <sys/syslog.h> 87 #include <sys/device.h> 88 #include <sys/malloc.h> 89 #include <sys/proc.h> 90 91 #define _ARM32_BUS_DMA_PRIVATE 92 #include <machine/bus.h> 93 94 #include <machine/intr.h> 95 #include <machine/pio.h> 96 #include <machine/bootconfig.h> 97 #include <machine/isa_machdep.h> 98 99 #include <dev/isa/isareg.h> 100 #include <dev/isa/isavar.h> 101 #include <dev/isa/isadmareg.h> 102 #include <dev/isa/isadmavar.h> 103 #include <arm/footbridge/isa/icu.h> 104 #include <arm/footbridge/dc21285reg.h> 105 #include <arm/footbridge/dc21285mem.h> 106 107 #include <uvm/uvm_extern.h> 108 109 #include "isadma.h" 110 111 /* prototypes */ 112 static void isa_icu_init __P((void)); 113 114 struct arm32_isa_chipset isa_chipset_tag; 115 116 void isa_strayintr __P((int)); 117 void intr_calculatemasks __P((void)); 118 int fakeintr __P((void *)); 119 120 int isa_irqdispatch __P((void *arg)); 121 122 u_int imask[NIPL]; 123 unsigned imen; 124 125 #define AUTO_EOI_1 126 #define AUTO_EOI_2 127 128 /* 129 * Fill in default interrupt table (in case of spuruious interrupt 130 * during configuration of kernel, setup interrupt control unit 131 */ 132 static void 133 isa_icu_init(void) 134 { 135 /* initialize 8259's */ 136 outb(IO_ICU1, 0x11); /* reset; program device, four bytes */ 137 outb(IO_ICU1+1, ICU_OFFSET); /* starting at this vector index */ 138 outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */ 139 #ifdef AUTO_EOI_1 140 outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */ 141 #else 142 outb(IO_ICU1+1, 1); /* 8086 mode */ 143 #endif 144 outb(IO_ICU1+1, 0xff); /* leave interrupts masked */ 145 outb(IO_ICU1, 0x68); /* special mask mode (if available) */ 146 outb(IO_ICU1, 0x0a); /* Read IRR by default. */ 147 #ifdef REORDER_IRQ 148 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */ 149 #endif 150 151 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ 152 outb(IO_ICU2+1, ICU_OFFSET+8); /* staring at this vector index */ 153 outb(IO_ICU2+1, IRQ_SLAVE); 154 #ifdef AUTO_EOI_2 155 outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */ 156 #else 157 outb(IO_ICU2+1, 1); /* 8086 mode */ 158 #endif 159 outb(IO_ICU2+1, 0xff); /* leave interrupts masked */ 160 outb(IO_ICU2, 0x68); /* special mask mode (if available) */ 161 outb(IO_ICU2, 0x0a); /* Read IRR by default. */ 162 } 163 164 /* 165 * Caught a stray interrupt, notify 166 */ 167 void 168 isa_strayintr(irq) 169 int irq; 170 { 171 static u_long strays; 172 173 /* 174 * Stray interrupts on irq 7 occur when an interrupt line is raised 175 * and then lowered before the CPU acknowledges it. This generally 176 * means either the device is screwed or something is cli'ing too 177 * long and it's timing out. 178 */ 179 if (++strays <= 5) 180 log(LOG_ERR, "stray interrupt %d%s\n", irq, 181 strays >= 5 ? "; stopped logging" : ""); 182 } 183 184 static struct intrq isa_intrq[ICU_LEN]; 185 186 /* 187 * Recalculate the interrupt masks from scratch. 188 * We could code special registry and deregistry versions of this function that 189 * would be faster, but the code would be nastier, and we don't expect this to 190 * happen very much anyway. 191 */ 192 void 193 intr_calculatemasks() 194 { 195 int irq, level; 196 struct intrq *iq; 197 struct intrhand *ih; 198 199 /* First, figure out which levels each IRQ uses. */ 200 for (irq = 0; irq < ICU_LEN; irq++) { 201 int levels = 0; 202 iq = &isa_intrq[irq]; 203 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 204 ih = TAILQ_NEXT(ih, ih_list)) 205 levels |= (1U << ih->ih_ipl); 206 iq->iq_levels = levels; 207 } 208 209 /* Then figure out which IRQs use each level. */ 210 for (level = 0; level < NIPL; level++) { 211 int irqs = 0; 212 for (irq = 0; irq < ICU_LEN; irq++) 213 if (isa_intrq[irq].iq_levels & (1U << level)) 214 irqs |= (1U << irq); 215 imask[level] = irqs; 216 } 217 218 /* 219 * IPL_NONE is used for hardware interrupts that are never blocked, 220 * and do not block anything else. 221 */ 222 imask[IPL_NONE] = 0; 223 224 imask[IPL_SOFT] |= imask[IPL_NONE]; 225 imask[IPL_SOFTCLOCK] |= imask[IPL_SOFT]; 226 imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK]; 227 228 /* 229 * Enforce a hierarchy that gives slow devices a better chance at not 230 * dropping data. 231 */ 232 imask[IPL_BIO] |= imask[IPL_SOFTCLOCK]; 233 imask[IPL_NET] |= imask[IPL_BIO]; 234 imask[IPL_SOFTSERIAL] |= imask[IPL_NET]; 235 imask[IPL_TTY] |= imask[IPL_NET]; 236 /* 237 * There are tty, network and disk drivers that use free() at interrupt 238 * time, so imp > (tty | net | bio). 239 */ 240 imask[IPL_IMP] |= imask[IPL_TTY]; 241 imask[IPL_AUDIO] |= imask[IPL_IMP]; 242 243 /* 244 * Since run queues may be manipulated by both the statclock and tty, 245 * network, and disk drivers, clock > imp. 246 */ 247 imask[IPL_CLOCK] |= imask[IPL_IMP]; 248 imask[IPL_STATCLOCK] |= imask[IPL_CLOCK]; 249 250 /* 251 * IPL_HIGH must block everything that can manipulate a run queue. 252 */ 253 imask[IPL_HIGH] |= imask[IPL_STATCLOCK]; 254 255 /* 256 * We need serial drivers to run at the absolute highest priority to 257 * avoid overruns, so serial > high. 258 */ 259 imask[IPL_SERIAL] |= imask[IPL_HIGH]; 260 261 /* And eventually calculate the complete masks. */ 262 for (irq = 0; irq < ICU_LEN; irq++) { 263 int irqs = 1 << irq; 264 iq = &isa_intrq[irq]; 265 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 266 ih = TAILQ_NEXT(ih, ih_list)) 267 irqs |= imask[ih->ih_ipl]; 268 iq->iq_mask = irqs; 269 } 270 271 /* Lastly, determine which IRQs are actually in use. */ 272 { 273 int irqs = 0; 274 for (irq = 0; irq < ICU_LEN; irq++) 275 if (!TAILQ_EMPTY(&isa_intrq[irq].iq_list)) 276 irqs |= (1U << irq); 277 if (irqs >= 0x100) /* any IRQs >= 8 in use */ 278 irqs |= 1 << IRQ_SLAVE; 279 imen = ~irqs; 280 SET_ICUS(); 281 } 282 #if 0 283 printf("type\tmask\tlevel\thand\n"); 284 for (irq = 0; irq < ICU_LEN; irq++) { 285 printf("%x\t%04x\t%x\t%p\n", intrtype[irq], intrmask[irq], 286 intrlevel[irq], intrhand[irq]); 287 } 288 for (level = 0; level < IPL_LEVELS; ++level) 289 printf("%d: %08x\n", level, imask[level]); 290 #endif 291 } 292 293 int 294 fakeintr(arg) 295 void *arg; 296 { 297 298 return 0; 299 } 300 301 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2) 302 303 int 304 isa_intr_alloc(ic, mask, type, irq) 305 isa_chipset_tag_t ic; 306 int mask; 307 int type; 308 int *irq; 309 { 310 int i, tmp, bestirq, count; 311 struct intrq *iq; 312 struct intrhand *ih; 313 314 if (type == IST_NONE) 315 panic("intr_alloc: bogus type"); 316 317 bestirq = -1; 318 count = -1; 319 320 /* some interrupts should never be dynamically allocated */ 321 mask &= 0xdef8; 322 323 /* 324 * XXX some interrupts will be used later (6 for fdc, 12 for pms). 325 * the right answer is to do "breadth-first" searching of devices. 326 */ 327 mask &= 0xefbf; 328 329 for (i = 0; i < ICU_LEN; i++) { 330 if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0) 331 continue; 332 333 iq = &isa_intrq[i]; 334 switch(iq->iq_ist) { 335 case IST_NONE: 336 /* 337 * if nothing's using the irq, just return it 338 */ 339 *irq = i; 340 return (0); 341 342 case IST_EDGE: 343 case IST_LEVEL: 344 if (type != iq->iq_ist) 345 continue; 346 /* 347 * if the irq is shareable, count the number of other 348 * handlers, and if it's smaller than the last irq like 349 * this, remember it 350 * 351 * XXX We should probably also consider the 352 * interrupt level and stick IPL_TTY with other 353 * IPL_TTY, etc. 354 */ 355 tmp = 0; 356 TAILQ_FOREACH(ih, &(iq->iq_list), ih_list) 357 tmp++; 358 if ((bestirq == -1) || (count > tmp)) { 359 bestirq = i; 360 count = tmp; 361 } 362 break; 363 364 case IST_PULSE: 365 /* this just isn't shareable */ 366 continue; 367 } 368 } 369 370 if (bestirq == -1) 371 return (1); 372 373 *irq = bestirq; 374 375 return (0); 376 } 377 378 const struct evcnt * 379 isa_intr_evcnt(isa_chipset_tag_t ic, int irq) 380 { 381 return &isa_intrq[irq].iq_ev; 382 } 383 384 /* 385 * Set up an interrupt handler to start being called. 386 * XXX PRONE TO RACE CONDITIONS, UGLY, 'INTERESTING' INSERTION ALGORITHM. 387 */ 388 void * 389 isa_intr_establish(ic, irq, type, level, ih_fun, ih_arg) 390 isa_chipset_tag_t ic; 391 int irq; 392 int type; 393 int level; 394 int (*ih_fun) __P((void *)); 395 void *ih_arg; 396 { 397 struct intrq *iq; 398 struct intrhand *ih; 399 u_int oldirqstate; 400 401 #if 0 402 printf("isa_intr_establish(%d, %d, %d)\n", irq, type, level); 403 #endif 404 /* no point in sleeping unless someone can free memory. */ 405 ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 406 if (ih == NULL) 407 return (NULL); 408 409 if (!LEGAL_IRQ(irq) || type == IST_NONE) 410 panic("intr_establish: bogus irq or type"); 411 412 iq = &isa_intrq[irq]; 413 414 switch (iq->iq_ist) { 415 case IST_NONE: 416 iq->iq_ist = type; 417 #if 0 418 printf("Setting irq %d to type %d - ", irq, type); 419 #endif 420 if (irq < 8) { 421 outb(0x4d0, (inb(0x4d0) & ~(1 << irq)) 422 | ((type == IST_LEVEL) ? (1 << irq) : 0)); 423 /* printf("%02x\n", inb(0x4d0));*/ 424 } else { 425 outb(0x4d1, (inb(0x4d1) & ~(1 << irq)) 426 | ((type == IST_LEVEL) ? (1 << irq) : 0)); 427 /* printf("%02x\n", inb(0x4d1));*/ 428 } 429 break; 430 case IST_EDGE: 431 case IST_LEVEL: 432 if (iq->iq_ist == type) 433 break; 434 case IST_PULSE: 435 if (type != IST_NONE) 436 panic("intr_establish: can't share %s with %s", 437 isa_intr_typename(iq->iq_ist), 438 isa_intr_typename(type)); 439 break; 440 } 441 442 ih->ih_func = ih_fun; 443 ih->ih_arg = ih_arg; 444 ih->ih_ipl = level; 445 ih->ih_irq = irq; 446 447 /* do not stop us */ 448 oldirqstate = disable_interrupts(I32_bit); 449 450 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 451 452 intr_calculatemasks(); 453 restore_interrupts(oldirqstate); 454 455 return (ih); 456 } 457 458 /* 459 * Deregister an interrupt handler. 460 */ 461 void 462 isa_intr_disestablish(ic, arg) 463 isa_chipset_tag_t ic; 464 void *arg; 465 { 466 struct intrhand *ih = arg; 467 struct intrq *iq = &isa_intrq[ih->ih_irq]; 468 int irq = ih->ih_irq; 469 u_int oldirqstate; 470 471 if (!LEGAL_IRQ(irq)) 472 panic("intr_disestablish: bogus irq"); 473 474 oldirqstate = disable_interrupts(I32_bit); 475 476 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 477 478 intr_calculatemasks(); 479 480 restore_interrupts(oldirqstate); 481 482 free(ih, M_DEVBUF); 483 484 if (TAILQ_EMPTY(&(iq->iq_list))) 485 iq->iq_ist = IST_NONE; 486 } 487 488 /* 489 * isa_intr_init() 490 * 491 * Initialise the ISA ICU and attach an ISA interrupt handler to the 492 * ISA interrupt line on the footbridge. 493 */ 494 void 495 isa_intr_init(void) 496 { 497 static void *isa_ih; 498 struct intrq *iq; 499 int i; 500 501 /* 502 * should get the parent here, but initialisation order being so 503 * strange I need to check if it's available 504 */ 505 for (i = 0; i < ICU_LEN; i++) { 506 iq = &isa_intrq[i]; 507 TAILQ_INIT(&iq->iq_list); 508 509 sprintf(iq->iq_name, "irq %d", i); 510 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 511 NULL, "isa", iq->iq_name); 512 } 513 514 isa_icu_init(); 515 intr_calculatemasks(); 516 /* something to break the build in an informative way */ 517 #ifndef ISA_FOOTBRIDGE_IRQ 518 #warning Before using isa with footbridge you must define ISA_FOOTBRIDGE_IRQ 519 #endif 520 isa_ih = footbridge_intr_claim(ISA_FOOTBRIDGE_IRQ, IPL_BIO, "isabus", 521 isa_irqdispatch, NULL); 522 523 } 524 525 /* Static array of ISA DMA segments. We only have one on CATS */ 526 #if NISADMA > 0 527 struct arm32_dma_range machdep_isa_dma_ranges[1]; 528 #endif 529 530 void 531 isa_footbridge_init(iobase, membase) 532 u_int iobase, membase; 533 { 534 #if NISADMA > 0 535 extern struct arm32_dma_range *footbridge_isa_dma_ranges; 536 extern int footbridge_isa_dma_nranges; 537 538 machdep_isa_dma_ranges[0].dr_sysbase = bootconfig.dram[0].address; 539 machdep_isa_dma_ranges[0].dr_busbase = bootconfig.dram[0].address; 540 machdep_isa_dma_ranges[0].dr_len = (16 * 1024 * 1024); 541 542 footbridge_isa_dma_ranges = machdep_isa_dma_ranges; 543 footbridge_isa_dma_nranges = 1; 544 #endif 545 546 isa_io_init(iobase, membase); 547 } 548 549 void 550 isa_attach_hook(parent, self, iba) 551 struct device *parent, *self; 552 struct isabus_attach_args *iba; 553 { 554 /* 555 * Since we can only have one ISA bus, we just use a single 556 * statically allocated ISA chipset structure. Pass it up 557 * now. 558 */ 559 iba->iba_ic = &isa_chipset_tag; 560 #if NISADMA > 0 561 isa_dma_init(); 562 #endif 563 } 564 565 int 566 isa_irqdispatch(arg) 567 void *arg; 568 { 569 struct clockframe *frame = arg; 570 int irq; 571 struct intrq *iq; 572 struct intrhand *ih; 573 u_int iack; 574 int res = 0; 575 576 iack = *((u_int *)(DC21285_PCI_IACK_VBASE)); 577 iack &= 0xff; 578 if (iack < 0x20 || iack > 0x2f) { 579 printf("isa_irqdispatch: %x\n", iack); 580 return(0); 581 } 582 583 irq = iack & 0x0f; 584 iq = &isa_intrq[irq]; 585 iq->iq_ev.ev_count++; 586 for (ih = TAILQ_FIRST(&iq->iq_list); res != 1 && ih != NULL; 587 ih = TAILQ_NEXT(ih, ih_list)) { 588 res = (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 589 } 590 return res; 591 } 592 593 594 void 595 isa_fillw(val, addr, len) 596 u_int val; 597 void *addr; 598 size_t len; 599 { 600 if ((u_int)addr >= isa_mem_data_vaddr() 601 && (u_int)addr < isa_mem_data_vaddr() + 0x100000) { 602 bus_size_t offset = ((u_int)addr) & 0xfffff; 603 bus_space_set_region_2(&isa_mem_bs_tag, 604 (bus_space_handle_t)isa_mem_bs_tag.bs_cookie, offset, 605 val, len); 606 } else { 607 u_short *ptr = addr; 608 609 while (len > 0) { 610 *ptr++ = val; 611 --len; 612 } 613 } 614 } 615
Indexes created Tue Sep 30 17:09:57 GMT 2025