isa_machdep.c revision 1.5
1 /* $NetBSD: isa_machdep.c,v 1.5 2003/08/07 16:26:52 agc Exp $ */ 2 3 /*- 4 * Copyright (c) 1996-1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Mark Brinicombe, Charles M. Hannum and by Jason R. Thorpe of the 9 * Numerical Aerospace Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /*- 41 * Copyright (c) 1991 The Regents of the University of California. 42 * All rights reserved. 43 * 44 * This code is derived from software contributed to Berkeley by 45 * William Jolitz. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that the following conditions 49 * are met: 50 * 1. Redistributions of source code must retain the above copyright 51 * notice, this list of conditions and the following disclaimer. 52 * 2. Redistributions in binary form must reproduce the above copyright 53 * notice, this list of conditions and the following disclaimer in the 54 * documentation and/or other materials provided with the distribution. 55 * 3. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)isa.c 7.2 (Berkeley) 5/13/91 72 */ 73 74 #include <sys/cdefs.h> 75 __KERNEL_RCSID(0, "$NetBSD: isa_machdep.c,v 1.5 2003/08/07 16:26:52 agc Exp $"); 76 77 #include "opt_irqstats.h" 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/syslog.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/proc.h> 86 87 #define _ARM32_BUS_DMA_PRIVATE 88 #include <machine/bus.h> 89 90 #include <machine/intr.h> 91 #include <machine/pio.h> 92 #include <machine/bootconfig.h> 93 #include <machine/isa_machdep.h> 94 95 #include <dev/isa/isareg.h> 96 #include <dev/isa/isavar.h> 97 #include <dev/isa/isadmareg.h> 98 #include <dev/isa/isadmavar.h> 99 #include <arm/footbridge/isa/icu.h> 100 #include <arm/footbridge/dc21285reg.h> 101 #include <arm/footbridge/dc21285mem.h> 102 103 #include <uvm/uvm_extern.h> 104 105 #include "isadma.h" 106 107 /* prototypes */ 108 static void isa_icu_init __P((void)); 109 110 struct arm32_isa_chipset isa_chipset_tag; 111 112 void isa_strayintr __P((int)); 113 void intr_calculatemasks __P((void)); 114 int fakeintr __P((void *)); 115 116 int isa_irqdispatch __P((void *arg)); 117 118 u_int imask[NIPL]; 119 unsigned imen; 120 121 #define AUTO_EOI_1 122 #define AUTO_EOI_2 123 124 /* 125 * Fill in default interrupt table (in case of spuruious interrupt 126 * during configuration of kernel, setup interrupt control unit 127 */ 128 static void 129 isa_icu_init(void) 130 { 131 /* initialize 8259's */ 132 outb(IO_ICU1, 0x11); /* reset; program device, four bytes */ 133 outb(IO_ICU1+1, ICU_OFFSET); /* starting at this vector index */ 134 outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */ 135 #ifdef AUTO_EOI_1 136 outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */ 137 #else 138 outb(IO_ICU1+1, 1); /* 8086 mode */ 139 #endif 140 outb(IO_ICU1+1, 0xff); /* leave interrupts masked */ 141 outb(IO_ICU1, 0x68); /* special mask mode (if available) */ 142 outb(IO_ICU1, 0x0a); /* Read IRR by default. */ 143 #ifdef REORDER_IRQ 144 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */ 145 #endif 146 147 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ 148 outb(IO_ICU2+1, ICU_OFFSET+8); /* staring at this vector index */ 149 outb(IO_ICU2+1, IRQ_SLAVE); 150 #ifdef AUTO_EOI_2 151 outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */ 152 #else 153 outb(IO_ICU2+1, 1); /* 8086 mode */ 154 #endif 155 outb(IO_ICU2+1, 0xff); /* leave interrupts masked */ 156 outb(IO_ICU2, 0x68); /* special mask mode (if available) */ 157 outb(IO_ICU2, 0x0a); /* Read IRR by default. */ 158 } 159 160 /* 161 * Caught a stray interrupt, notify 162 */ 163 void 164 isa_strayintr(irq) 165 int irq; 166 { 167 static u_long strays; 168 169 /* 170 * Stray interrupts on irq 7 occur when an interrupt line is raised 171 * and then lowered before the CPU acknowledges it. This generally 172 * means either the device is screwed or something is cli'ing too 173 * long and it's timing out. 174 */ 175 if (++strays <= 5) 176 log(LOG_ERR, "stray interrupt %d%s\n", irq, 177 strays >= 5 ? "; stopped logging" : ""); 178 } 179 180 static struct intrq isa_intrq[ICU_LEN]; 181 182 /* 183 * Recalculate the interrupt masks from scratch. 184 * We could code special registry and deregistry versions of this function that 185 * would be faster, but the code would be nastier, and we don't expect this to 186 * happen very much anyway. 187 */ 188 void 189 intr_calculatemasks() 190 { 191 int irq, level; 192 struct intrq *iq; 193 struct intrhand *ih; 194 195 /* First, figure out which levels each IRQ uses. */ 196 for (irq = 0; irq < ICU_LEN; irq++) { 197 int levels = 0; 198 iq = &isa_intrq[irq]; 199 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 200 ih = TAILQ_NEXT(ih, ih_list)) 201 levels |= (1U << ih->ih_ipl); 202 iq->iq_levels = levels; 203 } 204 205 /* Then figure out which IRQs use each level. */ 206 for (level = 0; level < NIPL; level++) { 207 int irqs = 0; 208 for (irq = 0; irq < ICU_LEN; irq++) 209 if (isa_intrq[irq].iq_levels & (1U << level)) 210 irqs |= (1U << irq); 211 imask[level] = irqs; 212 } 213 214 /* 215 * IPL_NONE is used for hardware interrupts that are never blocked, 216 * and do not block anything else. 217 */ 218 imask[IPL_NONE] = 0; 219 220 imask[IPL_SOFT] |= imask[IPL_NONE]; 221 imask[IPL_SOFTCLOCK] |= imask[IPL_SOFT]; 222 imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK]; 223 224 /* 225 * Enforce a hierarchy that gives slow devices a better chance at not 226 * dropping data. 227 */ 228 imask[IPL_BIO] |= imask[IPL_SOFTCLOCK]; 229 imask[IPL_NET] |= imask[IPL_BIO]; 230 imask[IPL_SOFTSERIAL] |= imask[IPL_NET]; 231 imask[IPL_TTY] |= imask[IPL_NET]; 232 /* 233 * There are tty, network and disk drivers that use free() at interrupt 234 * time, so imp > (tty | net | bio). 235 */ 236 imask[IPL_VM] |= imask[IPL_TTY]; 237 imask[IPL_AUDIO] |= imask[IPL_VM]; 238 239 /* 240 * Since run queues may be manipulated by both the statclock and tty, 241 * network, and disk drivers, clock > imp. 242 */ 243 imask[IPL_CLOCK] |= imask[IPL_VM]; 244 imask[IPL_STATCLOCK] |= imask[IPL_CLOCK]; 245 246 /* 247 * IPL_HIGH must block everything that can manipulate a run queue. 248 */ 249 imask[IPL_HIGH] |= imask[IPL_STATCLOCK]; 250 251 /* 252 * We need serial drivers to run at the absolute highest priority to 253 * avoid overruns, so serial > high. 254 */ 255 imask[IPL_SERIAL] |= imask[IPL_HIGH]; 256 257 /* And eventually calculate the complete masks. */ 258 for (irq = 0; irq < ICU_LEN; irq++) { 259 int irqs = 1 << irq; 260 iq = &isa_intrq[irq]; 261 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 262 ih = TAILQ_NEXT(ih, ih_list)) 263 irqs |= imask[ih->ih_ipl]; 264 iq->iq_mask = irqs; 265 } 266 267 /* Lastly, determine which IRQs are actually in use. */ 268 { 269 int irqs = 0; 270 for (irq = 0; irq < ICU_LEN; irq++) 271 if (!TAILQ_EMPTY(&isa_intrq[irq].iq_list)) 272 irqs |= (1U << irq); 273 if (irqs >= 0x100) /* any IRQs >= 8 in use */ 274 irqs |= 1 << IRQ_SLAVE; 275 imen = ~irqs; 276 SET_ICUS(); 277 } 278 #if 0 279 printf("type\tmask\tlevel\thand\n"); 280 for (irq = 0; irq < ICU_LEN; irq++) { 281 printf("%x\t%04x\t%x\t%p\n", intrtype[irq], intrmask[irq], 282 intrlevel[irq], intrhand[irq]); 283 } 284 for (level = 0; level < IPL_LEVELS; ++level) 285 printf("%d: %08x\n", level, imask[level]); 286 #endif 287 } 288 289 int 290 fakeintr(arg) 291 void *arg; 292 { 293 294 return 0; 295 } 296 297 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2) 298 299 int 300 isa_intr_alloc(ic, mask, type, irq) 301 isa_chipset_tag_t ic; 302 int mask; 303 int type; 304 int *irq; 305 { 306 int i, tmp, bestirq, count; 307 struct intrq *iq; 308 struct intrhand *ih; 309 310 if (type == IST_NONE) 311 panic("intr_alloc: bogus type"); 312 313 bestirq = -1; 314 count = -1; 315 316 /* some interrupts should never be dynamically allocated */ 317 mask &= 0xdef8; 318 319 /* 320 * XXX some interrupts will be used later (6 for fdc, 12 for pms). 321 * the right answer is to do "breadth-first" searching of devices. 322 */ 323 mask &= 0xefbf; 324 325 for (i = 0; i < ICU_LEN; i++) { 326 if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0) 327 continue; 328 329 iq = &isa_intrq[i]; 330 switch(iq->iq_ist) { 331 case IST_NONE: 332 /* 333 * if nothing's using the irq, just return it 334 */ 335 *irq = i; 336 return (0); 337 338 case IST_EDGE: 339 case IST_LEVEL: 340 if (type != iq->iq_ist) 341 continue; 342 /* 343 * if the irq is shareable, count the number of other 344 * handlers, and if it's smaller than the last irq like 345 * this, remember it 346 * 347 * XXX We should probably also consider the 348 * interrupt level and stick IPL_TTY with other 349 * IPL_TTY, etc. 350 */ 351 tmp = 0; 352 TAILQ_FOREACH(ih, &(iq->iq_list), ih_list) 353 tmp++; 354 if ((bestirq == -1) || (count > tmp)) { 355 bestirq = i; 356 count = tmp; 357 } 358 break; 359 360 case IST_PULSE: 361 /* this just isn't shareable */ 362 continue; 363 } 364 } 365 366 if (bestirq == -1) 367 return (1); 368 369 *irq = bestirq; 370 371 return (0); 372 } 373 374 const struct evcnt * 375 isa_intr_evcnt(isa_chipset_tag_t ic, int irq) 376 { 377 return &isa_intrq[irq].iq_ev; 378 } 379 380 /* 381 * Set up an interrupt handler to start being called. 382 * XXX PRONE TO RACE CONDITIONS, UGLY, 'INTERESTING' INSERTION ALGORITHM. 383 */ 384 void * 385 isa_intr_establish(ic, irq, type, level, ih_fun, ih_arg) 386 isa_chipset_tag_t ic; 387 int irq; 388 int type; 389 int level; 390 int (*ih_fun) __P((void *)); 391 void *ih_arg; 392 { 393 struct intrq *iq; 394 struct intrhand *ih; 395 u_int oldirqstate; 396 397 #if 0 398 printf("isa_intr_establish(%d, %d, %d)\n", irq, type, level); 399 #endif 400 /* no point in sleeping unless someone can free memory. */ 401 ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 402 if (ih == NULL) 403 return (NULL); 404 405 if (!LEGAL_IRQ(irq) || type == IST_NONE) 406 panic("intr_establish: bogus irq or type"); 407 408 iq = &isa_intrq[irq]; 409 410 switch (iq->iq_ist) { 411 case IST_NONE: 412 iq->iq_ist = type; 413 #if 0 414 printf("Setting irq %d to type %d - ", irq, type); 415 #endif 416 if (irq < 8) { 417 outb(0x4d0, (inb(0x4d0) & ~(1 << irq)) 418 | ((type == IST_LEVEL) ? (1 << irq) : 0)); 419 /* printf("%02x\n", inb(0x4d0));*/ 420 } else { 421 outb(0x4d1, (inb(0x4d1) & ~(1 << irq)) 422 | ((type == IST_LEVEL) ? (1 << irq) : 0)); 423 /* printf("%02x\n", inb(0x4d1));*/ 424 } 425 break; 426 case IST_EDGE: 427 case IST_LEVEL: 428 if (iq->iq_ist == type) 429 break; 430 case IST_PULSE: 431 if (type != IST_NONE) 432 panic("intr_establish: can't share %s with %s", 433 isa_intr_typename(iq->iq_ist), 434 isa_intr_typename(type)); 435 break; 436 } 437 438 ih->ih_func = ih_fun; 439 ih->ih_arg = ih_arg; 440 ih->ih_ipl = level; 441 ih->ih_irq = irq; 442 443 /* do not stop us */ 444 oldirqstate = disable_interrupts(I32_bit); 445 446 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 447 448 intr_calculatemasks(); 449 restore_interrupts(oldirqstate); 450 451 return (ih); 452 } 453 454 /* 455 * Deregister an interrupt handler. 456 */ 457 void 458 isa_intr_disestablish(ic, arg) 459 isa_chipset_tag_t ic; 460 void *arg; 461 { 462 struct intrhand *ih = arg; 463 struct intrq *iq = &isa_intrq[ih->ih_irq]; 464 int irq = ih->ih_irq; 465 u_int oldirqstate; 466 467 if (!LEGAL_IRQ(irq)) 468 panic("intr_disestablish: bogus irq"); 469 470 oldirqstate = disable_interrupts(I32_bit); 471 472 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 473 474 intr_calculatemasks(); 475 476 restore_interrupts(oldirqstate); 477 478 free(ih, M_DEVBUF); 479 480 if (TAILQ_EMPTY(&(iq->iq_list))) 481 iq->iq_ist = IST_NONE; 482 } 483 484 /* 485 * isa_intr_init() 486 * 487 * Initialise the ISA ICU and attach an ISA interrupt handler to the 488 * ISA interrupt line on the footbridge. 489 */ 490 void 491 isa_intr_init(void) 492 { 493 static void *isa_ih; 494 struct intrq *iq; 495 int i; 496 497 /* 498 * should get the parent here, but initialisation order being so 499 * strange I need to check if it's available 500 */ 501 for (i = 0; i < ICU_LEN; i++) { 502 iq = &isa_intrq[i]; 503 TAILQ_INIT(&iq->iq_list); 504 505 sprintf(iq->iq_name, "irq %d", i); 506 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 507 NULL, "isa", iq->iq_name); 508 } 509 510 isa_icu_init(); 511 intr_calculatemasks(); 512 /* something to break the build in an informative way */ 513 #ifndef ISA_FOOTBRIDGE_IRQ 514 #warning Before using isa with footbridge you must define ISA_FOOTBRIDGE_IRQ 515 #endif 516 isa_ih = footbridge_intr_claim(ISA_FOOTBRIDGE_IRQ, IPL_BIO, "isabus", 517 isa_irqdispatch, NULL); 518 519 } 520 521 /* Static array of ISA DMA segments. We only have one on CATS */ 522 #if NISADMA > 0 523 struct arm32_dma_range machdep_isa_dma_ranges[1]; 524 #endif 525 526 void 527 isa_footbridge_init(iobase, membase) 528 u_int iobase, membase; 529 { 530 #if NISADMA > 0 531 extern struct arm32_dma_range *footbridge_isa_dma_ranges; 532 extern int footbridge_isa_dma_nranges; 533 534 machdep_isa_dma_ranges[0].dr_sysbase = bootconfig.dram[0].address; 535 machdep_isa_dma_ranges[0].dr_busbase = bootconfig.dram[0].address; 536 machdep_isa_dma_ranges[0].dr_len = (16 * 1024 * 1024); 537 538 footbridge_isa_dma_ranges = machdep_isa_dma_ranges; 539 footbridge_isa_dma_nranges = 1; 540 #endif 541 542 isa_io_init(iobase, membase); 543 } 544 545 void 546 isa_attach_hook(parent, self, iba) 547 struct device *parent, *self; 548 struct isabus_attach_args *iba; 549 { 550 /* 551 * Since we can only have one ISA bus, we just use a single 552 * statically allocated ISA chipset structure. Pass it up 553 * now. 554 */ 555 iba->iba_ic = &isa_chipset_tag; 556 #if NISADMA > 0 557 isa_dma_init(); 558 #endif 559 } 560 561 int 562 isa_irqdispatch(arg) 563 void *arg; 564 { 565 struct clockframe *frame = arg; 566 int irq; 567 struct intrq *iq; 568 struct intrhand *ih; 569 u_int iack; 570 int res = 0; 571 572 iack = *((u_int *)(DC21285_PCI_IACK_VBASE)); 573 iack &= 0xff; 574 if (iack < 0x20 || iack > 0x2f) { 575 printf("isa_irqdispatch: %x\n", iack); 576 return(0); 577 } 578 579 irq = iack & 0x0f; 580 iq = &isa_intrq[irq]; 581 iq->iq_ev.ev_count++; 582 for (ih = TAILQ_FIRST(&iq->iq_list); res != 1 && ih != NULL; 583 ih = TAILQ_NEXT(ih, ih_list)) { 584 res = (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 585 } 586 return res; 587 } 588 589 590 void 591 isa_fillw(val, addr, len) 592 u_int val; 593 void *addr; 594 size_t len; 595 { 596 if ((u_int)addr >= isa_mem_data_vaddr() 597 && (u_int)addr < isa_mem_data_vaddr() + 0x100000) { 598 bus_size_t offset = ((u_int)addr) & 0xfffff; 599 bus_space_set_region_2(&isa_mem_bs_tag, 600 (bus_space_handle_t)isa_mem_bs_tag.bs_cookie, offset, 601 val, len); 602 } else { 603 u_short *ptr = addr; 604 605 while (len > 0) { 606 *ptr++ = val; 607 --len; 608 } 609 } 610 } 611
Indexes created Tue Sep 30 20:09:53 GMT 2025