isa_machdep.c revision 1.6.50.5
1 /* $NetBSD: isa_machdep.c,v 1.6.50.5 2008/02/24 13:39:15 chris Exp $ */ 2 3 /*- 4 * Copyright (c) 1996-1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Mark Brinicombe, Charles M. Hannum and by Jason R. Thorpe of the 9 * Numerical Aerospace Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /*- 41 * Copyright (c) 1991 The Regents of the University of California. 42 * All rights reserved. 43 * 44 * This code is derived from software contributed to Berkeley by 45 * William Jolitz. 46 * 47 * Redistribution and use in source and binary forms, with or without 48 * modification, are permitted provided that the following conditions 49 * are met: 50 * 1. Redistributions of source code must retain the above copyright 51 * notice, this list of conditions and the following disclaimer. 52 * 2. Redistributions in binary form must reproduce the above copyright 53 * notice, this list of conditions and the following disclaimer in the 54 * documentation and/or other materials provided with the distribution. 55 * 3. Neither the name of the University nor the names of its contributors 56 * may be used to endorse or promote products derived from this software 57 * without specific prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 60 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 61 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 62 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 63 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 64 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 65 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69 * SUCH DAMAGE. 70 * 71 * @(#)isa.c 7.2 (Berkeley) 5/13/91 72 */ 73 74 #include <sys/cdefs.h> 75 __KERNEL_RCSID(0, "$NetBSD: isa_machdep.c,v 1.6.50.5 2008/02/24 13:39:15 chris Exp $"); 76 77 #include "opt_irqstats.h" 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/syslog.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/proc.h> 86 87 #define _ARM32_BUS_DMA_PRIVATE 88 #include <machine/bus.h> 89 90 #include <machine/intr.h> 91 #include <machine/pio.h> 92 #include <machine/bootconfig.h> 93 #include <machine/isa_machdep.h> 94 95 #include <dev/isa/isareg.h> 96 #include <dev/isa/isavar.h> 97 #include <dev/isa/isadmareg.h> 98 #include <dev/isa/isadmavar.h> 99 #include <arm/footbridge/isa/icu.h> 100 #include <arm/footbridge/dc21285reg.h> 101 #include <arm/footbridge/dc21285mem.h> 102 #include <dev/ic/i8259reg.h> 103 104 #include <uvm/uvm_extern.h> 105 106 #include "isadma.h" 107 108 /* prototypes */ 109 static void isa_icu_init __P((void)); 110 111 struct arm32_isa_chipset isa_chipset_tag; 112 113 void isa_strayintr __P((int)); 114 void intr_calculatemasks __P((void)); 115 116 int isa_irqdispatch __P((void *arg)); 117 118 uint32_t imen; 119 120 static void isa_set_irq_mask(uint32_t intr_enabled); 121 static void isa_set_irq_hardware_type(int irq, int type); 122 static struct intrline pic_irqlines[ICU_LEN]; 123 124 static struct pic_softc isa_pic = 125 { 126 .pic_ops.pic_set_irq_hardware_mask = isa_set_irq_mask, 127 .pic_ops.pic_set_irq_hardware_type = isa_set_irq_hardware_type, 128 .pic_nirqs = ICU_LEN, 129 .pic_pre_assigned_irqs = 0xefbf, 130 .pic_name = "isa", 131 .pic_intrlines = pic_irqlines 132 }; 133 134 135 #define AUTO_EOI_1 136 #define AUTO_EOI_2 137 138 /* 139 * Fill in default interrupt table (in case of spuruious interrupt 140 * during configuration of kernel, setup interrupt control unit 141 */ 142 static void 143 isa_icu_init(void) 144 { 145 /* reset; program device, four bytes */ 146 outb(IO_ICU1 + PIC_ICW1, ICW1_SELECT | ICW1_IC4); 147 148 /* starting at this vector index */ 149 outb(IO_ICU1 + PIC_ICW2, ICU_OFFSET); 150 /* slave on line 2 */ 151 outb(IO_ICU1 + PIC_ICW3, ICW3_CASCADE(IRQ_SLAVE)); 152 153 #ifdef AUTO_EOI_1 154 /* auto EOI, 8086 mode */ 155 outb(IO_ICU1 + PIC_ICW4, ICW4_AEOI | ICW4_8086); 156 #else 157 /* 8086 mode */ 158 outb(IO_ICU1 + PIC_ICW4, ICW4_8086); 159 #endif 160 /* leave interrupts masked */ 161 outb(IO_ICU1 + PIC_OCW1, 0xff); 162 /* special mask mode (if available) */ 163 outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM); 164 /* Read IRR by default. */ 165 outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_RR); 166 #ifdef REORDER_IRQ 167 /* pri order 3-7, 0-2 (com2 first) */ 168 outb(IO_ICU1 + PIC_OCW2, OCW2_SELECT | OCW2_R | OCW2_SL | 169 OCW2_ILS(3 - 1)); 170 #endif 171 172 /* reset; program device, four bytes */ 173 outb(IO_ICU2 + PIC_ICW1, ICW1_SELECT | ICW1_IC4); 174 175 /* staring at this vector index */ 176 outb(IO_ICU2 + PIC_ICW2, ICU_OFFSET + 8); 177 /* slave connected to line 2 of master */ 178 outb(IO_ICU2 + PIC_ICW3, ICW3_SIC(IRQ_SLAVE)); 179 #ifdef AUTO_EOI_2 180 /* auto EOI, 8086 mode */ 181 outb(IO_ICU2 + PIC_ICW4, ICW4_AEOI | ICW4_8086); 182 #else 183 /* 8086 mode */ 184 outb(IO_ICU2 + PIC_ICW4, ICW4_8086); 185 #endif 186 /* leave interrupts masked */ 187 outb(IO_ICU2 + PIC_OCW1, 0xff); 188 /* special mask mode (if available) */ 189 outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM); 190 /* Read IRR by default. */ 191 outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_RR); 192 } 193 194 /* 195 * Caught a stray interrupt, notify 196 */ 197 void 198 isa_strayintr(irq) 199 int irq; 200 { 201 static u_long strays; 202 203 /* 204 * Stray interrupts on irq 7 occur when an interrupt line is raised 205 * and then lowered before the CPU acknowledges it. This generally 206 * means either the device is screwed or something is cli'ing too 207 * long and it's timing out. 208 */ 209 if (++strays <= 5) 210 log(LOG_ERR, "stray interrupt %d%s\n", irq, 211 strays >= 5 ? "; stopped logging" : ""); 212 } 213 214 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2) 215 216 int 217 isa_intr_alloc(ic, mask, type, irq) 218 isa_chipset_tag_t ic; 219 int mask; 220 int type; 221 int *irq; 222 { 223 int i, tmp, bestirq, count; 224 struct intrline *il; 225 struct intrhand *ih; 226 227 if (type == IST_NONE) 228 panic("intr_alloc: bogus type"); 229 230 bestirq = -1; 231 count = -1; 232 233 /* some interrupts should never be dynamically allocated */ 234 mask &= 0xdef8; 235 236 /* 237 * XXX some interrupts will be used later (6 for fdc, 12 for pms). 238 * the right answer is to do "breadth-first" searching of devices. 239 */ 240 mask &= 0xefbf; 241 242 for (i = 0; i < ICU_LEN; i++) { 243 if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0) 244 continue; 245 246 /* XXX shouldn't expose internals of arm_intr here */ 247 il = &(isa_pic.pic_intrlines[i]); 248 switch(il->il_ist) { 249 case IST_NONE: 250 /* 251 * if nothing's using the irq, just return it 252 */ 253 *irq = i; 254 return (0); 255 256 case IST_EDGE: 257 case IST_LEVEL: 258 if (type != il->il_ist) 259 continue; 260 /* 261 * if the irq is shareable, count the number of other 262 * handlers, and if it's smaller than the last irq like 263 * this, remember it 264 * 265 * XXX We should probably also consider the 266 * interrupt level and stick IPL_TTY with other 267 * IPL_TTY, etc. 268 */ 269 tmp = 0; 270 TAILQ_FOREACH(ih, &(il->il_handler_list), ih_list) 271 tmp++; 272 if ((bestirq == -1) || (count > tmp)) { 273 bestirq = i; 274 count = tmp; 275 } 276 break; 277 278 case IST_PULSE: 279 /* this just isn't shareable */ 280 continue; 281 } 282 } 283 284 if (bestirq == -1) 285 return (1); 286 287 *irq = bestirq; 288 289 return (0); 290 } 291 292 const struct evcnt * 293 isa_intr_evcnt(isa_chipset_tag_t ic, int irq) 294 { 295 return arm_intr_evcnt(&isa_pic, irq); 296 } 297 298 /* 299 * Set up an interrupt handler to start being called. 300 * XXX PRONE TO RACE CONDITIONS, UGLY, 'INTERESTING' INSERTION ALGORITHM. 301 */ 302 void * 303 isa_intr_establish(ic, irq, type, level, ih_fun, ih_arg) 304 isa_chipset_tag_t ic; 305 int irq; 306 int type; 307 int level; 308 int (*ih_fun) __P((void *)); 309 void *ih_arg; 310 { 311 if (!LEGAL_IRQ(irq) || type == IST_NONE) 312 panic("intr_establish: bogus irq or type"); 313 314 return arm_intr_claim(&isa_pic, irq, type, level, NULL, ih_fun, ih_arg); 315 } 316 317 /* 318 * Deregister an interrupt handler. 319 */ 320 void 321 isa_intr_disestablish(ic, arg) 322 isa_chipset_tag_t ic; 323 void *arg; 324 { 325 return arm_intr_disestablish(&isa_pic, arg); 326 } 327 328 static void 329 isa_set_irq_mask(uint32_t intr_enabled) 330 { 331 uint32_t oldirqstate; 332 333 oldirqstate = disable_interrupts(I32_bit); 334 /* slave is always enabled */ 335 imen = ~(intr_enabled | (1 << IRQ_SLAVE)); 336 imen &=0xffff; 337 SET_ICUS(); 338 restore_interrupts(oldirqstate); 339 } 340 341 static void 342 isa_set_irq_hardware_type(int irq, int type) 343 { 344 /* irq trigger types are setup in the m1543 */ 345 if (irq < 8) { 346 outb(0x4d0, (inb(0x4d0) & ~(1 << irq)) 347 | ((type == IST_LEVEL) ? (1 << irq) : 0)); 348 } else { 349 outb(0x4d1, (inb(0x4d1) & ~(1 << irq)) 350 | ((type == IST_LEVEL) ? (1 << irq) : 0)); 351 } 352 } 353 354 /* 355 * isa_intr_init() 356 * 357 * Initialise the ISA ICU and attach an ISA interrupt handler to the 358 * ISA interrupt line on the footbridge. 359 */ 360 void 361 isa_intr_init(void) 362 { 363 static void *isa_ih; 364 365 isa_icu_init(); 366 367 arm_intr_register_pic(&isa_pic); 368 369 /* something to break the build in an informative way */ 370 #ifndef ISA_FOOTBRIDGE_IRQ 371 #warning Before using isa with footbridge you must define ISA_FOOTBRIDGE_IRQ 372 #endif 373 isa_ih = footbridge_intr_claim(ISA_FOOTBRIDGE_IRQ, IPL_IRQBUS, "isabus", 374 isa_irqdispatch, NULL); 375 376 } 377 378 /* Static array of ISA DMA segments. We only have one on CATS */ 379 #if NISADMA > 0 380 struct arm32_dma_range machdep_isa_dma_ranges[1]; 381 #endif 382 383 void 384 isa_footbridge_init(iobase, membase) 385 u_int iobase, membase; 386 { 387 #if NISADMA > 0 388 extern struct arm32_dma_range *footbridge_isa_dma_ranges; 389 extern int footbridge_isa_dma_nranges; 390 391 machdep_isa_dma_ranges[0].dr_sysbase = bootconfig.dram[0].address; 392 machdep_isa_dma_ranges[0].dr_busbase = bootconfig.dram[0].address; 393 machdep_isa_dma_ranges[0].dr_len = (16 * 1024 * 1024); 394 395 footbridge_isa_dma_ranges = machdep_isa_dma_ranges; 396 footbridge_isa_dma_nranges = 1; 397 #endif 398 399 isa_io_init(iobase, membase); 400 } 401 402 void 403 isa_attach_hook(parent, self, iba) 404 struct device *parent, *self; 405 struct isabus_attach_args *iba; 406 { 407 /* 408 * Since we can only have one ISA bus, we just use a single 409 * statically allocated ISA chipset structure. Pass it up 410 * now. 411 */ 412 iba->iba_ic = &isa_chipset_tag; 413 #if NISADMA > 0 414 isa_dma_init(); 415 #endif 416 } 417 418 int 419 isa_irqdispatch(arg) 420 void *arg; 421 { 422 uint32_t ipendingmask; 423 uint32_t oldirqstate; 424 425 /* disable irqs while reading from the ICUs 426 * Note that this could be an splhigh, except that serial ports 427 * attach to isa, and so they wouldn't be blocked */ 428 oldirqstate = disable_interrupts(I32_bit); 429 430 /* read from the isa registers */ 431 ipendingmask = inb(IO_ICU1); 432 433 if (ipendingmask & (1 << IRQ_SLAVE)) 434 { 435 ipendingmask &= ~(1 << IRQ_SLAVE); 436 ipendingmask |= inb(IO_ICU2) << 8; 437 } 438 restore_interrupts(oldirqstate); 439 440 /* 441 * Setup the interrupts into the ipl lists. 442 * They'll be processed later, as the only way to get here is from 443 * an interrupt 444 */ 445 arm_intr_queue_irqs(&isa_pic, ipendingmask); 446 447 return 1; 448 } 449 450 451 void 452 isa_fillw(val, addr, len) 453 u_int val; 454 void *addr; 455 size_t len; 456 { 457 if ((u_int)addr >= isa_mem_data_vaddr() 458 && (u_int)addr < isa_mem_data_vaddr() + 0x100000) { 459 bus_size_t offset = ((u_int)addr) & 0xfffff; 460 bus_space_set_region_2(&isa_mem_bs_tag, 461 (bus_space_handle_t)isa_mem_bs_tag.bs_cookie, offset, 462 val, len); 463 } else { 464 u_short *ptr = addr; 465 466 while (len > 0) { 467 *ptr++ = val; 468 --len; 469 } 470 } 471 } 472
Indexes created Thu Oct 23 22:10:10 GMT 2025