isa_machdep.c revision 1.9
1 /* $NetBSD: isa_machdep.c,v 1.9 2009/03/14 14:45:55 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1996-1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Mark Brinicombe, Charles M. Hannum and by Jason R. Thorpe of the 9 * Numerical Aerospace Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1991 The Regents of the University of California. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to Berkeley by 38 * William Jolitz. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. Neither the name of the University nor the names of its contributors 49 * may be used to endorse or promote products derived from this software 50 * without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 53 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 54 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 55 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 56 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 57 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 58 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 59 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 60 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 61 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 62 * SUCH DAMAGE. 63 * 64 * @(#)isa.c 7.2 (Berkeley) 5/13/91 65 */ 66 67 #include <sys/cdefs.h> 68 __KERNEL_RCSID(0, "$NetBSD: isa_machdep.c,v 1.9 2009/03/14 14:45:55 dsl Exp $"); 69 70 #include "opt_irqstats.h" 71 72 #include <sys/param.h> 73 #include <sys/systm.h> 74 #include <sys/kernel.h> 75 #include <sys/syslog.h> 76 #include <sys/device.h> 77 #include <sys/malloc.h> 78 #include <sys/proc.h> 79 80 #define _ARM32_BUS_DMA_PRIVATE 81 #include <machine/bus.h> 82 83 #include <machine/intr.h> 84 #include <machine/pio.h> 85 #include <machine/bootconfig.h> 86 #include <machine/isa_machdep.h> 87 88 #include <dev/isa/isareg.h> 89 #include <dev/isa/isavar.h> 90 #include <dev/isa/isadmareg.h> 91 #include <dev/isa/isadmavar.h> 92 #include <arm/footbridge/isa/icu.h> 93 #include <arm/footbridge/dc21285reg.h> 94 #include <arm/footbridge/dc21285mem.h> 95 96 #include <uvm/uvm_extern.h> 97 98 #include "isadma.h" 99 100 /* prototypes */ 101 static void isa_icu_init(void); 102 103 struct arm32_isa_chipset isa_chipset_tag; 104 105 void isa_strayintr(int); 106 void intr_calculatemasks(void); 107 int fakeintr(void *); 108 109 int isa_irqdispatch(void *arg); 110 111 u_int imask[NIPL]; 112 unsigned imen; 113 114 #define AUTO_EOI_1 115 #define AUTO_EOI_2 116 117 /* 118 * Fill in default interrupt table (in case of spuruious interrupt 119 * during configuration of kernel, setup interrupt control unit 120 */ 121 static void 122 isa_icu_init(void) 123 { 124 /* initialize 8259's */ 125 outb(IO_ICU1, 0x11); /* reset; program device, four bytes */ 126 outb(IO_ICU1+1, ICU_OFFSET); /* starting at this vector index */ 127 outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */ 128 #ifdef AUTO_EOI_1 129 outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */ 130 #else 131 outb(IO_ICU1+1, 1); /* 8086 mode */ 132 #endif 133 outb(IO_ICU1+1, 0xff); /* leave interrupts masked */ 134 outb(IO_ICU1, 0x68); /* special mask mode (if available) */ 135 outb(IO_ICU1, 0x0a); /* Read IRR by default. */ 136 #ifdef REORDER_IRQ 137 outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */ 138 #endif 139 140 outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ 141 outb(IO_ICU2+1, ICU_OFFSET+8); /* staring at this vector index */ 142 outb(IO_ICU2+1, IRQ_SLAVE); 143 #ifdef AUTO_EOI_2 144 outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */ 145 #else 146 outb(IO_ICU2+1, 1); /* 8086 mode */ 147 #endif 148 outb(IO_ICU2+1, 0xff); /* leave interrupts masked */ 149 outb(IO_ICU2, 0x68); /* special mask mode (if available) */ 150 outb(IO_ICU2, 0x0a); /* Read IRR by default. */ 151 } 152 153 /* 154 * Caught a stray interrupt, notify 155 */ 156 void 157 isa_strayintr(irq) 158 int irq; 159 { 160 static u_long strays; 161 162 /* 163 * Stray interrupts on irq 7 occur when an interrupt line is raised 164 * and then lowered before the CPU acknowledges it. This generally 165 * means either the device is screwed or something is cli'ing too 166 * long and it's timing out. 167 */ 168 if (++strays <= 5) 169 log(LOG_ERR, "stray interrupt %d%s\n", irq, 170 strays >= 5 ? "; stopped logging" : ""); 171 } 172 173 static struct intrq isa_intrq[ICU_LEN]; 174 175 /* 176 * Recalculate the interrupt masks from scratch. 177 * We could code special registry and deregistry versions of this function that 178 * would be faster, but the code would be nastier, and we don't expect this to 179 * happen very much anyway. 180 */ 181 void 182 intr_calculatemasks() 183 { 184 int irq, level; 185 struct intrq *iq; 186 struct intrhand *ih; 187 188 /* First, figure out which levels each IRQ uses. */ 189 for (irq = 0; irq < ICU_LEN; irq++) { 190 int levels = 0; 191 iq = &isa_intrq[irq]; 192 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 193 ih = TAILQ_NEXT(ih, ih_list)) 194 levels |= (1U << ih->ih_ipl); 195 iq->iq_levels = levels; 196 } 197 198 /* Then figure out which IRQs use each level. */ 199 for (level = 0; level < NIPL; level++) { 200 int irqs = 0; 201 for (irq = 0; irq < ICU_LEN; irq++) 202 if (isa_intrq[irq].iq_levels & (1U << level)) 203 irqs |= (1U << irq); 204 imask[level] = irqs; 205 } 206 207 imask[IPL_NONE] = 0; 208 imask[IPL_SOFTCLOCK] |= imask[IPL_NONE]; 209 imask[IPL_SOFTBIO] |= imask[IPL_SOFTCLOCK]; 210 imask[IPL_SOFTNET] |= imask[IPL_SOFTBIO]; 211 imask[IPL_SOFTSERIAL] |= imask[IPL_SOFTNET]; 212 imask[IPL_VM] |= imask[IPL_SOFTSERIAL]; 213 imask[IPL_SCHED] |= imask[IPL_VM]; 214 imask[IPL_HIGH] |= imask[IPL_SCHED]; 215 216 /* And eventually calculate the complete masks. */ 217 for (irq = 0; irq < ICU_LEN; irq++) { 218 int irqs = 1 << irq; 219 iq = &isa_intrq[irq]; 220 for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL; 221 ih = TAILQ_NEXT(ih, ih_list)) 222 irqs |= imask[ih->ih_ipl]; 223 iq->iq_mask = irqs; 224 } 225 226 /* Lastly, determine which IRQs are actually in use. */ 227 { 228 int irqs = 0; 229 for (irq = 0; irq < ICU_LEN; irq++) 230 if (!TAILQ_EMPTY(&isa_intrq[irq].iq_list)) 231 irqs |= (1U << irq); 232 if (irqs >= 0x100) /* any IRQs >= 8 in use */ 233 irqs |= 1 << IRQ_SLAVE; 234 imen = ~irqs; 235 SET_ICUS(); 236 } 237 #if 0 238 printf("type\tmask\tlevel\thand\n"); 239 for (irq = 0; irq < ICU_LEN; irq++) { 240 printf("%x\t%04x\t%x\t%p\n", intrtype[irq], intrmask[irq], 241 intrlevel[irq], intrhand[irq]); 242 } 243 for (level = 0; level < IPL_LEVELS; ++level) 244 printf("%d: %08x\n", level, imask[level]); 245 #endif 246 } 247 248 int 249 fakeintr(arg) 250 void *arg; 251 { 252 253 return 0; 254 } 255 256 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2) 257 258 int 259 isa_intr_alloc(ic, mask, type, irq) 260 isa_chipset_tag_t ic; 261 int mask; 262 int type; 263 int *irq; 264 { 265 int i, tmp, bestirq, count; 266 struct intrq *iq; 267 struct intrhand *ih; 268 269 if (type == IST_NONE) 270 panic("intr_alloc: bogus type"); 271 272 bestirq = -1; 273 count = -1; 274 275 /* some interrupts should never be dynamically allocated */ 276 mask &= 0xdef8; 277 278 /* 279 * XXX some interrupts will be used later (6 for fdc, 12 for pms). 280 * the right answer is to do "breadth-first" searching of devices. 281 */ 282 mask &= 0xefbf; 283 284 for (i = 0; i < ICU_LEN; i++) { 285 if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0) 286 continue; 287 288 iq = &isa_intrq[i]; 289 switch(iq->iq_ist) { 290 case IST_NONE: 291 /* 292 * if nothing's using the irq, just return it 293 */ 294 *irq = i; 295 return (0); 296 297 case IST_EDGE: 298 case IST_LEVEL: 299 if (type != iq->iq_ist) 300 continue; 301 /* 302 * if the irq is shareable, count the number of other 303 * handlers, and if it's smaller than the last irq like 304 * this, remember it 305 * 306 * XXX We should probably also consider the 307 * interrupt level and stick IPL_TTY with other 308 * IPL_TTY, etc. 309 */ 310 tmp = 0; 311 TAILQ_FOREACH(ih, &(iq->iq_list), ih_list) 312 tmp++; 313 if ((bestirq == -1) || (count > tmp)) { 314 bestirq = i; 315 count = tmp; 316 } 317 break; 318 319 case IST_PULSE: 320 /* this just isn't shareable */ 321 continue; 322 } 323 } 324 325 if (bestirq == -1) 326 return (1); 327 328 *irq = bestirq; 329 330 return (0); 331 } 332 333 const struct evcnt * 334 isa_intr_evcnt(isa_chipset_tag_t ic, int irq) 335 { 336 return &isa_intrq[irq].iq_ev; 337 } 338 339 /* 340 * Set up an interrupt handler to start being called. 341 * XXX PRONE TO RACE CONDITIONS, UGLY, 'INTERESTING' INSERTION ALGORITHM. 342 */ 343 void * 344 isa_intr_establish(ic, irq, type, level, ih_fun, ih_arg) 345 isa_chipset_tag_t ic; 346 int irq; 347 int type; 348 int level; 349 int (*ih_fun)(void *); 350 void *ih_arg; 351 { 352 struct intrq *iq; 353 struct intrhand *ih; 354 u_int oldirqstate; 355 356 #if 0 357 printf("isa_intr_establish(%d, %d, %d)\n", irq, type, level); 358 #endif 359 /* no point in sleeping unless someone can free memory. */ 360 ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 361 if (ih == NULL) 362 return (NULL); 363 364 if (!LEGAL_IRQ(irq) || type == IST_NONE) 365 panic("intr_establish: bogus irq or type"); 366 367 iq = &isa_intrq[irq]; 368 369 switch (iq->iq_ist) { 370 case IST_NONE: 371 iq->iq_ist = type; 372 #if 0 373 printf("Setting irq %d to type %d - ", irq, type); 374 #endif 375 if (irq < 8) { 376 outb(0x4d0, (inb(0x4d0) & ~(1 << irq)) 377 | ((type == IST_LEVEL) ? (1 << irq) : 0)); 378 /* printf("%02x\n", inb(0x4d0));*/ 379 } else { 380 outb(0x4d1, (inb(0x4d1) & ~(1 << irq)) 381 | ((type == IST_LEVEL) ? (1 << irq) : 0)); 382 /* printf("%02x\n", inb(0x4d1));*/ 383 } 384 break; 385 case IST_EDGE: 386 case IST_LEVEL: 387 if (iq->iq_ist == type) 388 break; 389 case IST_PULSE: 390 if (type != IST_NONE) 391 panic("intr_establish: can't share %s with %s", 392 isa_intr_typename(iq->iq_ist), 393 isa_intr_typename(type)); 394 break; 395 } 396 397 ih->ih_func = ih_fun; 398 ih->ih_arg = ih_arg; 399 ih->ih_ipl = level; 400 ih->ih_irq = irq; 401 402 /* do not stop us */ 403 oldirqstate = disable_interrupts(I32_bit); 404 405 TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list); 406 407 intr_calculatemasks(); 408 restore_interrupts(oldirqstate); 409 410 return (ih); 411 } 412 413 /* 414 * Deregister an interrupt handler. 415 */ 416 void 417 isa_intr_disestablish(ic, arg) 418 isa_chipset_tag_t ic; 419 void *arg; 420 { 421 struct intrhand *ih = arg; 422 struct intrq *iq = &isa_intrq[ih->ih_irq]; 423 int irq = ih->ih_irq; 424 u_int oldirqstate; 425 426 if (!LEGAL_IRQ(irq)) 427 panic("intr_disestablish: bogus irq"); 428 429 oldirqstate = disable_interrupts(I32_bit); 430 431 TAILQ_REMOVE(&iq->iq_list, ih, ih_list); 432 433 intr_calculatemasks(); 434 435 restore_interrupts(oldirqstate); 436 437 free(ih, M_DEVBUF); 438 439 if (TAILQ_EMPTY(&(iq->iq_list))) 440 iq->iq_ist = IST_NONE; 441 } 442 443 /* 444 * isa_intr_init() 445 * 446 * Initialise the ISA ICU and attach an ISA interrupt handler to the 447 * ISA interrupt line on the footbridge. 448 */ 449 void 450 isa_intr_init(void) 451 { 452 static void *isa_ih; 453 struct intrq *iq; 454 int i; 455 456 /* 457 * should get the parent here, but initialisation order being so 458 * strange I need to check if it's available 459 */ 460 for (i = 0; i < ICU_LEN; i++) { 461 iq = &isa_intrq[i]; 462 TAILQ_INIT(&iq->iq_list); 463 464 sprintf(iq->iq_name, "irq %d", i); 465 evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR, 466 NULL, "isa", iq->iq_name); 467 } 468 469 isa_icu_init(); 470 intr_calculatemasks(); 471 /* something to break the build in an informative way */ 472 #ifndef ISA_FOOTBRIDGE_IRQ 473 #warning Before using isa with footbridge you must define ISA_FOOTBRIDGE_IRQ 474 #endif 475 isa_ih = footbridge_intr_claim(ISA_FOOTBRIDGE_IRQ, IPL_BIO, "isabus", 476 isa_irqdispatch, NULL); 477 478 } 479 480 /* Static array of ISA DMA segments. We only have one on CATS */ 481 #if NISADMA > 0 482 struct arm32_dma_range machdep_isa_dma_ranges[1]; 483 #endif 484 485 void 486 isa_footbridge_init(iobase, membase) 487 u_int iobase, membase; 488 { 489 #if NISADMA > 0 490 extern struct arm32_dma_range *footbridge_isa_dma_ranges; 491 extern int footbridge_isa_dma_nranges; 492 493 machdep_isa_dma_ranges[0].dr_sysbase = bootconfig.dram[0].address; 494 machdep_isa_dma_ranges[0].dr_busbase = bootconfig.dram[0].address; 495 machdep_isa_dma_ranges[0].dr_len = (16 * 1024 * 1024); 496 497 footbridge_isa_dma_ranges = machdep_isa_dma_ranges; 498 footbridge_isa_dma_nranges = 1; 499 #endif 500 501 isa_io_init(iobase, membase); 502 } 503 504 void 505 isa_attach_hook(parent, self, iba) 506 struct device *parent, *self; 507 struct isabus_attach_args *iba; 508 { 509 /* 510 * Since we can only have one ISA bus, we just use a single 511 * statically allocated ISA chipset structure. Pass it up 512 * now. 513 */ 514 iba->iba_ic = &isa_chipset_tag; 515 #if NISADMA > 0 516 isa_dma_init(); 517 #endif 518 } 519 520 int 521 isa_irqdispatch(arg) 522 void *arg; 523 { 524 struct clockframe *frame = arg; 525 int irq; 526 struct intrq *iq; 527 struct intrhand *ih; 528 u_int iack; 529 int res = 0; 530 531 iack = *((u_int *)(DC21285_PCI_IACK_VBASE)); 532 iack &= 0xff; 533 if (iack < 0x20 || iack > 0x2f) { 534 printf("isa_irqdispatch: %x\n", iack); 535 return(0); 536 } 537 538 irq = iack & 0x0f; 539 iq = &isa_intrq[irq]; 540 iq->iq_ev.ev_count++; 541 for (ih = TAILQ_FIRST(&iq->iq_list); res != 1 && ih != NULL; 542 ih = TAILQ_NEXT(ih, ih_list)) { 543 res = (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame); 544 } 545 return res; 546 } 547 548 549 void 550 isa_fillw(val, addr, len) 551 u_int val; 552 void *addr; 553 size_t len; 554 { 555 if ((u_int)addr >= isa_mem_data_vaddr() 556 && (u_int)addr < isa_mem_data_vaddr() + 0x100000) { 557 bus_size_t offset = ((u_int)addr) & 0xfffff; 558 bus_space_set_region_2(&isa_mem_bs_tag, 559 (bus_space_handle_t)isa_mem_bs_tag.bs_cookie, offset, 560 val, len); 561 } else { 562 u_short *ptr = addr; 563 564 while (len > 0) { 565 *ptr++ = val; 566 --len; 567 } 568 } 569 } 570
Indexes created Tue Sep 30 20:09:53 GMT 2025