gemini_gmacvar.h revision 1.1
1 /* $NetBSD: gemini_gmacvar.h,v 1.1 2008/12/14 01:57:02 matt Exp $ */ 2 /*- 3 * Copyright (c) 2008 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas <matt (at) 3am-software.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef _ARM_GEMINI_GEMINI_GMACVAR_H 32 #define _ARM_GEMINI_GEMINI_GMACVAR_H 33 34 #include <sys/device.h> 35 #include <sys/queue.h> 36 #include <net/if.h> 37 #include <net/if_media.h> 38 #include <dev/mii/mii.h> 39 #include <dev/mii/miivar.h> 40 41 #include <arm/gemini/gemini_gmacreg.h> 42 43 typedef struct gmac_hwqueue gmac_hwqueue_t; 44 typedef struct gmac_hwqmem gmac_hwqmem_t; 45 typedef struct gmac_mapcache gmac_mapcache_t; 46 47 #define MAX_TXMAPS 256 48 #define MIN_TXMAPS 16 49 #define MAX_RXMAPS 256 50 #define MIN_RXMAPS 32 51 52 #define RXQ_NDESCS 128 53 #define TXQ_NDESCS 128 54 55 struct gmac_mapcache { 56 bus_dma_tag_t mc_dmat; 57 bus_size_t mc_mapsize; 58 size_t mc_nsegs; 59 size_t mc_free; 60 size_t mc_used; 61 size_t mc_max; 62 bus_dmamap_t mc_maps[0]; 63 }; 64 65 struct gmac_softc { 66 device_t sc_dev; 67 bus_space_tag_t sc_iot; 68 bus_space_handle_t sc_ioh; 69 bus_dma_tag_t sc_dmat; 70 71 /* 72 * MDIO state 73 */ 74 kmutex_t sc_mdiolock; 75 uint32_t sc_mdiobits; 76 device_t sc_gpio_dev; 77 uint8_t sc_gpio_mdclk; 78 uint8_t sc_gpio_mdin; 79 uint8_t sc_gpio_mdout; 80 81 /* 82 * What GMAC ports have attached? 83 */ 84 uint8_t sc_ports; 85 uint8_t sc_running; 86 87 /* 88 * The hardware free queue and software free queue are shared 89 * resources. As are the dmamap caches. 90 */ 91 gmac_hwqueue_t *sc_swfreeq; 92 gmac_hwqueue_t *sc_hwfreeq; 93 gmac_mapcache_t *sc_rxmaps; 94 gmac_mapcache_t *sc_txmaps; 95 96 /* 97 * What interrupts are enabled for both ports? 98 */ 99 uint32_t sc_int_enabled[5]; 100 uint32_t sc_int_select[5]; 101 }; 102 103 struct gmac_attach_args { 104 bus_space_tag_t gma_iot; 105 bus_space_handle_t gma_ioh; 106 bus_dma_tag_t gma_dmat; 107 108 int gma_port; 109 int gma_phy; 110 int gma_intr; 111 112 mii_readreg_t gma_mii_readreg; 113 mii_writereg_t gma_mii_writereg; 114 }; 115 116 struct gmac_hwqmem { 117 bus_dma_tag_t hqm_dmat; 118 bus_dmamap_t hqm_dmamap; 119 gmac_mapcache_t *hqm_mc; 120 gmac_desc_t *hqm_base; 121 bus_size_t hqm_memsize; 122 bus_dma_segment_t hqm_segs[1]; 123 size_t hqm_ndesc; 124 size_t hqm_nqueue; 125 int hqm_nsegs; 126 uint8_t hqm_refs; 127 uint8_t hqm_flags; 128 #define HQM_TX 0x0001 129 #define HQM_RX 0x0000 130 #define HQM_PRODUCER 0x0002 131 #define HQM_CONSUMER 0x0000 132 }; 133 134 struct gmac_hwqueue { 135 gmac_desc_t *hwq_base; 136 gmac_hwqmem_t *hwq_hqm; 137 union { 138 SLIST_ENTRY(gmac_hwqueue) qun_link; 139 SLIST_HEAD(,gmac_hwqueue) qun_producers; 140 struct gmac_hwqueue *qun_producer; 141 } hwq_qun; 142 #define hwq_link hwq_qun.qun_link 143 #define hwq_producers hwq_qun.qun_producers 144 #define hwq_producer hwq_qun.qun_producer 145 struct ifnet *hwq_ifp; 146 struct ifqueue hwq_ifq; 147 struct mbuf *hwq_rxmbuf; 148 struct mbuf **hwq_mp; 149 bus_space_tag_t hwq_iot; 150 bus_space_handle_t hwq_qrwptr_ioh; 151 /* 152 * These are in units of gmac_desc_t, not bytes. 153 */ 154 size_t hwq_qoff; /* offset in descriptors to start */ 155 uint16_t hwq_wptr; /* next descriptor to write */ 156 uint16_t hwq_rptr; /* next descriptor to read */ 157 uint16_t hwq_free; /* descriptors can be produced */ 158 uint16_t hwq_size; /* total number of descriptors */ 159 uint8_t hwq_ref; 160 }; 161 162 #ifdef _KERNEL 163 gmac_hwqmem_t * 164 gmac_hwqmem_create(gmac_mapcache_t *, size_t, size_t, int); 165 void gmac_hwqmem_destroy(gmac_hwqmem_t *); 166 167 void gmac_hwqueue_destroy(gmac_hwqueue_t *); 168 gmac_hwqueue_t * 169 gmac_hwqueue_create(gmac_hwqmem_t *, bus_space_tag_t, 170 bus_space_handle_t, bus_size_t, bus_size_t, size_t); 171 172 gmac_desc_t * 173 gmac_hwqueue_desc(gmac_hwqueue_t *, size_t); 174 void gmac_hwqueue_sync(gmac_hwqueue_t *); 175 void gmac_hwqueue_consume(gmac_hwqueue_t *); 176 void gmac_hwqueue_produce(gmac_hwqueue_t *, size_t); 177 178 gmac_mapcache_t * 179 gmac_mapcache_create(bus_dma_tag_t, size_t, bus_size_t, int); 180 void gmac_mapcache_destroy(gmac_mapcache_t **); 181 int gmac_mapcache_fill(gmac_mapcache_t *, size_t); 182 bus_dmamap_t 183 gmac_mapcache_get(gmac_mapcache_t *); 184 void gmac_mapcache_put(gmac_mapcache_t *, bus_dmamap_t); 185 186 void gmac_intr_update(struct gmac_softc *); 187 #endif 188 189 #endif /* _ARM_GEMINI_GEMINI_GMACVAR_H */ 190
Indexes created Tue Oct 14 11:09:46 GMT 2025