1 1.1.4.2 mjf /* $NetBSD: gemini_ipmvar.h,v 1.1.4.2 2009/01/17 13:27:52 mjf Exp $ */ 2 1.1.4.2 mjf 3 1.1.4.2 mjf #ifndef _GEMINI_IPMVAR_H_ 4 1.1.4.2 mjf #define _GEMINI_IPMVAR_H_ 5 1.1.4.2 mjf 6 1.1.4.2 mjf /* 7 1.1.4.2 mjf * message queue 8 1.1.4.2 mjf * 9 1.1.4.2 mjf * - the queue gets located in memory shared between cores 10 1.1.4.2 mjf * - is mapped non-cached so SW coherency is not required. 11 1.1.4.2 mjf * - be sure ipm_queue_t starts on 32 bit (min) boundary to align descriptors 12 1.1.4.2 mjf * - note that indicies are 8 bit and NIPMDESC < (1<<8) 13 1.1.4.2 mjf * be sure to adjust typedef if size is increased 14 1.1.4.2 mjf * - current sizes, typedef, and padding make sizeof(ipm_queue_t) == 4096 15 1.1.4.2 mjf */ 16 1.1.4.2 mjf typedef uint32_t ipmqindex_t; 17 1.1.4.2 mjf #define NIPMDESC 255 18 1.1.4.2 mjf #define IPMQPADSZ (4096 - ((sizeof(ipm_desc_t) * NIPMDESC) + (2 * sizeof(ipmqindex_t)))) 19 1.1.4.2 mjf typedef struct ipm_queue { 20 1.1.4.2 mjf ipm_desc_t ipm_desc[NIPMDESC]; 21 1.1.4.2 mjf volatile ipmqindex_t ix_write; /* writer increments and inserts here */ 22 1.1.4.2 mjf volatile ipmqindex_t ix_read; /* reader extracts here and increments */ 23 1.1.4.2 mjf uint8_t pad[IPMQPADSZ]; 24 1.1.4.2 mjf } ipm_queue_t; 25 1.1.4.2 mjf 26 1.1.4.2 mjf static inline ipmqindex_t 27 1.1.4.2 mjf ipmqnext(ipmqindex_t ix) 28 1.1.4.2 mjf { 29 1.1.4.2 mjf if (++ix >= NIPMDESC) 30 1.1.4.2 mjf ix = 0; 31 1.1.4.2 mjf return ix; 32 1.1.4.2 mjf } 33 1.1.4.2 mjf 34 1.1.4.2 mjf static inline bool 35 1.1.4.2 mjf ipmqisempty(ipmqindex_t ixr, ipmqindex_t ixw) 36 1.1.4.2 mjf { 37 1.1.4.2 mjf if (ixr == ixw) 38 1.1.4.2 mjf return TRUE; 39 1.1.4.2 mjf return FALSE; 40 1.1.4.2 mjf } 41 1.1.4.2 mjf 42 1.1.4.2 mjf static inline bool 43 1.1.4.2 mjf ipmqisfull(ipmqindex_t ixr, ipmqindex_t ixw) 44 1.1.4.2 mjf { 45 1.1.4.2 mjf if (ipmqnext(ixw) == ixr) 46 1.1.4.2 mjf return TRUE; 47 1.1.4.2 mjf return FALSE; 48 1.1.4.2 mjf } 49 1.1.4.2 mjf 50 1.1.4.2 mjf #endif /* _GEMINI_IPMVAR_H_ */ 51