gemini_reg.h revision 1.1
1 /* $NetBSD: gemini_reg.h,v 1.1 2008/10/24 04:23:18 matt Exp $ */ 2 3 #ifndef _ARM_GEMINI_REG_H_ 4 #define _ARM_GEMINI_REG_H_ 5 6 /* 7 * Register definitions for Gemini SOC 8 */ 9 10 #include "opt_gemini.h" 11 #include <machine/endian.h> 12 #include <sys/cdefs.h> 13 14 #if defined(SL3516) 15 /* 16 * Gemini SL3516 memory map 17 */ 18 #define GEMINI_SRAM_BASE 0x00000000 /* Internal SRAM */ 19 #define GEMINI_SRAM_SIZE 0x10000000 /* 128 MB */ 20 #define GEMINI_DRAM_BASE 0x10000000 /* DRAM (via DDR Control Module) */ 21 #define GEMINI_DRAM_SIZE 0x20000000 /* 512 MB */ 22 #define GEMINI_FLASH_BASE 0x30000000 /* DRAM (via DDR Control Module) */ 23 #define GEMINI_FLASH_SIZE 0x10000000 /* 128 MB */ 24 25 /* 26 * Gemini SL3516 device map 27 */ 28 #define GEMINI_GLOBAL_BASE 0x40000000 /* Global registers */ 29 #define GEMINI_WATCHDOG_BASE 0x41000000 /* Watch dog timer module */ 30 #define GEMINI_UART_BASE 0x42000000 /* UART control module */ 31 #define GEMINI_UART_SIZE 0x20 32 #define GEMINI_TIMER_BASE 0x43000000 /* Timer module */ 33 #define GEMINI_LCD_BASE 0x44000000 /* LCD Interface module */ 34 #define GEMINI_RTC_BASE 0x45000000 /* Real Time Clock module */ 35 #define GEMINI_SATA_BASE 0x46000000 /* Serial ATA module */ 36 #define GEMINI_LPCHC_BASE 0x47000000 /* LPC Hosr Controller module */ 37 #define GEMINI_LPCP_BASE 0x47800000 /* LPC Peripherals IO space */ 38 #define GEMINI_IC0_BASE 0x48000000 /* Interrupt Control module #0 */ 39 #define GEMINI_IC1_BASE 0x49000000 /* Interrupt Control module #1 */ 40 #define GEMINI_SSPC_BASE 0x4a000000 /* Synchronous Serial Port Control module */ 41 #define GEMINI_PWRC_BASE 0x4b000000 /* Power Control module */ 42 #define GEMINI_CIR_BASE 0x4c000000 /* CIR Control module */ 43 #define GEMINI_GPIO0_BASE 0x4d000000 /* GPIO module #0 */ 44 #define GEMINI_GPIO1_BASE 0x4e000000 /* GPIO module #1 */ 45 #define GEMINI_GPIO2_BASE 0x4f000000 /* GPIO module #2 */ 46 #define GEMINI_PCICFG_BASE 0x50000000 /* PCI IO, configuration and control space */ 47 #define GEMINI_PCIIO_BASE 0x50001000 /* PCI IO space */ 48 #define GEMINI_PCIIO_SIZE 0x0007f000 /* PCI IO space size */ 49 #define GEMINI_PCIMEM_BASE 0x58000000 /* PCI Memory space */ 50 #define GEMINI_PCIMEM_SIZE 0x08000000 /* PCI Memory space size */ 51 #define GEMINI_NGC_BASE 0x60000000 /* NetEngine & GMAC Configuration registers */ 52 #define GEMINI_SDC_BASE 0x62000000 /* Security DMA and Configure registers */ 53 #define GEMINI_MIDE_BASE 0x63000000 /* Multi IDE registers */ 54 #define GEMINI_RXDC_BASE 0x64000000 /* RAID XOR DMA Configuration registers */ 55 #define GEMINI_FLASHC_BASE 0x65000000 /* Flash Controller registers */ 56 #define GEMINI_DRAMC_BASE 0x66000000 /* DRAM (DDR/SDR) Controller registers */ 57 #define GEMINI_GDMA_BASE 0x67000000 /* General DMA registers */ 58 #define GEMINI_USB0_BASE 0x68000000 /* USB #0 registers */ 59 #define GEMINI_USB1_BASE 0x69000000 /* USB #1 registers */ 60 #define GEMINI_TVE_BASE 0x6a000000 /* TVE registers */ 61 #define GEMINI_SRAM_SHADOW_BASE 0x70000000 /* Shadow of internal SRAM */ 62 63 /* 64 * Gemini SL3516 Watchdog device register offsets and bits 65 */ 66 #define GEMINI_WDT_WDCOUNTER 0x0 /* Watchdog Timer Counter */ /* ro */ 67 #define GEMINI_WDT_WDLOAD 0x4 /* Watchdog Timer Load */ /* rw */ 68 #define WDT_WDLOAD_DFLT 0x3EF1480 /* default Load reg val */ 69 #define GEMINI_WDT_WDRESTART 0x8 /* Watchdog Timer Restart */ /* wo */ 70 #define WDT_WDRESTART_Resv __BITS(31,16) 71 #define WDT_WDRESTART_RST __BITS(15,0) 72 #define WDT_WDRESTART_MAGIC 0x5ab9 73 #define GEMINI_WDT_WDCR 0xc /* Watchdog Timer Control */ /* rw */ 74 #define WDT_WDCR_Resv __BITS(31,5) 75 #define WDT_WDCR_CLKSRC __BIT(4) /* Timer Clock Source: 5 MHz clock */ 76 #define WDCR_CLKSRC_PCLK (0 << 4) /* Timer Clock Source: PCLK (APB CLK) */ 77 #define WDCR_CLKSRC_5MHZ (1 << 4) /* Timer Clock Source: 5 MHz clock */ 78 #define WDT_WDCR_EXTSIG_ENB __BIT(3) /* Timer External Signal Enable */ 79 #define WDT_WDCR_INTR_ENB __BIT(2) /* Timer System Interrupt Enable */ 80 #define WDT_WDCR_RESET_ENB __BIT(1) /* Timer System Reset Enable */ 81 #define WDT_WDCR_ENB __BIT(0) /* Timer Enable */ 82 #define GEMINI_WDT_WDSTATUS 0x10 /* Watchdog Timer Status */ /* ro */ 83 #define WDT_WDSTATUS_Resv __BITS(31,1) 84 #define WDT_WDSTATUS_ZERO __BIT(0) /* non-zero if timer counted down to zero! */ 85 #define GEMINI_WDT_WDCLEAR 0x14 /* Watchdog Timer Clear */ /* wo */ 86 #define WDT_WDCLEAR_Resv __BITS(31,1) 87 #define WDT_WDCLEAR_CLEAR __BIT(0) /* write this bit to clear Status */ 88 #define GEMINI_WDT_WDINTERLEN 0x18 /* Watchdog Timer Interrupt Length */ /* rw */ 89 /* duration of signal assertion, */ 90 /* in units of clock cycles */ 91 #define WDT_WDINTERLEN_DFLT 0xff /* default is 256 cycles */ 92 93 94 /* 95 * Gemini SL3516 Timer device register offsets and bits 96 * 97 * have 3 timers, here indexed 1<=(n)<=3 as in the doc 98 * each has 4 sequential 32bit rw regs 99 */ 100 #define GEMINI_NTIMERS 3 101 #define GEMINI_TIMERn_REG(n, o) ((((n) - 1) * 0x10) + (o)) 102 #define GEMINI_TIMERn_COUNTER(n) GEMINI_TIMERn_REG((n), 0x0) /* rw */ 103 #define GEMINI_TIMERn_LOAD(n) GEMINI_TIMERn_REG((n), 0x4) /* rw */ 104 #define GEMINI_TIMERn_MATCH1(n) GEMINI_TIMERn_REG((n), 0x08) /* rw */ 105 #define GEMINI_TIMERn_MATCH2(n) GEMINI_TIMERn_REG((n), 0x0C) /* rw */ 106 #define GEMINI_TIMER_TMCR 0x30 /* rw */ 107 #define TIMER_TMCR_Resv __BITS(31,12) 108 #define TIMER_TMCR_TMnUPDOWN(n) __BIT(9 + (n) - 1) 109 #define TIMER_TMCR_TMnOFENABLE(n) __BIT((((n) - 1) * 3) + 2) 110 #define TIMER_TMCR_TMnCLOCK(n) __BIT((((n) - 1) * 3) + 1) 111 #define TIMER_TMCR_TMnENABLE(n) __BIT((((n) - 1) * 3) + 0) 112 #define GEMINI_TIMER_TMnCR_MASK(n) \ 113 ( TIMER_TMCR_TMnUPDOWN(n) \ 114 | TIMER_TMCR_TMnOFENABLE(n) \ 115 | TIMER_TMCR_TMnCLOCK(n) \ 116 | TIMER_TMCR_TMnENABLE(n) ) 117 #define GEMINI_TIMER_INTRSTATE 0x34 /* rw */ 118 #define TIMER_INTRSTATE_Resv __BITS(31,9) 119 #define TIMER_INTRSTATE_TMnOVFLOW(n) __BIT((((n) -1) * 3) + 2) 120 #define TIMER_INTRSTATE_TMnMATCH2(n) __BIT((((n) -1) * 3) + 1) 121 #define TIMER_INTRSTATE_TMnMATCH1(n) __BIT((((n) -1) * 3) + 0) 122 #define GEMINI_TIMER_INTRMASK 0x38 /* rw */ 123 #define TIMER_INTRMASK_Resv __BITS(31,9) 124 #define TIMER_INTRMASK_TMnOVFLOW(n) __BIT((((n) -1) * 3) + 2) 125 #define TIMER_INTRMASK_TMnMATCH2(n) __BIT((((n) -1) * 3) + 1) 126 #define TIMER_INTRMASK_TMnMATCH1(n) __BIT((((n) -1) * 3) + 0) 127 #define GEMINI_TIMERn_INTRMASK(n) \ 128 ( TIMER_INTRMASK_TMnOVFLOW(n) \ 129 | TIMER_INTRMASK_TMnMATCH2(n) \ 130 | TIMER_INTRMASK_TMnMATCH1(n) ) 131 132 /* 133 * Gemini SL3516 Interrupt Controller device register offsets and bits 134 */ 135 #define GEMINI_ICU_IRQ_SOURCE 0x0 /* ro */ 136 #define GEMINI_ICU_IRQ_ENABLE 0x4 /* rw */ 137 #define GEMINI_ICU_IRQ_CLEAR 0x8 /* wo */ 138 #define GEMINI_ICU_IRQ_TRIGMODE 0xc /* rw */ 139 #define ICU_IRQ_TRIGMODE_EDGE 1 /* edge triggered */ 140 #define ICU_IRQ_TRIGMODE_LEVEL 0 /* level triggered */ 141 #define GEMINI_ICU_IRQ_TRIGLEVEL 0x10 /* rw */ 142 #define ICU_IRQ_TRIGLEVEL_LO 1 /* active low or falling edge */ 143 #define ICU_IRQ_TRIGLEVEL_HI 0 /* active high or rising edge */ 144 #define GEMINI_ICU_IRQ_STATUS 0x14 /* ro */ 145 146 #define GEMINI_ICU_FIQ_SOURCE 0x20 /* ro */ 147 #define GEMINI_ICU_FIQ_ENABLE 0x24 /* rw */ 148 #define GEMINI_ICU_FIQ_CLEAR 0x28 /* wo */ 149 #define GEMINI_ICU_FIQ_TRIGMODE 0x2c /* rw */ 150 #define GEMINI_ICU_FIQ_TRIGLEVEL 0x30 /* rw */ 151 #define GEMINI_ICU_FIQ_STATUS 0x34 /* ro */ 152 153 #define GEMINI_ICU_REVISION 0x50 /* ro */ 154 #define GEMINI_ICU_INPUT_NUM 0x54 /* ro */ 155 #define ICU_INPUT_NUM_RESV __BITS(31,16) 156 #define ICU_INPUT_NUM_IRQ __BITS(15,8) 157 #define ICU_INPUT_NUM_FIQ __BITS(7,0) 158 #define GEMINI_ICU_IRQ_DEBOUNCE 0x58 /* ro */ 159 #define GEMINI_ICU_FIQ_DEBOUNCE 0x5c /* ro */ 160 161 162 /* 163 * Gemini PCI controller register offsets and bits 164 */ 165 #define GEMINI_PCI_IOSIZE 0x00 /* I/O Space Size */ /* rw */ 166 #define GEMINI_PCI_PROT 0x04 /* AHB Protection */ /* rw */ 167 #define GEMINI_PCI_PCICTRL 0x08 /* PCI Control Signal */ /* rw */ 168 #define GEMINI_PCI_ERREN 0x0c /* Soft Reset Counter and 169 * Response Error Enable */ /* rw */ 170 #define GEMINI_PCI_SOFTRST 0x10 /* Soft Reset */ 171 #define GEMINI_PCI_CFG_CMD 0x28 /* PCI Configuration Command */ /* rw */ 172 #define PCI_CFG_CMD_ENB __BIT(31) /* Enable */ 173 #define PCI_CFG_CMD_RESa __BITS(30,24) 174 #define PCI_CFG_CMD_BUSNO __BITS(23,16) /* Bus Number */ 175 #define PCI_CFG_CMD_BUSn(n) (((n) << 16) & PCI_CFG_CMD_BUSNO) 176 #define PCI_CFG_CMD_DEVNO __BITS(15,11) /* Device Number */ 177 #define PCI_CFG_CMD_DEVn(n) (((n) << 11) & PCI_CFG_CMD_DEVNO) 178 #define PCI_CFG_CMD_FUNCNO __BITS(10,8) /* Function Number */ 179 #define PCI_CFG_CMD_FUNCn(n) (((n) << 8) & PCI_CFG_CMD_FUNCNO) 180 #define PCI_CFG_CMD_REGNO __BITS(7,2) /* Register Number */ 181 #define PCI_CFG_CMD_REGn(n) (((n) << 0) & PCI_CFG_CMD_REGNO) 182 #define PCI_CFG_CMD_RESb __BITS(1,0) 183 #define PCI_CFG_CMD_RESV \ 184 (PCI_CFG_CMD_RESa | PCI_CFG_CMD_RESb) 185 #define GEMINI_PCI_CFG_DATA 0x2c /* PCI Configuration Data */ /* rw */ 186 187 /* 188 * Gemini machine dependent PCI config registers 189 */ 190 #define GEMINI_PCI_CFG_REG_PMR1 0x40 /* Power Management 1 */ /* rw */ 191 #define GEMINI_PCI_CFG_REG_PMR2 0x44 /* Power Management 2 */ /* rw */ 192 #define GEMINI_PCI_CFG_REG_CTL1 0x48 /* Control 1 */ /* rw */ 193 #define GEMINI_PCI_CFG_REG_CTL2 0x4c /* Control 2 */ /* rw */ 194 #define PCI_CFG_REG_CTL2_INTSTS __BITS(31,28) 195 #define CFG_REG_CTL2_INTSTS_INTD __BIT(28 + 3) 196 #define CFG_REG_CTL2_INTSTS_INTC __BIT(28 + 2) 197 #define CFG_REG_CTL2_INTSTS_INTB __BIT(28 + 1) 198 #define CFG_REG_CTL2_INTSTS_INTA __BIT(28 + 0) 199 #define PCI_CFG_REG_CTL2_INTMASK __BITS(27,16) 200 #define CFG_REG_CTL2_INTMASK_CMDERR __BIT(16 + 11) 201 #define CFG_REG_CTL2_INTMASK_PARERR __BIT(16 + 10) 202 #define CFG_REG_CTL2_INTMASK_INTD __BIT(16 + 9) 203 #define CFG_REG_CTL2_INTMASK_INTC __BIT(16 + 8) 204 #define CFG_REG_CTL2_INTMASK_INTB __BIT(16 + 7) 205 #define CFG_REG_CTL2_INTMASK_INTA __BIT(16 + 6) 206 #define CFG_REG_CTL2_INTMASK_INT_ABCD __BITS(16+9,16+6) 207 #define CFG_REG_CTL2_INTMASK_MABRT_RX __BIT(16 + 5) 208 #define CFG_REG_CTL2_INTMASK_TABRT_RX __BIT(16 + 4) 209 #define CFG_REG_CTL2_INTMASK_TABRT_TX __BIT(16 + 3) 210 #define CFG_REG_CTL2_INTMASK_RETRY4 __BIT(16 + 2) 211 #define CFG_REG_CTL2_INTMASK_SERR_RX __BIT(16 + 1) 212 #define CFG_REG_CTL2_INTMASK_PERR_RX __BIT(16 + 0) 213 #define PCI_CFG_REG_CTL2_RESa __BIT(15) 214 #define PCI_CFG_REG_CTL2_MSTPRI __BITS(14,8) 215 #define CFG_REG_CTL2_MSTPRI_REQn(n) __BIT(8 + (n)) 216 #define PCI_CFG_REG_CTL2_RESb __BITS(7,4) 217 #define PCI_CFG_REG_CTL2_TRDYW __BITS(3,0) 218 #define PCI_CFG_REG_CTL2_RESV \ 219 (PCI_CFG_REG_CTL2_RESa | PCI_CFG_REG_CTL2_RESb) 220 #define GEMINI_PCI_CFG_REG_MEM1 0x50 /* Memory 1 Base */ /* rw */ 221 #define GEMINI_PCI_CFG_REG_MEM2 0x54 /* Memory 2 Base */ /* rw */ 222 #define GEMINI_PCI_CFG_REG_MEM3 0x58 /* Memory 3 Base */ /* rw */ 223 #define PCI_CFG_REG_MEM_BASE_MASK __BITS(31,20) 224 #define PCI_CFG_REG_MEM_BASE(base) ((base) & PCI_CFG_REG_MEM_BASE_MASK) 225 #define PCI_CFG_REG_MEM_SIZE_MASK __BITS(19,16) 226 #define PCI_CFG_REG_MEM_SIZE_1MB (0x0 << 16) 227 #define PCI_CFG_REG_MEM_SIZE_2MB (0x1 << 16) 228 #define PCI_CFG_REG_MEM_SIZE_4MB (0x2 << 16) 229 #define PCI_CFG_REG_MEM_SIZE_8MB (0x3 << 16) 230 #define PCI_CFG_REG_MEM_SIZE_16MB (0x4 << 16) 231 #define PCI_CFG_REG_MEM_SIZE_32MB (0x5 << 16) 232 #define PCI_CFG_REG_MEM_SIZE_64MB (0x6 << 16) 233 #define PCI_CFG_REG_MEM_SIZE_128MB (0x7 << 16) 234 #define PCI_CFG_REG_MEM_SIZE_256MB (0x8 << 16) 235 #define PCI_CFG_REG_MEM_SIZE_512MB (0x9 << 16) 236 #define PCI_CFG_REG_MEM_SIZE_1GB (0xa << 16) 237 #define PCI_CFG_REG_MEM_SIZE_2GB (0xb << 16) 238 #define PCI_CFG_REG_MEM_RESV __BITS(19,16) 239 240 #ifndef _LOCORE 241 static inline unsigned int 242 gemini_pci_cfg_reg_mem_size(size_t sz) 243 { 244 switch (sz) { 245 case (1 << 20): 246 return PCI_CFG_REG_MEM_SIZE_1MB; 247 case (2 << 20): 248 return PCI_CFG_REG_MEM_SIZE_2MB; 249 case (4 << 20): 250 return PCI_CFG_REG_MEM_SIZE_4MB; 251 case (8 << 20): 252 return PCI_CFG_REG_MEM_SIZE_8MB; 253 case (16 << 20): 254 return PCI_CFG_REG_MEM_SIZE_16MB; 255 case (32 << 20): 256 return PCI_CFG_REG_MEM_SIZE_32MB; 257 case (64 << 20): 258 return PCI_CFG_REG_MEM_SIZE_64MB; 259 case (128 << 20): 260 return PCI_CFG_REG_MEM_SIZE_128MB; 261 case (256 << 20): 262 return PCI_CFG_REG_MEM_SIZE_256MB; 263 case (512 << 20): 264 return PCI_CFG_REG_MEM_SIZE_512MB; 265 case (1024 << 20): 266 return PCI_CFG_REG_MEM_SIZE_1GB; 267 case (2048 << 20): 268 return PCI_CFG_REG_MEM_SIZE_2GB; 269 default: 270 panic("gemini_pci_cfg_reg_mem_size: bad size %#lx\n", sz); 271 } 272 /* NOTREACHED */ 273 } 274 #endif /* _LOCORE */ 275 276 #else 277 # error unknown gemini cpu type 278 #endif 279 280 #endif /* _ARM_GEMINI_REG_H_ */ 281
Indexes created Sun Oct 19 16:10:00 GMT 2025