gemini_reg.h revision 1.6
1 /* $NetBSD: gemini_reg.h,v 1.6 2008/11/20 22:36:36 cliff Exp $ */ 2 3 #ifndef _ARM_GEMINI_REG_H_ 4 #define _ARM_GEMINI_REG_H_ 5 6 /* 7 * Register definitions for Gemini SOC 8 */ 9 10 #include "opt_gemini.h" 11 #include <machine/endian.h> 12 #include <sys/cdefs.h> 13 14 #if defined(SL3516) 15 /* 16 * Gemini SL3516 memory map 17 */ 18 #define GEMINI_SRAM_BASE 0x00000000 /* Internal SRAM */ 19 /* NOTE: use the SHADOW to avoid conflict w/ DRAM */ 20 #define GEMINI_SRAM_SIZE 0x10000000 /* 128 MB */ 21 #define GEMINI_DRAM_BASE 0x00000000 /* DRAM (via DDR Control Module) */ 22 /* NOTE: this is a shadow of 0x10000000 */ 23 #define GEMINI_DRAM_SIZE 0x20000000 /* 512 MB */ 24 /* NOTE: size of addr space, not necessarily populated */ 25 #define GEMINI_FLASH_BASE 0x30000000 /* DRAM (via DDR Control Module) */ 26 #define GEMINI_FLASH_SIZE 0x10000000 /* 128 MB */ 27 28 /* 29 * Gemini SL3516 device map 30 */ 31 #define GEMINI_GLOBAL_BASE 0x40000000 /* Global registers */ 32 #define GEMINI_WATCHDOG_BASE 0x41000000 /* Watch dog timer module */ 33 #define GEMINI_UART_BASE 0x42000000 /* UART control module */ 34 #define GEMINI_UART_SIZE 0x20 35 #define GEMINI_TIMER_BASE 0x43000000 /* Timer module */ 36 #define GEMINI_LCD_BASE 0x44000000 /* LCD Interface module */ 37 #define GEMINI_RTC_BASE 0x45000000 /* Real Time Clock module */ 38 #define GEMINI_SATA_BASE 0x46000000 /* Serial ATA module */ 39 #define GEMINI_LPCHC_BASE 0x47000000 /* LPC Hosr Controller module */ 40 #define GEMINI_LPCIO_BASE 0x47800000 /* LPC Peripherals IO space */ 41 #define GEMINI_IC0_BASE 0x48000000 /* Interrupt Control module #0 */ 42 #define GEMINI_IC1_BASE 0x49000000 /* Interrupt Control module #1 */ 43 #define GEMINI_SSPC_BASE 0x4a000000 /* Synchronous Serial Port Control module */ 44 #define GEMINI_PWRC_BASE 0x4b000000 /* Power Control module */ 45 #define GEMINI_CIR_BASE 0x4c000000 /* CIR Control module */ 46 #define GEMINI_GPIO0_BASE 0x4d000000 /* GPIO module #0 */ 47 #define GEMINI_GPIO1_BASE 0x4e000000 /* GPIO module #1 */ 48 #define GEMINI_GPIO2_BASE 0x4f000000 /* GPIO module #2 */ 49 #define GEMINI_PCICFG_BASE 0x50000000 /* PCI IO, configuration and control space */ 50 #define GEMINI_PCIIO_BASE 0x50001000 /* PCI IO space */ 51 #define GEMINI_PCIIO_SIZE 0x0007f000 /* PCI IO space size */ 52 #define GEMINI_PCIMEM_BASE 0x58000000 /* PCI Memory space */ 53 #define GEMINI_PCIMEM_SIZE 0x08000000 /* PCI Memory space size */ 54 #define GEMINI_NGC_BASE 0x60000000 /* NetEngine & GMAC Configuration registers */ 55 #define GEMINI_SDC_BASE 0x62000000 /* Security DMA and Configure registers */ 56 #define GEMINI_MIDE_BASE 0x63000000 /* Multi IDE registers */ 57 #define GEMINI_RXDC_BASE 0x64000000 /* RAID XOR DMA Configuration registers */ 58 #define GEMINI_FLASHC_BASE 0x65000000 /* Flash Controller registers */ 59 #define GEMINI_DRAMC_BASE 0x66000000 /* DRAM (DDR/SDR) Controller registers */ 60 #define GEMINI_GDMA_BASE 0x67000000 /* General DMA registers */ 61 #define GEMINI_USB0_BASE 0x68000000 /* USB #0 registers */ 62 #define GEMINI_USB1_BASE 0x69000000 /* USB #1 registers */ 63 #define GEMINI_TVE_BASE 0x6a000000 /* TVE registers */ 64 #define GEMINI_SRAM_SHADOW_BASE 0x70000000 /* Shadow of internal SRAM */ 65 66 /* 67 * Gemini SL3516 Global register offsets and bits 68 */ 69 #define GEMINI_GLOBAL_WORD_ID 0x0 /* Global Word ID */ /* ro */ 70 #define GLOBAL_ID_CHIP_ID __BITS(31,8) 71 #define GLOBAL_ID_CHIP_REV __BITS(7,0) 72 #define GEMINI_GLOBAL_RESET_CTL 0xc /* Global Soft Reset Control */ /* rw */ 73 #define GLOBAL_RESET_GLOBAL __BIT(31) /* Global Soft Reset */ 74 #define GLOBAL_RESET_CPU1 __BIT(30) /* CPU#1 reset hold */ 75 #define GEMINI_GLOBAL_MISC_CTL 0x30 /* Miscellaneous Control */ /* rw */ 76 #define GEMINI_GLOBAL_CPU0 0x38 /* CPU #0 Status and Control */ /* rw */ 77 #define GLOBAL_CPU0_IPICPU1 __BIT(31) /* IPI to CPU#1 */ 78 #define GEMINI_GLOBAL_CPU1 0x3c /* CPU #1 Status and Control */ /* rw */ 79 #define GLOBAL_CPU1_IPICPU0 __BIT(31) /* IPI to CPU#0 */ 80 81 /* 82 * Gemini SL3516 Watchdog device register offsets and bits 83 */ 84 #define GEMINI_WDT_WDCOUNTER 0x0 /* Watchdog Timer Counter */ /* ro */ 85 #define GEMINI_WDT_WDLOAD 0x4 /* Watchdog Timer Load */ /* rw */ 86 #define WDT_WDLOAD_DFLT 0x3EF1480 /* default Load reg val */ 87 #define GEMINI_WDT_WDRESTART 0x8 /* Watchdog Timer Restart */ /* wo */ 88 #define WDT_WDRESTART_Resv __BITS(31,16) 89 #define WDT_WDRESTART_RST __BITS(15,0) 90 #define WDT_WDRESTART_MAGIC 0x5ab9 91 #define GEMINI_WDT_WDCR 0xc /* Watchdog Timer Control */ /* rw */ 92 #define WDT_WDCR_Resv __BITS(31,5) 93 #define WDT_WDCR_CLKSRC __BIT(4) /* Timer Clock Source: 5 MHz clock */ 94 #define WDCR_CLKSRC_PCLK (0 << 4) /* Timer Clock Source: PCLK (APB CLK) */ 95 #define WDCR_CLKSRC_5MHZ (1 << 4) /* Timer Clock Source: 5 MHz clock */ 96 #define WDT_WDCR_EXTSIG_ENB __BIT(3) /* Timer External Signal Enable */ 97 #define WDT_WDCR_INTR_ENB __BIT(2) /* Timer System Interrupt Enable */ 98 #define WDT_WDCR_RESET_ENB __BIT(1) /* Timer System Reset Enable */ 99 #define WDT_WDCR_ENB __BIT(0) /* Timer Enable */ 100 #define GEMINI_WDT_WDSTATUS 0x10 /* Watchdog Timer Status */ /* ro */ 101 #define WDT_WDSTATUS_Resv __BITS(31,1) 102 #define WDT_WDSTATUS_ZERO __BIT(0) /* non-zero if timer counted down to zero! */ 103 #define GEMINI_WDT_WDCLEAR 0x14 /* Watchdog Timer Clear */ /* wo */ 104 #define WDT_WDCLEAR_Resv __BITS(31,1) 105 #define WDT_WDCLEAR_CLEAR __BIT(0) /* write this bit to clear Status */ 106 #define GEMINI_WDT_WDINTERLEN 0x18 /* Watchdog Timer Interrupt Length */ /* rw */ 107 /* duration of signal assertion, */ 108 /* in units of clock cycles */ 109 #define WDT_WDINTERLEN_DFLT 0xff /* default is 256 cycles */ 110 111 112 /* 113 * Gemini SL3516 Timer device register offsets and bits 114 * 115 * have 3 timers, here indexed 1<=(n)<=3 as in the doc 116 * each has 4 sequential 32bit rw regs 117 */ 118 #define GEMINI_NTIMERS 3 119 #define GEMINI_TIMERn_REG(n, o) ((((n) - 1) * 0x10) + (o)) 120 #define GEMINI_TIMERn_COUNTER(n) GEMINI_TIMERn_REG((n), 0x0) /* rw */ 121 #define GEMINI_TIMERn_LOAD(n) GEMINI_TIMERn_REG((n), 0x4) /* rw */ 122 #define GEMINI_TIMERn_MATCH1(n) GEMINI_TIMERn_REG((n), 0x08) /* rw */ 123 #define GEMINI_TIMERn_MATCH2(n) GEMINI_TIMERn_REG((n), 0x0C) /* rw */ 124 #define GEMINI_TIMER_TMCR 0x30 /* rw */ 125 #define TIMER_TMCR_Resv __BITS(31,12) 126 #define TIMER_TMCR_TMnUPDOWN(n) __BIT(9 + (n) - 1) 127 #define TIMER_TMCR_TMnOFENABLE(n) __BIT((((n) - 1) * 3) + 2) 128 #define TIMER_TMCR_TMnCLOCK(n) __BIT((((n) - 1) * 3) + 1) 129 #define TIMER_TMCR_TMnENABLE(n) __BIT((((n) - 1) * 3) + 0) 130 #define GEMINI_TIMER_TMnCR_MASK(n) \ 131 ( TIMER_TMCR_TMnUPDOWN(n) \ 132 | TIMER_TMCR_TMnOFENABLE(n) \ 133 | TIMER_TMCR_TMnCLOCK(n) \ 134 | TIMER_TMCR_TMnENABLE(n) ) 135 #define GEMINI_TIMER_INTRSTATE 0x34 /* rw */ 136 #define TIMER_INTRSTATE_Resv __BITS(31,9) 137 #define TIMER_INTRSTATE_TMnOVFLOW(n) __BIT((((n) -1) * 3) + 2) 138 #define TIMER_INTRSTATE_TMnMATCH2(n) __BIT((((n) -1) * 3) + 1) 139 #define TIMER_INTRSTATE_TMnMATCH1(n) __BIT((((n) -1) * 3) + 0) 140 #define GEMINI_TIMER_INTRMASK 0x38 /* rw */ 141 #define TIMER_INTRMASK_Resv __BITS(31,9) 142 #define TIMER_INTRMASK_TMnOVFLOW(n) __BIT((((n) -1) * 3) + 2) 143 #define TIMER_INTRMASK_TMnMATCH2(n) __BIT((((n) -1) * 3) + 1) 144 #define TIMER_INTRMASK_TMnMATCH1(n) __BIT((((n) -1) * 3) + 0) 145 #define GEMINI_TIMERn_INTRMASK(n) \ 146 ( TIMER_INTRMASK_TMnOVFLOW(n) \ 147 | TIMER_INTRMASK_TMnMATCH2(n) \ 148 | TIMER_INTRMASK_TMnMATCH1(n) ) 149 150 /* 151 * Gemini SL3516 Interrupt Controller device register offsets and bits 152 */ 153 #define GEMINI_ICU_IRQ_SOURCE 0x0 /* ro */ 154 #define GEMINI_ICU_IRQ_ENABLE 0x4 /* rw */ 155 #define GEMINI_ICU_IRQ_CLEAR 0x8 /* wo */ 156 #define GEMINI_ICU_IRQ_TRIGMODE 0xc /* rw */ 157 #define ICU_IRQ_TRIGMODE_EDGE 1 /* edge triggered */ 158 #define ICU_IRQ_TRIGMODE_LEVEL 0 /* level triggered */ 159 #define GEMINI_ICU_IRQ_TRIGLEVEL 0x10 /* rw */ 160 #define ICU_IRQ_TRIGLEVEL_LO 1 /* active low or falling edge */ 161 #define ICU_IRQ_TRIGLEVEL_HI 0 /* active high or rising edge */ 162 #define GEMINI_ICU_IRQ_STATUS 0x14 /* ro */ 163 164 #define GEMINI_ICU_FIQ_SOURCE 0x20 /* ro */ 165 #define GEMINI_ICU_FIQ_ENABLE 0x24 /* rw */ 166 #define GEMINI_ICU_FIQ_CLEAR 0x28 /* wo */ 167 #define GEMINI_ICU_FIQ_TRIGMODE 0x2c /* rw */ 168 #define GEMINI_ICU_FIQ_TRIGLEVEL 0x30 /* rw */ 169 #define GEMINI_ICU_FIQ_STATUS 0x34 /* ro */ 170 171 #define GEMINI_ICU_REVISION 0x50 /* ro */ 172 #define GEMINI_ICU_INPUT_NUM 0x54 /* ro */ 173 #define ICU_INPUT_NUM_RESV __BITS(31,16) 174 #define ICU_INPUT_NUM_IRQ __BITS(15,8) 175 #define ICU_INPUT_NUM_FIQ __BITS(7,0) 176 #define GEMINI_ICU_IRQ_DEBOUNCE 0x58 /* ro */ 177 #define GEMINI_ICU_FIQ_DEBOUNCE 0x5c /* ro */ 178 179 180 /* 181 * Gemini LPC controller register offsets and bits 182 */ 183 #define GEMINI_LPCHC_ID 0x00 /* ro */ 184 # define LPCHC_ID_DEVICE __BITS(31,8) /* Device ID */ 185 # define LPCHC_ID_REV __BITS(7,0) /* Revision */ 186 # define _LPCHC_ID_DEVICE(r) ((typeof(r))(((r) & LPCHC_ID_DEVICE) >> 8)) 187 # define _LPCHC_ID_REV(r) ((typeof(r))(((r) & LPCHC_ID_REV) >> 0)) 188 #define GEMINI_LPCHC_CSR 0x04 /* rw */ 189 # define LPCHC_CSR_RESa __BITS(31,24) 190 # define LPCHC_CSR_STO __BIT(23) /* Sync Time Out */ 191 # define LPCHC_CSR_SERR __BIT(22) /* Sync Error */ 192 # define LPCHC_CSR_RESb __BITS(21,8) 193 # define LPCHC_CSR_STOE __BIT(7) /* Sync Time Out Enable */ 194 # define LPCHC_CSR_SERRE __BIT(6) /* Sync Error Enable */ 195 # define LPCHC_CSR_RESc __BITS(5,1) 196 # define LPCHC_CSR_BEN __BIT(0) /* Bridge Enable */ 197 #define GEMINI_LPCHC_IRQCTL 0x08 /* rw */ 198 # define LPCHC_IRQCTL_RESV __BITS(31,8) 199 # define LPCHC_IRQCTL_SIRQEN __BIT(7) /* Serial IRQ Enable */ 200 # define LPCHC_IRQCTL_SIRQMS __BIT(6) /* Serial IRQ Mode Select */ 201 # define LPCHC_IRQCTL_SIRQFN __BITS(5,2) /* Serial IRQ Frame Number */ 202 # define LPCHC_IRQCTL_SIRQFW __BITS(1,0) /* Serial IRQ Frame Width */ 203 # define IRQCTL_SIRQFW_4 0 204 # define IRQCTL_SIRQFW_6 1 205 # define IRQCTL_SIRQFW_8 2 206 # define IRQCTL_SIRQFW_RESV 3 207 #define GEMINI_LPCHC_SERIRQSTS 0x0c /* rwc */ 208 # define LPCHC_SERIRQSTS_RESV __BITS(31,17) 209 #define GEMINI_LPCHC_SERIRQTYP 0x10 /* rw */ 210 # define LPCHC_SERIRQTYP_RESV __BITS(31,17) 211 # define SERIRQTYP_EDGE 1 212 # define SERIRQTYP_LEVEL 0 213 #define GEMINI_LPCHC_SERIRQPOLARITY 0x14 /* rw */ 214 # define LPCHC_SERIRQPOLARITY_RESV __BITS(31,17) 215 # define SERIRQPOLARITY_HI 1 216 # define SERIRQPOLARITY_LO 0 217 #define GEMINI_LPCHC_SIZE (GEMINI_LPCHC_SERIRQPOLARITY + 4) 218 #define GEMINI_LPCHC_NSERIRQ 17 219 220 /* 221 * Gemini GPIO controller register offsets and bits 222 */ 223 #define GEMINI_GPIO_DATAOUT 0x00 /* Data Out */ /* rw */ 224 #define GEMINI_GPIO_DATAIN 0x04 /* Data Out */ /* ro */ 225 #define GEMINI_GPIO_PINDIR 0x08 /* Pin Direction */ /* rw */ 226 #define GPIO_PINDIR_INPUT 0 227 #define GPIO_PINDIR_OUTPUT 1 228 #define GEMINI_GPIO_PINBYPASS 0x0c /* Pin Bypass */ /* rw */ 229 #define GEMINI_GPIO_DATASET 0x10 /* Data Set */ /* wo */ 230 #define GEMINI_GPIO_DATACLR 0x14 /* Data Clear */ /* wo */ 231 #define GEMINI_GPIO_PULLENB 0x18 /* Pullup Enable */ /* rw */ 232 #define GEMINI_GPIO_PULLTYPE 0x1c /* Pullup Type */ /* rw */ 233 #define GPIO_PULLTYPE_LOW 0 234 #define GPIO_PULLTYPE_HIGH 1 235 #define GEMINI_GPIO_INTRENB 0x20 /* Interrupt Enable */ /* rw */ 236 #define GEMINI_GPIO_INTRRAWSTATE 0x24 /* Interrupt Raw State */ /* ro */ 237 #define GEMINI_GPIO_INTRMSKSTATE 0x28 /* Interrupt Masked State */ /* ro */ 238 #define GEMINI_GPIO_INTRMASK 0x2c /* Interrupt Mask */ /* rw */ 239 #define GEMINI_GPIO_INTRCLR 0x30 /* Interrupt Clear */ /* wo */ 240 #define GEMINI_GPIO_INTRTRIG 0x34 /* Interrupt Trigger Method */ /* rw */ 241 #define GPIO_INTRTRIG_EDGE 0 242 #define GPIO_INTRTRIG_LEVEL 1 243 #define GEMINI_GPIO_INTREDGEBOTH 0x38 /* Both edges trigger Intr. */ /* rw */ 244 #define GEMINI_GPIO_INTRDIR 0x3c /* edge/level direction */ /* rw */ 245 #define GPIO_INTRDIR_EDGE_RISING 0 246 #define GPIO_INTRDIR_EDGE_FALLING 1 247 #define GPIO_INTRDIR_LEVEL_HIGH 0 248 #define GPIO_INTRDIR_LEVEL_LOW 1 249 #define GEMINI_GPIO_BOUNCEENB 0x40 /* Bounce Enable */ /* rw */ 250 #define GEMINI_GPIO_BOUNCESCALE 0x44 /* Bounce Pre-Scale */ /* rw */ 251 #define GPIO_BOUNCESCALE_RESV __BITS(31,16) 252 #define GPIO_BOUNCESCALE_VAL __BITS(15,0) /* NOTE: 253 * if bounce is enabled, and bounce pre-scale == 0 254 * then the the pin will not detect any interrupt 255 */ 256 #define GEMINI_GPIO_SIZE (GEMINI_GPIO_BOUNCESCALE + 4) 257 258 /* 259 * Gemini PCI controller register offsets and bits 260 */ 261 #define GEMINI_PCI_IOSIZE 0x00 /* I/O Space Size */ /* rw */ 262 #define GEMINI_PCI_PROT 0x04 /* AHB Protection */ /* rw */ 263 #define GEMINI_PCI_PCICTRL 0x08 /* PCI Control Signal */ /* rw */ 264 #define GEMINI_PCI_ERREN 0x0c /* Soft Reset Counter and 265 * Response Error Enable */ /* rw */ 266 #define GEMINI_PCI_SOFTRST 0x10 /* Soft Reset */ 267 #define GEMINI_PCI_CFG_CMD 0x28 /* PCI Configuration Command */ /* rw */ 268 #define PCI_CFG_CMD_ENB __BIT(31) /* Enable */ 269 #define PCI_CFG_CMD_RESa __BITS(30,24) 270 #define PCI_CFG_CMD_BUSNO __BITS(23,16) /* Bus Number */ 271 #define PCI_CFG_CMD_BUSn(n) (((n) << 16) & PCI_CFG_CMD_BUSNO) 272 #define PCI_CFG_CMD_DEVNO __BITS(15,11) /* Device Number */ 273 #define PCI_CFG_CMD_DEVn(n) (((n) << 11) & PCI_CFG_CMD_DEVNO) 274 #define PCI_CFG_CMD_FUNCNO __BITS(10,8) /* Function Number */ 275 #define PCI_CFG_CMD_FUNCn(n) (((n) << 8) & PCI_CFG_CMD_FUNCNO) 276 #define PCI_CFG_CMD_REGNO __BITS(7,2) /* Register Number */ 277 #define PCI_CFG_CMD_REGn(n) (((n) << 0) & PCI_CFG_CMD_REGNO) 278 #define PCI_CFG_CMD_RESb __BITS(1,0) 279 #define PCI_CFG_CMD_RESV \ 280 (PCI_CFG_CMD_RESa | PCI_CFG_CMD_RESb) 281 #define GEMINI_PCI_CFG_DATA 0x2c /* PCI Configuration Data */ /* rw */ 282 283 /* 284 * Gemini machine dependent PCI config registers 285 */ 286 #define GEMINI_PCI_CFG_REG_PMR1 0x40 /* Power Management 1 */ /* rw */ 287 #define GEMINI_PCI_CFG_REG_PMR2 0x44 /* Power Management 2 */ /* rw */ 288 #define GEMINI_PCI_CFG_REG_CTL1 0x48 /* Control 1 */ /* rw */ 289 #define GEMINI_PCI_CFG_REG_CTL2 0x4c /* Control 2 */ /* rw */ 290 #define PCI_CFG_REG_CTL2_INTSTS __BITS(31,28) 291 #define CFG_REG_CTL2_INTSTS_INTD __BIT(28 + 3) 292 #define CFG_REG_CTL2_INTSTS_INTC __BIT(28 + 2) 293 #define CFG_REG_CTL2_INTSTS_INTB __BIT(28 + 1) 294 #define CFG_REG_CTL2_INTSTS_INTA __BIT(28 + 0) 295 #define PCI_CFG_REG_CTL2_INTMASK __BITS(27,16) 296 #define CFG_REG_CTL2_INTMASK_CMDERR __BIT(16 + 11) 297 #define CFG_REG_CTL2_INTMASK_PARERR __BIT(16 + 10) 298 #define CFG_REG_CTL2_INTMASK_INTD __BIT(16 + 9) 299 #define CFG_REG_CTL2_INTMASK_INTC __BIT(16 + 8) 300 #define CFG_REG_CTL2_INTMASK_INTB __BIT(16 + 7) 301 #define CFG_REG_CTL2_INTMASK_INTA __BIT(16 + 6) 302 #define CFG_REG_CTL2_INTMASK_INT_ABCD __BITS(16+9,16+6) 303 #define CFG_REG_CTL2_INTMASK_MABRT_RX __BIT(16 + 5) 304 #define CFG_REG_CTL2_INTMASK_TABRT_RX __BIT(16 + 4) 305 #define CFG_REG_CTL2_INTMASK_TABRT_TX __BIT(16 + 3) 306 #define CFG_REG_CTL2_INTMASK_RETRY4 __BIT(16 + 2) 307 #define CFG_REG_CTL2_INTMASK_SERR_RX __BIT(16 + 1) 308 #define CFG_REG_CTL2_INTMASK_PERR_RX __BIT(16 + 0) 309 #define PCI_CFG_REG_CTL2_RESa __BIT(15) 310 #define PCI_CFG_REG_CTL2_MSTPRI __BITS(14,8) 311 #define CFG_REG_CTL2_MSTPRI_REQn(n) __BIT(8 + (n)) 312 #define PCI_CFG_REG_CTL2_RESb __BITS(7,4) 313 #define PCI_CFG_REG_CTL2_TRDYW __BITS(3,0) 314 #define PCI_CFG_REG_CTL2_RESV \ 315 (PCI_CFG_REG_CTL2_RESa | PCI_CFG_REG_CTL2_RESb) 316 #define GEMINI_PCI_CFG_REG_MEM1 0x50 /* Memory 1 Base */ /* rw */ 317 #define GEMINI_PCI_CFG_REG_MEM2 0x54 /* Memory 2 Base */ /* rw */ 318 #define GEMINI_PCI_CFG_REG_MEM3 0x58 /* Memory 3 Base */ /* rw */ 319 #define PCI_CFG_REG_MEM_BASE_MASK __BITS(31,20) 320 #define PCI_CFG_REG_MEM_BASE(base) ((base) & PCI_CFG_REG_MEM_BASE_MASK) 321 #define PCI_CFG_REG_MEM_SIZE_MASK __BITS(19,16) 322 #define PCI_CFG_REG_MEM_SIZE_1MB (0x0 << 16) 323 #define PCI_CFG_REG_MEM_SIZE_2MB (0x1 << 16) 324 #define PCI_CFG_REG_MEM_SIZE_4MB (0x2 << 16) 325 #define PCI_CFG_REG_MEM_SIZE_8MB (0x3 << 16) 326 #define PCI_CFG_REG_MEM_SIZE_16MB (0x4 << 16) 327 #define PCI_CFG_REG_MEM_SIZE_32MB (0x5 << 16) 328 #define PCI_CFG_REG_MEM_SIZE_64MB (0x6 << 16) 329 #define PCI_CFG_REG_MEM_SIZE_128MB (0x7 << 16) 330 #define PCI_CFG_REG_MEM_SIZE_256MB (0x8 << 16) 331 #define PCI_CFG_REG_MEM_SIZE_512MB (0x9 << 16) 332 #define PCI_CFG_REG_MEM_SIZE_1GB (0xa << 16) 333 #define PCI_CFG_REG_MEM_SIZE_2GB (0xb << 16) 334 #define PCI_CFG_REG_MEM_RESV __BITS(19,16) 335 336 #ifndef _LOCORE 337 static inline unsigned int 338 gemini_pci_cfg_reg_mem_size(size_t sz) 339 { 340 switch (sz) { 341 case (1 << 20): 342 return PCI_CFG_REG_MEM_SIZE_1MB; 343 case (2 << 20): 344 return PCI_CFG_REG_MEM_SIZE_2MB; 345 case (4 << 20): 346 return PCI_CFG_REG_MEM_SIZE_4MB; 347 case (8 << 20): 348 return PCI_CFG_REG_MEM_SIZE_8MB; 349 case (16 << 20): 350 return PCI_CFG_REG_MEM_SIZE_16MB; 351 case (32 << 20): 352 return PCI_CFG_REG_MEM_SIZE_32MB; 353 case (64 << 20): 354 return PCI_CFG_REG_MEM_SIZE_64MB; 355 case (128 << 20): 356 return PCI_CFG_REG_MEM_SIZE_128MB; 357 case (256 << 20): 358 return PCI_CFG_REG_MEM_SIZE_256MB; 359 case (512 << 20): 360 return PCI_CFG_REG_MEM_SIZE_512MB; 361 case (1024 << 20): 362 return PCI_CFG_REG_MEM_SIZE_1GB; 363 case (2048 << 20): 364 return PCI_CFG_REG_MEM_SIZE_2GB; 365 default: 366 panic("gemini_pci_cfg_reg_mem_size: bad size %#lx\n", sz); 367 } 368 /* NOTREACHED */ 369 } 370 #endif /* _LOCORE */ 371 372 /* 373 * Gemini SL3516 IDE device register offsets, &etc. 374 */ 375 #define GEMINI_MIDE_NCHAN 2 376 #define GEMINI_MIDE_OFFSET(chan) ((chan == 0) ? 0x0 : 0x400000) 377 #define GEMINI_MIDE_BASEn(chan) (GEMINI_MIDE_BASE + GEMINI_MIDE_OFFSET(chan)) 378 #define GEMINI_MIDE_CMDBLK 0x20 379 #define GEMINI_MIDE_CTLBLK 0x36 380 #define GEMINI_MIDE_SIZE 0x40 381 382 383 /* 384 * Gemini DRAM Controller register offsets, &etc. 385 */ 386 #define GEMINI_DRAMC_RMCR 0x40 /* CPU Remap Control */ /* rw */ 387 #define DRAMC_RMCR_RESa __BITS(31,29) 388 #define DRAMC_RMCR_RMBAR __BITS(28,20) /* Remap Base Address */ 389 #define DRAMC_RMCR_RMBAR_SHFT 20 390 #define DRAMC_RMCR_RESb __BITS(19,9) 391 #define DRAMC_RMCR_RMSZR __BITS(8,0) /* Remap Size Address */ 392 #define DRAMC_RMCR_RMSZR_SHFT 0 393 394 #else 395 # error unknown gemini cpu type 396 #endif 397 398 #endif /* _ARM_GEMINI_REG_H_ */ 399
Indexes created Sun Sep 28 07:09:56 GMT 2025