if_gmc.c revision 1.3.2.2
1 1.3.2.2 mjf /* $NetBSD: if_gmc.c,v 1.3.2.2 2009/01/17 13:27:53 mjf Exp $ */ 2 1.3.2.2 mjf /*- 3 1.3.2.2 mjf * Copyright (c) 2008 The NetBSD Foundation, Inc. 4 1.3.2.2 mjf * All rights reserved. 5 1.3.2.2 mjf * 6 1.3.2.2 mjf * This code is derived from software contributed to The NetBSD Foundation 7 1.3.2.2 mjf * by Matt Thomas <matt (at) 3am-software.com> 8 1.3.2.2 mjf * 9 1.3.2.2 mjf * Redistribution and use in source and binary forms, with or without 10 1.3.2.2 mjf * modification, are permitted provided that the following conditions 11 1.3.2.2 mjf * are met: 12 1.3.2.2 mjf * 1. Redistributions of source code must retain the above copyright 13 1.3.2.2 mjf * notice, this list of conditions and the following disclaimer. 14 1.3.2.2 mjf * 2. Redistributions in binary form must reproduce the above copyright 15 1.3.2.2 mjf * notice, this list of conditions and the following disclaimer in the 16 1.3.2.2 mjf * documentation and/or other materials provided with the distribution. 17 1.3.2.2 mjf * 18 1.3.2.2 mjf * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 1.3.2.2 mjf * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 1.3.2.2 mjf * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 1.3.2.2 mjf * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 1.3.2.2 mjf * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 1.3.2.2 mjf * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 1.3.2.2 mjf * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 1.3.2.2 mjf * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 1.3.2.2 mjf * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 1.3.2.2 mjf * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 1.3.2.2 mjf * POSSIBILITY OF SUCH DAMAGE. 29 1.3.2.2 mjf */ 30 1.3.2.2 mjf 31 1.3.2.2 mjf #include <sys/param.h> 32 1.3.2.2 mjf #include <sys/callout.h> 33 1.3.2.2 mjf #include <sys/device.h> 34 1.3.2.2 mjf #include <sys/ioctl.h> 35 1.3.2.2 mjf #include <sys/kernel.h> 36 1.3.2.2 mjf #include <sys/kmem.h> 37 1.3.2.2 mjf #include <sys/mbuf.h> 38 1.3.2.2 mjf 39 1.3.2.2 mjf #include <machine/bus.h> 40 1.3.2.2 mjf #include <machine/intr.h> 41 1.3.2.2 mjf 42 1.3.2.2 mjf #include <arm/gemini/gemini_reg.h> 43 1.3.2.2 mjf #include <arm/gemini/gemini_gmacreg.h> 44 1.3.2.2 mjf #include <arm/gemini/gemini_gmacvar.h> 45 1.3.2.2 mjf 46 1.3.2.2 mjf #include <net/if.h> 47 1.3.2.2 mjf #include <net/if_ether.h> 48 1.3.2.2 mjf #include <net/if_dl.h> 49 1.3.2.2 mjf 50 1.3.2.2 mjf __KERNEL_RCSID(0, "$NetBSD: if_gmc.c,v 1.3.2.2 2009/01/17 13:27:53 mjf Exp $"); 51 1.3.2.2 mjf 52 1.3.2.2 mjf #define MAX_TXSEG 32 53 1.3.2.2 mjf 54 1.3.2.2 mjf struct gmc_softc { 55 1.3.2.2 mjf device_t sc_dev; 56 1.3.2.2 mjf struct gmac_softc *sc_psc; 57 1.3.2.2 mjf struct gmc_softc *sc_sibling; 58 1.3.2.2 mjf bus_dma_tag_t sc_dmat; 59 1.3.2.2 mjf bus_space_tag_t sc_iot; 60 1.3.2.2 mjf bus_space_handle_t sc_ioh; 61 1.3.2.2 mjf bus_space_handle_t sc_dma_ioh; 62 1.3.2.2 mjf bus_space_handle_t sc_gmac_ioh; 63 1.3.2.2 mjf struct ethercom sc_ec; 64 1.3.2.2 mjf struct mii_data sc_mii; 65 1.3.2.2 mjf void *sc_ih; 66 1.3.2.2 mjf bool sc_port1; 67 1.3.2.2 mjf uint8_t sc_phy; 68 1.3.2.2 mjf gmac_hwqueue_t *sc_rxq; 69 1.3.2.2 mjf gmac_hwqueue_t *sc_txq[6]; 70 1.3.2.2 mjf callout_t sc_mii_ch; 71 1.3.2.2 mjf 72 1.3.2.2 mjf uint32_t sc_gmac_status; 73 1.3.2.2 mjf uint32_t sc_gmac_sta_add[3]; 74 1.3.2.2 mjf uint32_t sc_gmac_mcast_filter[2]; 75 1.3.2.2 mjf uint32_t sc_gmac_rx_filter; 76 1.3.2.2 mjf uint32_t sc_gmac_config[2]; 77 1.3.2.2 mjf uint32_t sc_dmavr; 78 1.3.2.2 mjf 79 1.3.2.2 mjf uint32_t sc_int_mask[5]; 80 1.3.2.2 mjf uint32_t sc_int_enabled[5]; 81 1.3.2.2 mjf }; 82 1.3.2.2 mjf 83 1.3.2.2 mjf #define sc_if sc_ec.ec_if 84 1.3.2.2 mjf 85 1.3.2.2 mjf static bool 86 1.3.2.2 mjf gmc_txqueue(struct gmc_softc *sc, gmac_hwqueue_t *hwq, struct mbuf *m) 87 1.3.2.2 mjf { 88 1.3.2.2 mjf bus_dmamap_t map; 89 1.3.2.2 mjf uint32_t desc0, desc1, desc3; 90 1.3.2.2 mjf struct mbuf *last_m, *m0; 91 1.3.2.2 mjf size_t count, i; 92 1.3.2.2 mjf int error; 93 1.3.2.2 mjf gmac_desc_t *d; 94 1.3.2.2 mjf 95 1.3.2.2 mjf KASSERT(hwq != NULL); 96 1.3.2.2 mjf 97 1.3.2.2 mjf map = gmac_mapcache_get(hwq->hwq_hqm->hqm_mc); 98 1.3.2.2 mjf if (map == NULL) 99 1.3.2.2 mjf return false; 100 1.3.2.2 mjf 101 1.3.2.2 mjf for (last_m = NULL, m0 = m, count = 0; 102 1.3.2.2 mjf m0 != NULL; 103 1.3.2.2 mjf last_m = m0, m0 = m0->m_next) { 104 1.3.2.2 mjf vaddr_t addr = (uintptr_t)m0->m_data; 105 1.3.2.2 mjf if (m0->m_len == 0) 106 1.3.2.2 mjf continue; 107 1.3.2.2 mjf if (addr & 1) { 108 1.3.2.2 mjf if (last_m != NULL && M_TRAILINGSPACE(last_m) > 0) { 109 1.3.2.2 mjf last_m->m_data[last_m->m_len++] = *m->m_data++; 110 1.3.2.2 mjf m->m_len--; 111 1.3.2.2 mjf } else if (M_TRAILINGSPACE(m0) > 0) { 112 1.3.2.2 mjf memmove(m0->m_data + 1, m0->m_data, m0->m_len); 113 1.3.2.2 mjf m0->m_data++; 114 1.3.2.2 mjf } else if (M_LEADINGSPACE(m0) > 0) { 115 1.3.2.2 mjf memmove(m0->m_data - 1, m0->m_data, m0->m_len); 116 1.3.2.2 mjf m0->m_data--; 117 1.3.2.2 mjf } else { 118 1.3.2.2 mjf panic("gmc_txqueue: odd addr %p", m0->m_data); 119 1.3.2.2 mjf } 120 1.3.2.2 mjf } 121 1.3.2.2 mjf count += ((addr & PGOFSET) + m->m_len + PGOFSET) >> PGSHIFT; 122 1.3.2.2 mjf } 123 1.3.2.2 mjf 124 1.3.2.2 mjf gmac_hwqueue_sync(hwq); 125 1.3.2.2 mjf if (hwq->hwq_free <= count) { 126 1.3.2.2 mjf gmac_mapcache_put(hwq->hwq_hqm->hqm_mc, map); 127 1.3.2.2 mjf return false; 128 1.3.2.2 mjf } 129 1.3.2.2 mjf 130 1.3.2.2 mjf error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 131 1.3.2.2 mjf BUS_DMA_WRITE|BUS_DMA_NOWAIT); 132 1.3.2.2 mjf if (error) { 133 1.3.2.2 mjf aprint_error_dev(sc->sc_dev, "ifstart: load failed: %d\n", 134 1.3.2.2 mjf error); 135 1.3.2.2 mjf gmac_mapcache_put(hwq->hwq_hqm->hqm_mc, map); 136 1.3.2.2 mjf m_freem(m); 137 1.3.2.2 mjf sc->sc_if.if_oerrors++; 138 1.3.2.2 mjf return true; 139 1.3.2.2 mjf } 140 1.3.2.2 mjf KASSERT(map->dm_nsegs > 0); 141 1.3.2.2 mjf 142 1.3.2.2 mjf /* 143 1.3.2.2 mjf * Sync the mbuf contents to memory/cache. 144 1.3.2.2 mjf */ 145 1.3.2.2 mjf bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 146 1.3.2.2 mjf BUS_DMASYNC_PREWRITE); 147 1.3.2.2 mjf 148 1.3.2.2 mjf /* 149 1.3.2.2 mjf * Now we need to load the descriptors... 150 1.3.2.2 mjf */ 151 1.3.2.2 mjf desc0 = map->dm_nsegs << 16; 152 1.3.2.2 mjf desc1 = m->m_pkthdr.len; 153 1.3.2.2 mjf desc3 = DESC3_SOF; 154 1.3.2.2 mjf i = 0; 155 1.3.2.2 mjf d = NULL; 156 1.3.2.2 mjf do { 157 1.3.2.2 mjf #if 0 158 1.3.2.2 mjf if (i > 0) 159 1.3.2.2 mjf aprint_debug_dev(sc->sc_dev, 160 1.3.2.2 mjf "gmac_txqueue: %zu@%p=%#x/%#x/%#x/%#x\n", 161 1.3.2.2 mjf i-1, d, d->d_desc0, d->d_desc1, 162 1.3.2.2 mjf d->d_bufaddr, d->d_desc3); 163 1.3.2.2 mjf #endif 164 1.3.2.2 mjf d = gmac_hwqueue_desc(hwq, i); 165 1.3.2.2 mjf KASSERT(map->dm_segs[i].ds_len > 0); 166 1.3.2.2 mjf KASSERT((map->dm_segs[i].ds_addr & 1) == 0); 167 1.3.2.2 mjf d->d_desc0 = htole32(map->dm_segs[i].ds_len | desc0); 168 1.3.2.2 mjf d->d_desc1 = htole32(desc1); 169 1.3.2.2 mjf d->d_bufaddr = htole32(map->dm_segs[i].ds_addr); 170 1.3.2.2 mjf d->d_desc3 = htole32(desc3); 171 1.3.2.2 mjf desc3 = 0; 172 1.3.2.2 mjf } while (++i < map->dm_nsegs); 173 1.3.2.2 mjf 174 1.3.2.2 mjf d->d_desc3 |= htole32(DESC3_EOF|DESC3_EOFIE); 175 1.3.2.2 mjf #if 0 176 1.3.2.2 mjf aprint_debug_dev(sc->sc_dev, 177 1.3.2.2 mjf "gmac_txqueue: %zu@%p=%#x/%#x/%#x/%#x\n", 178 1.3.2.2 mjf i-1, d, d->d_desc0, d->d_desc1, d->d_bufaddr, d->d_desc3); 179 1.3.2.2 mjf #endif 180 1.3.2.2 mjf M_SETCTX(m, map); 181 1.3.2.2 mjf IF_ENQUEUE(&hwq->hwq_ifq, m); 182 1.3.2.2 mjf /* 183 1.3.2.2 mjf * Last descriptor has been marked. Give them to the h/w. 184 1.3.2.2 mjf * This will sync for us. 185 1.3.2.2 mjf */ 186 1.3.2.2 mjf gmac_hwqueue_produce(hwq, map->dm_nsegs); 187 1.3.2.2 mjf #if 0 188 1.3.2.2 mjf aprint_debug_dev(sc->sc_dev, 189 1.3.2.2 mjf "gmac_txqueue: *%zu@%p=%#x/%#x/%#x/%#x\n", 190 1.3.2.2 mjf i-1, d, d->d_desc0, d->d_desc1, d->d_bufaddr, d->d_desc3); 191 1.3.2.2 mjf #endif 192 1.3.2.2 mjf return true; 193 1.3.2.2 mjf } 194 1.3.2.2 mjf 195 1.3.2.2 mjf static void 196 1.3.2.2 mjf gmc_filter_change(struct gmc_softc *sc) 197 1.3.2.2 mjf { 198 1.3.2.2 mjf struct ether_multi *enm; 199 1.3.2.2 mjf struct ether_multistep step; 200 1.3.2.2 mjf uint32_t mhash[2]; 201 1.3.2.2 mjf uint32_t new0, new1, new2; 202 1.3.2.2 mjf const char * const eaddr = CLLADDR(sc->sc_if.if_sadl); 203 1.3.2.2 mjf 204 1.3.2.2 mjf new0 = eaddr[0] | ((eaddr[1] | (eaddr[2] | (eaddr[3] << 8)) << 8) << 8); 205 1.3.2.2 mjf new1 = eaddr[4] | (eaddr[5] << 8); 206 1.3.2.2 mjf new2 = 0; 207 1.3.2.2 mjf if (sc->sc_gmac_sta_add[0] != new0 208 1.3.2.2 mjf || sc->sc_gmac_sta_add[1] != new1 209 1.3.2.2 mjf || sc->sc_gmac_sta_add[2] != new2) { 210 1.3.2.2 mjf bus_space_write_4(sc->sc_iot, sc->sc_gmac_ioh, GMAC_STA_ADD0, 211 1.3.2.2 mjf new0); 212 1.3.2.2 mjf bus_space_write_4(sc->sc_iot, sc->sc_gmac_ioh, GMAC_STA_ADD1, 213 1.3.2.2 mjf new1); 214 1.3.2.2 mjf bus_space_write_4(sc->sc_iot, sc->sc_gmac_ioh, GMAC_STA_ADD2, 215 1.3.2.2 mjf new2); 216 1.3.2.2 mjf sc->sc_gmac_sta_add[0] = new0; 217 1.3.2.2 mjf sc->sc_gmac_sta_add[1] = new1; 218 1.3.2.2 mjf sc->sc_gmac_sta_add[2] = new2; 219 1.3.2.2 mjf } 220 1.3.2.2 mjf 221 1.3.2.2 mjf mhash[0] = 0; 222 1.3.2.2 mjf mhash[1] = 0; 223 1.3.2.2 mjf ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 224 1.3.2.2 mjf while (enm != NULL) { 225 1.3.2.2 mjf size_t i; 226 1.3.2.2 mjf if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 227 1.3.2.2 mjf mhash[0] = mhash[1] = 0xffffffff; 228 1.3.2.2 mjf break; 229 1.3.2.2 mjf } 230 1.3.2.2 mjf i = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 231 1.3.2.2 mjf mhash[(i >> 5) & 1] |= 1 << (i & 31); 232 1.3.2.2 mjf ETHER_NEXT_MULTI(step, enm); 233 1.3.2.2 mjf } 234 1.3.2.2 mjf 235 1.3.2.2 mjf if (sc->sc_gmac_mcast_filter[0] != mhash[0] 236 1.3.2.2 mjf || sc->sc_gmac_mcast_filter[1] != mhash[1]) { 237 1.3.2.2 mjf bus_space_write_4(sc->sc_iot, sc->sc_gmac_ioh, 238 1.3.2.2 mjf GMAC_MCAST_FILTER0, mhash[0]); 239 1.3.2.2 mjf bus_space_write_4(sc->sc_iot, sc->sc_gmac_ioh, 240 1.3.2.2 mjf GMAC_MCAST_FILTER1, mhash[1]); 241 1.3.2.2 mjf sc->sc_gmac_mcast_filter[0] = mhash[0]; 242 1.3.2.2 mjf sc->sc_gmac_mcast_filter[1] = mhash[1]; 243 1.3.2.2 mjf } 244 1.3.2.2 mjf 245 1.3.2.2 mjf new0 = sc->sc_gmac_rx_filter & ~RXFILTER_PROMISC; 246 1.3.2.2 mjf new0 |= RXFILTER_BROADCAST | RXFILTER_UNICAST | RXFILTER_MULTICAST; 247 1.3.2.2 mjf if (sc->sc_if.if_flags & IFF_PROMISC) 248 1.3.2.2 mjf new0 |= RXFILTER_PROMISC; 249 1.3.2.2 mjf 250 1.3.2.2 mjf if (new0 != sc->sc_gmac_rx_filter) { 251 1.3.2.2 mjf bus_space_write_4(sc->sc_iot, sc->sc_gmac_ioh, GMAC_RX_FILTER, 252 1.3.2.2 mjf new0); 253 1.3.2.2 mjf sc->sc_gmac_rx_filter = new0; 254 1.3.2.2 mjf } 255 1.3.2.2 mjf } 256 1.3.2.2 mjf 257 1.3.2.2 mjf static void 258 1.3.2.2 mjf gmc_mii_tick(void *arg) 259 1.3.2.2 mjf { 260 1.3.2.2 mjf struct gmc_softc * const sc = arg; 261 1.3.2.2 mjf struct gmac_softc * const psc = sc->sc_psc; 262 1.3.2.2 mjf int s = splnet(); 263 1.3.2.2 mjf 264 1.3.2.2 mjf /* 265 1.3.2.2 mjf * If we had to increase the number of receive mbufs due to fifo 266 1.3.2.2 mjf * overflows, we need a way to decrease them. So every second we 267 1.3.2.2 mjf * recieve less than or equal to MIN_RXMAPS packets, we decrement 268 1.3.2.2 mjf * swfree_min until it returns to MIN_RXMAPS. 269 1.3.2.2 mjf */ 270 1.3.2.2 mjf if (psc->sc_rxpkts_per_sec <= MIN_RXMAPS 271 1.3.2.2 mjf && psc->sc_swfree_min > MIN_RXMAPS) { 272 1.3.2.2 mjf psc->sc_swfree_min--; 273 1.3.2.2 mjf gmac_swfree_min_update(psc); 274 1.3.2.2 mjf } 275 1.3.2.2 mjf /* 276 1.3.2.2 mjf * If only one GMAC is running or this is port0, reset the count. 277 1.3.2.2 mjf */ 278 1.3.2.2 mjf if (psc->sc_running != 3 || !sc->sc_port1) 279 1.3.2.2 mjf psc->sc_rxpkts_per_sec = 0; 280 1.3.2.2 mjf 281 1.3.2.2 mjf mii_tick(&sc->sc_mii); 282 1.3.2.2 mjf if (sc->sc_if.if_flags & IFF_RUNNING) 283 1.3.2.2 mjf callout_schedule(&sc->sc_mii_ch, hz); 284 1.3.2.2 mjf 285 1.3.2.2 mjf splx(s); 286 1.3.2.2 mjf } 287 1.3.2.2 mjf 288 1.3.2.2 mjf static int 289 1.3.2.2 mjf gmc_mediachange(struct ifnet *ifp) 290 1.3.2.2 mjf { 291 1.3.2.2 mjf struct gmc_softc * const sc = ifp->if_softc; 292 1.3.2.2 mjf 293 1.3.2.2 mjf if ((ifp->if_flags & IFF_UP) == 0) 294 1.3.2.2 mjf return 0; 295 1.3.2.2 mjf 296 1.3.2.2 mjf return mii_mediachg(&sc->sc_mii); 297 1.3.2.2 mjf } 298 1.3.2.2 mjf 299 1.3.2.2 mjf static void 300 1.3.2.2 mjf gmc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 301 1.3.2.2 mjf { 302 1.3.2.2 mjf struct gmc_softc * const sc = ifp->if_softc; 303 1.3.2.2 mjf 304 1.3.2.2 mjf mii_pollstat(&sc->sc_mii); 305 1.3.2.2 mjf ifmr->ifm_status = sc->sc_mii.mii_media_status; 306 1.3.2.2 mjf ifmr->ifm_active = sc->sc_mii.mii_media_active; 307 1.3.2.2 mjf } 308 1.3.2.2 mjf 309 1.3.2.2 mjf static void 310 1.3.2.2 mjf gmc_mii_statchg(device_t self) 311 1.3.2.2 mjf { 312 1.3.2.2 mjf struct gmc_softc * const sc = device_private(self); 313 1.3.2.2 mjf uint32_t gmac_status; 314 1.3.2.2 mjf 315 1.3.2.2 mjf gmac_status = sc->sc_gmac_status; 316 1.3.2.2 mjf 317 1.3.2.2 mjf gmac_status &= ~STATUS_PHYMODE_MASK; 318 1.3.2.2 mjf gmac_status |= STATUS_PHYMODE_RGMII_A; 319 1.3.2.2 mjf 320 1.3.2.2 mjf gmac_status &= ~STATUS_SPEED_MASK; 321 1.3.2.2 mjf if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_1000_T) { 322 1.3.2.2 mjf gmac_status |= STATUS_SPEED_1000M; 323 1.3.2.2 mjf } else if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_100_TX) { 324 1.3.2.2 mjf gmac_status |= STATUS_SPEED_100M; 325 1.3.2.2 mjf } else { 326 1.3.2.2 mjf gmac_status |= STATUS_SPEED_10M; 327 1.3.2.2 mjf } 328 1.3.2.2 mjf 329 1.3.2.2 mjf if (sc->sc_mii.mii_media_active & IFM_FDX) 330 1.3.2.2 mjf gmac_status |= STATUS_DUPLEX_FULL; 331 1.3.2.2 mjf else 332 1.3.2.2 mjf gmac_status &= ~STATUS_DUPLEX_FULL; 333 1.3.2.2 mjf 334 1.3.2.2 mjf if (sc->sc_mii.mii_media_status & IFM_ACTIVE) 335 1.3.2.2 mjf gmac_status |= STATUS_LINK_ON; 336 1.3.2.2 mjf else 337 1.3.2.2 mjf gmac_status &= ~STATUS_LINK_ON; 338 1.3.2.2 mjf 339 1.3.2.2 mjf if (sc->sc_gmac_status != gmac_status) { 340 1.3.2.2 mjf aprint_debug_dev(sc->sc_dev, 341 1.3.2.2 mjf "status change old=%#x new=%#x active=%#x\n", 342 1.3.2.2 mjf sc->sc_gmac_status, gmac_status, 343 1.3.2.2 mjf sc->sc_mii.mii_media_active); 344 1.3.2.2 mjf sc->sc_gmac_status = gmac_status; 345 1.3.2.2 mjf bus_space_write_4(sc->sc_iot, sc->sc_gmac_ioh, GMAC_STATUS, 346 1.3.2.2 mjf sc->sc_gmac_status); 347 1.3.2.2 mjf } 348 1.3.2.2 mjf 349 1.3.2.2 mjf (*sc->sc_mii.mii_writereg)(sc->sc_dev, sc->sc_phy, 0x0018, 0x0041); 350 1.3.2.2 mjf } 351 1.3.2.2 mjf 352 1.3.2.2 mjf static int 353 1.3.2.2 mjf gmc_ifioctl(struct ifnet *ifp, u_long cmd, void *data) 354 1.3.2.2 mjf { 355 1.3.2.2 mjf struct gmc_softc * const sc = ifp->if_softc; 356 1.3.2.2 mjf struct ifreq * const ifr = data; 357 1.3.2.2 mjf int s; 358 1.3.2.2 mjf int error; 359 1.3.2.2 mjf s = splnet(); 360 1.3.2.2 mjf 361 1.3.2.2 mjf switch (cmd) { 362 1.3.2.2 mjf case SIOCSIFMEDIA: 363 1.3.2.2 mjf case SIOCGIFMEDIA: 364 1.3.2.2 mjf error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 365 1.3.2.2 mjf break; 366 1.3.2.2 mjf default: 367 1.3.2.2 mjf error = ether_ioctl(ifp, cmd, data); 368 1.3.2.2 mjf if (error == ENETRESET) { 369 1.3.2.2 mjf if (ifp->if_flags & IFF_RUNNING) { 370 1.3.2.2 mjf /* 371 1.3.2.2 mjf * If the interface is running, we have to 372 1.3.2.2 mjf * update its multicast filter. 373 1.3.2.2 mjf */ 374 1.3.2.2 mjf gmc_filter_change(sc); 375 1.3.2.2 mjf } 376 1.3.2.2 mjf error = 0; 377 1.3.2.2 mjf } 378 1.3.2.2 mjf } 379 1.3.2.2 mjf 380 1.3.2.2 mjf splx(s); 381 1.3.2.2 mjf return error; 382 1.3.2.2 mjf } 383 1.3.2.2 mjf 384 1.3.2.2 mjf static void 385 1.3.2.2 mjf gmc_ifstart(struct ifnet *ifp) 386 1.3.2.2 mjf { 387 1.3.2.2 mjf struct gmc_softc * const sc = ifp->if_softc; 388 1.3.2.2 mjf 389 1.3.2.2 mjf #if 0 390 1.3.2.2 mjf if ((sc->sc_gmac_status & STATUS_LINK_ON) == 0) 391 1.3.2.2 mjf return; 392 1.3.2.2 mjf #endif 393 1.3.2.2 mjf if ((ifp->if_flags & IFF_RUNNING) == 0) 394 1.3.2.2 mjf return; 395 1.3.2.2 mjf 396 1.3.2.2 mjf for (;;) { 397 1.3.2.2 mjf struct mbuf *m; 398 1.3.2.2 mjf IF_DEQUEUE(&ifp->if_snd, m); 399 1.3.2.2 mjf if (m == NULL) 400 1.3.2.2 mjf break; 401 1.3.2.2 mjf if (!gmc_txqueue(sc, sc->sc_txq[0], m)) { 402 1.3.2.2 mjf IF_PREPEND(&ifp->if_snd, m); 403 1.3.2.2 mjf ifp->if_flags |= IFF_OACTIVE; 404 1.3.2.2 mjf break; 405 1.3.2.2 mjf } 406 1.3.2.2 mjf } 407 1.3.2.2 mjf } 408 1.3.2.2 mjf 409 1.3.2.2 mjf static void 410 1.3.2.2 mjf gmc_ifstop(struct ifnet *ifp, int disable) 411 1.3.2.2 mjf { 412 1.3.2.2 mjf struct gmc_softc * const sc = ifp->if_softc; 413 1.3.2.2 mjf struct gmac_softc * const psc = sc->sc_psc; 414 1.3.2.2 mjf 415 1.3.2.2 mjf psc->sc_running &= ~(sc->sc_port1 ? 2 : 1); 416 1.3.2.2 mjf psc->sc_int_enabled[0] &= ~sc->sc_int_enabled[0]; 417 1.3.2.2 mjf psc->sc_int_enabled[1] &= ~sc->sc_int_enabled[1]; 418 1.3.2.2 mjf psc->sc_int_enabled[2] &= ~sc->sc_int_enabled[2]; 419 1.3.2.2 mjf psc->sc_int_enabled[3] &= ~sc->sc_int_enabled[3]; 420 1.3.2.2 mjf psc->sc_int_enabled[4] &= ~sc->sc_int_enabled[4] | INT4_SW_FREEQ_EMPTY; 421 1.3.2.2 mjf if (psc->sc_running == 0) { 422 1.3.2.2 mjf psc->sc_int_enabled[4] &= ~INT4_SW_FREEQ_EMPTY; 423 1.3.2.2 mjf KASSERT(psc->sc_int_enabled[0] == 0); 424 1.3.2.2 mjf KASSERT(psc->sc_int_enabled[1] == 0); 425 1.3.2.2 mjf KASSERT(psc->sc_int_enabled[2] == 0); 426 1.3.2.2 mjf KASSERT(psc->sc_int_enabled[3] == 0); 427 1.3.2.2 mjf KASSERT(psc->sc_int_enabled[4] == 0); 428 1.3.2.2 mjf } else if (((psc->sc_int_select[4] & INT4_SW_FREEQ_EMPTY) != 0) 429 1.3.2.2 mjf == sc->sc_port1) { 430 1.3.2.2 mjf psc->sc_int_select[4] &= ~INT4_SW_FREEQ_EMPTY; 431 1.3.2.2 mjf bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_MASK, 432 1.3.2.2 mjf psc->sc_int_select[4]); 433 1.3.2.2 mjf } 434 1.3.2.2 mjf gmac_intr_update(psc); 435 1.3.2.2 mjf if (disable) { 436 1.3.2.2 mjf #if 0 437 1.3.2.2 mjf if (psc->sc_running == 0) { 438 1.3.2.2 mjf gmac_mapcache_destroy(&psc->sc_txmaps); 439 1.3.2.2 mjf gmac_mapcache_destroy(&psc->sc_rxmaps); 440 1.3.2.2 mjf } 441 1.3.2.2 mjf #endif 442 1.3.2.2 mjf } 443 1.3.2.2 mjf } 444 1.3.2.2 mjf 445 1.3.2.2 mjf static int 446 1.3.2.2 mjf gmc_ifinit(struct ifnet *ifp) 447 1.3.2.2 mjf { 448 1.3.2.2 mjf struct gmc_softc * const sc = ifp->if_softc; 449 1.3.2.2 mjf struct gmac_softc * const psc = sc->sc_psc; 450 1.3.2.2 mjf uint32_t new, mask; 451 1.3.2.2 mjf 452 1.3.2.2 mjf gmac_mapcache_fill(psc->sc_rxmaps, MIN_RXMAPS); 453 1.3.2.2 mjf gmac_mapcache_fill(psc->sc_txmaps, MIN_TXMAPS); 454 1.3.2.2 mjf 455 1.3.2.2 mjf if (sc->sc_rxq == NULL) { 456 1.3.2.2 mjf gmac_hwqmem_t *hqm; 457 1.3.2.2 mjf hqm = gmac_hwqmem_create(psc->sc_rxmaps, 16, /*RXQ_NDESCS,*/ 1, 458 1.3.2.2 mjf HQM_CONSUMER|HQM_RX); 459 1.3.2.2 mjf sc->sc_rxq = gmac_hwqueue_create(hqm, sc->sc_iot, 460 1.3.2.2 mjf sc->sc_ioh, GMAC_DEF_RXQn_RWPTR(sc->sc_port1), 461 1.3.2.2 mjf GMAC_DEF_RXQn_BASE(sc->sc_port1), 0); 462 1.3.2.2 mjf if (sc->sc_rxq == NULL) { 463 1.3.2.2 mjf gmac_hwqmem_destroy(hqm); 464 1.3.2.2 mjf goto failed; 465 1.3.2.2 mjf } 466 1.3.2.2 mjf sc->sc_rxq->hwq_ifp = ifp; 467 1.3.2.2 mjf sc->sc_rxq->hwq_producer = psc->sc_swfreeq; 468 1.3.2.2 mjf } 469 1.3.2.2 mjf 470 1.3.2.2 mjf if (sc->sc_txq[0] == NULL) { 471 1.3.2.2 mjf gmac_hwqueue_t *hwq, *last_hwq; 472 1.3.2.2 mjf gmac_hwqmem_t *hqm; 473 1.3.2.2 mjf size_t i; 474 1.3.2.2 mjf 475 1.3.2.2 mjf hqm = gmac_hwqmem_create(psc->sc_txmaps, TXQ_NDESCS, 6, 476 1.3.2.2 mjf HQM_PRODUCER|HQM_TX); 477 1.3.2.2 mjf KASSERT(hqm != NULL); 478 1.3.2.2 mjf for (i = 0; i < __arraycount(sc->sc_txq); i++) { 479 1.3.2.2 mjf sc->sc_txq[i] = gmac_hwqueue_create(hqm, sc->sc_iot, 480 1.3.2.2 mjf sc->sc_dma_ioh, GMAC_SW_TX_Qn_RWPTR(i), 481 1.3.2.2 mjf GMAC_SW_TX_Q_BASE, i); 482 1.3.2.2 mjf if (sc->sc_txq[i] == NULL) { 483 1.3.2.2 mjf if (i == 0) 484 1.3.2.2 mjf gmac_hwqmem_destroy(hqm); 485 1.3.2.2 mjf goto failed; 486 1.3.2.2 mjf } 487 1.3.2.2 mjf sc->sc_txq[i]->hwq_ifp = ifp; 488 1.3.2.2 mjf 489 1.3.2.2 mjf last_hwq = NULL; 490 1.3.2.2 mjf SLIST_FOREACH(hwq, &psc->sc_hwfreeq->hwq_producers, 491 1.3.2.2 mjf hwq_link) { 492 1.3.2.2 mjf if (sc->sc_txq[i]->hwq_qoff < hwq->hwq_qoff) 493 1.3.2.2 mjf break; 494 1.3.2.2 mjf last_hwq = hwq; 495 1.3.2.2 mjf } 496 1.3.2.2 mjf if (last_hwq == NULL) 497 1.3.2.2 mjf SLIST_INSERT_HEAD( 498 1.3.2.2 mjf &psc->sc_hwfreeq->hwq_producers, 499 1.3.2.2 mjf sc->sc_txq[i], hwq_link); 500 1.3.2.2 mjf else 501 1.3.2.2 mjf SLIST_INSERT_AFTER(last_hwq, sc->sc_txq[i], 502 1.3.2.2 mjf hwq_link); 503 1.3.2.2 mjf } 504 1.3.2.2 mjf } 505 1.3.2.2 mjf 506 1.3.2.2 mjf gmc_filter_change(sc); 507 1.3.2.2 mjf 508 1.3.2.2 mjf mask = DMAVR_LOOPBACK|DMAVR_DROP_SMALL_ACK|DMAVR_EXTRABYTES_MASK 509 1.3.2.2 mjf |DMAVR_RXBURSTSIZE_MASK|DMAVR_RXBUSWIDTH_MASK 510 1.3.2.2 mjf |DMAVR_TXBURSTSIZE_MASK|DMAVR_TXBUSWIDTH_MASK; 511 1.3.2.2 mjf new = DMAVR_RXDMA_ENABLE|DMAVR_TXDMA_ENABLE 512 1.3.2.2 mjf |DMAVR_EXTRABYTES(2) 513 1.3.2.2 mjf |DMAVR_RXBURSTSIZE(DMAVR_BURSTSIZE_32W) 514 1.3.2.2 mjf |DMAVR_RXBUSWIDTH(DMAVR_BUSWIDTH_32BITS) 515 1.3.2.2 mjf |DMAVR_TXBURSTSIZE(DMAVR_BURSTSIZE_32W) 516 1.3.2.2 mjf |DMAVR_TXBUSWIDTH(DMAVR_BUSWIDTH_32BITS); 517 1.3.2.2 mjf new |= sc->sc_dmavr & ~mask; 518 1.3.2.2 mjf if (sc->sc_dmavr != new) { 519 1.3.2.2 mjf sc->sc_dmavr = new; 520 1.3.2.2 mjf bus_space_write_4(sc->sc_iot, sc->sc_dma_ioh, GMAC_DMAVR, 521 1.3.2.2 mjf sc->sc_dmavr); 522 1.3.2.2 mjf aprint_debug_dev(sc->sc_dev, "gmc_ifinit: dmavr=%#x/%#x\n", 523 1.3.2.2 mjf sc->sc_dmavr, 524 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh, GMAC_DMAVR)); 525 1.3.2.2 mjf } 526 1.3.2.2 mjf 527 1.3.2.2 mjf mask = CONFIG0_MAXLEN_MASK|CONFIG0_TX_DISABLE|CONFIG0_RX_DISABLE 528 1.3.2.2 mjf |CONFIG0_LOOPBACK|/*CONFIG0_SIM_TEST|*/CONFIG0_INVERSE_RXC_RGMII 529 1.3.2.2 mjf |CONFIG0_RGMII_INBAND_STATUS_ENABLE; 530 1.3.2.2 mjf new = CONFIG0_MAXLEN(CONFIG0_MAXLEN_1536)|CONFIG0_R_LATCHED_MMII; 531 1.3.2.2 mjf new |= (sc->sc_gmac_config[0] & ~mask); 532 1.3.2.2 mjf if (sc->sc_gmac_config[0] != new) { 533 1.3.2.2 mjf sc->sc_gmac_config[0] = new; 534 1.3.2.2 mjf bus_space_write_4(sc->sc_iot, sc->sc_gmac_ioh, GMAC_CONFIG0, 535 1.3.2.2 mjf sc->sc_gmac_config[0]); 536 1.3.2.2 mjf aprint_debug_dev(sc->sc_dev, "gmc_ifinit: config0=%#x/%#x\n", 537 1.3.2.2 mjf sc->sc_gmac_config[0], 538 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_gmac_ioh, GMAC_CONFIG0)); 539 1.3.2.2 mjf } 540 1.3.2.2 mjf 541 1.3.2.2 mjf psc->sc_rxpkts_per_sec += 542 1.3.2.2 mjf gmac_rxproduce(psc->sc_swfreeq, psc->sc_swfree_min); 543 1.3.2.2 mjf 544 1.3.2.2 mjf /* 545 1.3.2.2 mjf * If we will be the only active interface, make sure the sw freeq 546 1.3.2.2 mjf * interrupt gets routed to use. 547 1.3.2.2 mjf */ 548 1.3.2.2 mjf if (psc->sc_running == 0 549 1.3.2.2 mjf && (((psc->sc_int_select[4] & INT4_SW_FREEQ_EMPTY) != 0) != sc->sc_port1)) { 550 1.3.2.2 mjf psc->sc_int_select[4] ^= INT4_SW_FREEQ_EMPTY; 551 1.3.2.2 mjf bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_MASK, 552 1.3.2.2 mjf psc->sc_int_select[4]); 553 1.3.2.2 mjf } 554 1.3.2.2 mjf sc->sc_int_enabled[0] = sc->sc_int_mask[0] 555 1.3.2.2 mjf & (INT0_TXDERR|INT0_TXPERR|INT0_RXDERR|INT0_RXPERR|INT0_SWTXQ_EOF); 556 1.3.2.2 mjf sc->sc_int_enabled[1] = sc->sc_int_mask[1] & INT1_DEF_RXQ_EOF; 557 1.3.2.2 mjf sc->sc_int_enabled[4] = INT4_SW_FREEQ_EMPTY | (sc->sc_int_mask[4] 558 1.3.2.2 mjf & (INT4_TX_FAIL|INT4_MIB_HEMIWRAP|INT4_RX_FIFO_OVRN 559 1.3.2.2 mjf |INT4_RGMII_STSCHG)); 560 1.3.2.2 mjf 561 1.3.2.2 mjf psc->sc_int_enabled[0] |= sc->sc_int_enabled[0]; 562 1.3.2.2 mjf psc->sc_int_enabled[1] |= sc->sc_int_enabled[1]; 563 1.3.2.2 mjf psc->sc_int_enabled[4] |= sc->sc_int_enabled[4]; 564 1.3.2.2 mjf 565 1.3.2.2 mjf gmac_intr_update(psc); 566 1.3.2.2 mjf 567 1.3.2.2 mjf if ((ifp->if_flags & IFF_RUNNING) == 0) 568 1.3.2.2 mjf mii_tick(&sc->sc_mii); 569 1.3.2.2 mjf 570 1.3.2.2 mjf ifp->if_flags |= IFF_RUNNING; 571 1.3.2.2 mjf psc->sc_running |= (sc->sc_port1 ? 2 : 1); 572 1.3.2.2 mjf 573 1.3.2.2 mjf callout_schedule(&sc->sc_mii_ch, hz); 574 1.3.2.2 mjf 575 1.3.2.2 mjf return 0; 576 1.3.2.2 mjf 577 1.3.2.2 mjf failed: 578 1.3.2.2 mjf gmc_ifstop(ifp, true); 579 1.3.2.2 mjf return ENOMEM; 580 1.3.2.2 mjf } 581 1.3.2.2 mjf 582 1.3.2.2 mjf static int 583 1.3.2.2 mjf gmc_intr(void *arg) 584 1.3.2.2 mjf { 585 1.3.2.2 mjf struct gmc_softc * const sc = arg; 586 1.3.2.2 mjf uint32_t int0_status, int1_status, int4_status; 587 1.3.2.2 mjf uint32_t status; 588 1.3.2.2 mjf bool do_ifstart = false; 589 1.3.2.2 mjf int rv = 0; 590 1.3.2.2 mjf 591 1.3.2.2 mjf aprint_debug_dev(sc->sc_dev, "gmac_intr: entry\n"); 592 1.3.2.2 mjf 593 1.3.2.2 mjf int0_status = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 594 1.3.2.2 mjf GMAC_INT0_STATUS); 595 1.3.2.2 mjf int1_status = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 596 1.3.2.2 mjf GMAC_INT1_STATUS); 597 1.3.2.2 mjf int4_status = bus_space_read_4(sc->sc_iot, sc->sc_ioh, 598 1.3.2.2 mjf GMAC_INT4_STATUS); 599 1.3.2.2 mjf 600 1.3.2.2 mjf aprint_debug_dev(sc->sc_dev, "gmac_intr: sts=%#x/%#x/%#x/%#x/%#x\n", 601 1.3.2.2 mjf int0_status, int1_status, 602 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_STATUS), 603 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_STATUS), 604 1.3.2.2 mjf int4_status); 605 1.3.2.2 mjf 606 1.3.2.2 mjf #if 0 607 1.3.2.2 mjf aprint_debug_dev(sc->sc_dev, "gmac_intr: mask=%#x/%#x/%#x/%#x/%#x\n", 608 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_MASK), 609 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_MASK), 610 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_MASK), 611 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_MASK), 612 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_MASK)); 613 1.3.2.2 mjf #endif 614 1.3.2.2 mjf 615 1.3.2.2 mjf status = int0_status & sc->sc_int_mask[0]; 616 1.3.2.2 mjf if (status & (INT0_TXDERR|INT0_TXPERR)) { 617 1.3.2.2 mjf aprint_error_dev(sc->sc_dev, 618 1.3.2.2 mjf "transmit%s%s error: %#x %08x bufaddr %#x\n", 619 1.3.2.2 mjf status & INT0_TXDERR ? " data" : "", 620 1.3.2.2 mjf status & INT0_TXPERR ? " protocol" : "", 621 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh, 622 1.3.2.2 mjf GMAC_DMA_TX_CUR_DESC), 623 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh, 624 1.3.2.2 mjf GMAC_SW_TX_Q0_RWPTR), 625 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh, 626 1.3.2.2 mjf GMAC_DMA_TX_DESC2)); 627 1.3.2.2 mjf bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_STATUS, 628 1.3.2.2 mjf status & (INT0_TXDERR|INT0_TXPERR)); 629 1.3.2.2 mjf Debugger(); 630 1.3.2.2 mjf } 631 1.3.2.2 mjf if (status & (INT0_RXDERR|INT0_RXPERR)) { 632 1.3.2.2 mjf aprint_error_dev(sc->sc_dev, 633 1.3.2.2 mjf "receive%s%s error: %#x %#x=%#x/%#x/%#x/%#x\n", 634 1.3.2.2 mjf status & INT0_RXDERR ? " data" : "", 635 1.3.2.2 mjf status & INT0_RXPERR ? " protocol" : "", 636 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh, 637 1.3.2.2 mjf GMAC_DMA_RX_CUR_DESC), 638 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_ioh, 639 1.3.2.2 mjf GMAC_SWFREEQ_RWPTR), 640 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh, 641 1.3.2.2 mjf GMAC_DMA_RX_DESC0), 642 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh, 643 1.3.2.2 mjf GMAC_DMA_RX_DESC1), 644 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh, 645 1.3.2.2 mjf GMAC_DMA_RX_DESC2), 646 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh, 647 1.3.2.2 mjf GMAC_DMA_RX_DESC3)); 648 1.3.2.2 mjf bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_STATUS, 649 1.3.2.2 mjf status & (INT0_RXDERR|INT0_RXPERR)); 650 1.3.2.2 mjf Debugger(); 651 1.3.2.2 mjf } 652 1.3.2.2 mjf if (status & INT0_SWTXQ_EOF) { 653 1.3.2.2 mjf status &= INT0_SWTXQ_EOF; 654 1.3.2.2 mjf for (int i = 0; status && i < __arraycount(sc->sc_txq); i++) { 655 1.3.2.2 mjf if (status & INT0_SWTXQn_EOF(i)) { 656 1.3.2.2 mjf gmac_hwqueue_sync(sc->sc_txq[i]); 657 1.3.2.2 mjf bus_space_write_4(sc->sc_iot, sc->sc_ioh, 658 1.3.2.2 mjf GMAC_INT0_STATUS, 659 1.3.2.2 mjf sc->sc_int_mask[0] & (INT0_SWTXQn_EOF(i)|INT0_SWTXQn_FIN(i))); 660 1.3.2.2 mjf status &= ~INT0_SWTXQn_EOF(i); 661 1.3.2.2 mjf } 662 1.3.2.2 mjf } 663 1.3.2.2 mjf do_ifstart = true; 664 1.3.2.2 mjf rv = 1; 665 1.3.2.2 mjf } 666 1.3.2.2 mjf 667 1.3.2.2 mjf if (int4_status & INT4_SW_FREEQ_EMPTY) { 668 1.3.2.2 mjf struct gmac_softc * const psc = sc->sc_psc; 669 1.3.2.2 mjf psc->sc_rxpkts_per_sec += 670 1.3.2.2 mjf gmac_rxproduce(psc->sc_swfreeq, psc->sc_swfree_min); 671 1.3.2.2 mjf bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_STATUS, 672 1.3.2.2 mjf status & INT4_SW_FREEQ_EMPTY); 673 1.3.2.2 mjf rv = 1; 674 1.3.2.2 mjf } 675 1.3.2.2 mjf 676 1.3.2.2 mjf status = int1_status & sc->sc_int_mask[1]; 677 1.3.2.2 mjf if (status & INT1_DEF_RXQ_EOF) { 678 1.3.2.2 mjf struct gmac_softc * const psc = sc->sc_psc; 679 1.3.2.2 mjf psc->sc_rxpkts_per_sec += 680 1.3.2.2 mjf gmac_hwqueue_consume(sc->sc_rxq, psc->sc_swfree_min); 681 1.3.2.2 mjf bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_STATUS, 682 1.3.2.2 mjf status & INT1_DEF_RXQ_EOF); 683 1.3.2.2 mjf rv = 1; 684 1.3.2.2 mjf } 685 1.3.2.2 mjf 686 1.3.2.2 mjf status = int4_status & sc->sc_int_enabled[4]; 687 1.3.2.2 mjf if (status & INT4_TX_FAIL) { 688 1.3.2.2 mjf } 689 1.3.2.2 mjf if (status & INT4_MIB_HEMIWRAP) { 690 1.3.2.2 mjf } 691 1.3.2.2 mjf if (status & INT4_RX_XON) { 692 1.3.2.2 mjf } 693 1.3.2.2 mjf if (status & INT4_RX_XOFF) { 694 1.3.2.2 mjf } 695 1.3.2.2 mjf if (status & INT4_TX_XON) { 696 1.3.2.2 mjf } 697 1.3.2.2 mjf if (status & INT4_TX_XOFF) { 698 1.3.2.2 mjf } 699 1.3.2.2 mjf if (status & INT4_RX_FIFO_OVRN) { 700 1.3.2.2 mjf #if 0 701 1.3.2.2 mjf if (sc->sc_psc->sc_swfree_min < MAX_RXMAPS) { 702 1.3.2.2 mjf sc->sc_psc->sc_swfree_min++; 703 1.3.2.2 mjf gmac_swfree_min_update(psc); 704 1.3.2.2 mjf } 705 1.3.2.2 mjf #endif 706 1.3.2.2 mjf sc->sc_if.if_ierrors++; 707 1.3.2.2 mjf } 708 1.3.2.2 mjf if (status & INT4_RGMII_STSCHG) { 709 1.3.2.2 mjf mii_tick(&sc->sc_mii); 710 1.3.2.2 mjf } 711 1.3.2.2 mjf bus_space_write_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_STATUS, status); 712 1.3.2.2 mjf 713 1.3.2.2 mjf if (do_ifstart) 714 1.3.2.2 mjf gmc_ifstart(&sc->sc_if); 715 1.3.2.2 mjf 716 1.3.2.2 mjf aprint_debug_dev(sc->sc_dev, "gmac_intr: sts=%#x/%#x/%#x/%#x/%#x\n", 717 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT0_STATUS), 718 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT1_STATUS), 719 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT2_STATUS), 720 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT3_STATUS), 721 1.3.2.2 mjf bus_space_read_4(sc->sc_iot, sc->sc_ioh, GMAC_INT4_STATUS)); 722 1.3.2.2 mjf aprint_debug_dev(sc->sc_dev, "gmac_intr: exit rv=%d\n", rv); 723 1.3.2.2 mjf return rv; 724 1.3.2.2 mjf } 725 1.3.2.2 mjf 726 1.3.2.2 mjf static int 727 1.3.2.2 mjf gmc_match(device_t parent, cfdata_t cf, void *aux) 728 1.3.2.2 mjf { 729 1.3.2.2 mjf struct gmac_softc *psc = device_private(parent); 730 1.3.2.2 mjf struct gmac_attach_args *gma = aux; 731 1.3.2.2 mjf 732 1.3.2.2 mjf if ((unsigned int)gma->gma_phy > 31) 733 1.3.2.2 mjf return 0; 734 1.3.2.2 mjf if ((unsigned int)gma->gma_port > 1) 735 1.3.2.2 mjf return 0; 736 1.3.2.2 mjf if (gma->gma_intr < 1 || gma->gma_intr > 2) 737 1.3.2.2 mjf return 0; 738 1.3.2.2 mjf 739 1.3.2.2 mjf if (psc->sc_ports & (1 << gma->gma_port)) 740 1.3.2.2 mjf return 0; 741 1.3.2.2 mjf 742 1.3.2.2 mjf return 1; 743 1.3.2.2 mjf } 744 1.3.2.2 mjf 745 1.3.2.2 mjf static void 746 1.3.2.2 mjf gmc_attach(device_t parent, device_t self, void *aux) 747 1.3.2.2 mjf { 748 1.3.2.2 mjf struct gmac_softc * const psc = device_private(parent); 749 1.3.2.2 mjf struct gmc_softc * const sc = device_private(self); 750 1.3.2.2 mjf struct gmac_attach_args *gma = aux; 751 1.3.2.2 mjf struct ifnet * const ifp = &sc->sc_if; 752 1.3.2.2 mjf static const char eaddrs[2][6] = { 753 1.3.2.2 mjf "\x0\x52\xc3\x11\x22\x33", 754 1.3.2.2 mjf "\x0\x52\xc3\x44\x55\x66", 755 1.3.2.2 mjf }; 756 1.3.2.2 mjf 757 1.3.2.2 mjf psc->sc_ports |= 1 << gma->gma_port; 758 1.3.2.2 mjf sc->sc_port1 = (gma->gma_port == 1); 759 1.3.2.2 mjf sc->sc_phy = gma->gma_phy; 760 1.3.2.2 mjf 761 1.3.2.2 mjf sc->sc_dev = self; 762 1.3.2.2 mjf sc->sc_psc = psc; 763 1.3.2.2 mjf sc->sc_iot = psc->sc_iot; 764 1.3.2.2 mjf sc->sc_ioh = psc->sc_ioh; 765 1.3.2.2 mjf sc->sc_dmat = psc->sc_dmat; 766 1.3.2.2 mjf 767 1.3.2.2 mjf bus_space_subregion(sc->sc_iot, sc->sc_ioh, 768 1.3.2.2 mjf GMAC_PORTn_DMA_OFFSET(gma->gma_port), GMAC_PORTn_DMA_SIZE, 769 1.3.2.2 mjf &sc->sc_dma_ioh); 770 1.3.2.2 mjf bus_space_subregion(sc->sc_iot, sc->sc_ioh, 771 1.3.2.2 mjf GMAC_PORTn_GMAC_OFFSET(gma->gma_port), GMAC_PORTn_GMAC_SIZE, 772 1.3.2.2 mjf &sc->sc_gmac_ioh); 773 1.3.2.2 mjf aprint_normal("\n"); 774 1.3.2.2 mjf aprint_naive("\n"); 775 1.3.2.2 mjf 776 1.3.2.2 mjf strlcpy(ifp->if_xname, device_xname(self), sizeof(ifp->if_xname)); 777 1.3.2.2 mjf ifp->if_flags = IFF_SIMPLEX|IFF_MULTICAST|IFF_BROADCAST; 778 1.3.2.2 mjf ifp->if_softc = sc; 779 1.3.2.2 mjf ifp->if_ioctl = gmc_ifioctl; 780 1.3.2.2 mjf ifp->if_stop = gmc_ifstop; 781 1.3.2.2 mjf ifp->if_start = gmc_ifstart; 782 1.3.2.2 mjf ifp->if_init = gmc_ifinit; 783 1.3.2.2 mjf 784 1.3.2.2 mjf IFQ_SET_READY(&ifp->if_snd); 785 1.3.2.2 mjf 786 1.3.2.2 mjf sc->sc_ec.ec_capabilities = ETHERCAP_VLAN_MTU | ETHERCAP_JUMBO_MTU; 787 1.3.2.2 mjf sc->sc_ec.ec_mii = &sc->sc_mii; 788 1.3.2.2 mjf 789 1.3.2.2 mjf sc->sc_mii.mii_ifp = ifp; 790 1.3.2.2 mjf sc->sc_mii.mii_statchg = gmc_mii_statchg; 791 1.3.2.2 mjf sc->sc_mii.mii_readreg = gma->gma_mii_readreg; 792 1.3.2.2 mjf sc->sc_mii.mii_writereg = gma->gma_mii_writereg; 793 1.3.2.2 mjf 794 1.3.2.2 mjf ifmedia_init(&sc->sc_mii.mii_media, 0, gmc_mediachange, 795 1.3.2.2 mjf gmc_mediastatus); 796 1.3.2.2 mjf 797 1.3.2.2 mjf if_attach(ifp); 798 1.3.2.2 mjf ether_ifattach(ifp, eaddrs[gma->gma_port]); 799 1.3.2.2 mjf mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, 800 1.3.2.2 mjf gma->gma_phy, MII_OFFSET_ANY, 0); 801 1.3.2.2 mjf 802 1.3.2.2 mjf if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 803 1.3.2.2 mjf ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 804 1.3.2.2 mjf ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 805 1.3.2.2 mjf } else { 806 1.3.2.2 mjf ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 807 1.3.2.2 mjf // ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_1000_T|IFM_FDX); 808 1.3.2.2 mjf } 809 1.3.2.2 mjf 810 1.3.2.2 mjf sc->sc_gmac_status = bus_space_read_4(sc->sc_iot, sc->sc_gmac_ioh, 811 1.3.2.2 mjf GMAC_STATUS); 812 1.3.2.2 mjf sc->sc_gmac_sta_add[0] = bus_space_read_4(sc->sc_iot, sc->sc_gmac_ioh, 813 1.3.2.2 mjf GMAC_STA_ADD0); 814 1.3.2.2 mjf sc->sc_gmac_sta_add[1] = bus_space_read_4(sc->sc_iot, sc->sc_gmac_ioh, 815 1.3.2.2 mjf GMAC_STA_ADD1); 816 1.3.2.2 mjf sc->sc_gmac_sta_add[2] = bus_space_read_4(sc->sc_iot, sc->sc_gmac_ioh, 817 1.3.2.2 mjf GMAC_STA_ADD2); 818 1.3.2.2 mjf sc->sc_gmac_mcast_filter[0] = bus_space_read_4(sc->sc_iot, 819 1.3.2.2 mjf sc->sc_gmac_ioh, GMAC_MCAST_FILTER0); 820 1.3.2.2 mjf sc->sc_gmac_mcast_filter[1] = bus_space_read_4(sc->sc_iot, 821 1.3.2.2 mjf sc->sc_gmac_ioh, GMAC_MCAST_FILTER1); 822 1.3.2.2 mjf sc->sc_gmac_rx_filter = bus_space_read_4(sc->sc_iot, sc->sc_gmac_ioh, 823 1.3.2.2 mjf GMAC_RX_FILTER); 824 1.3.2.2 mjf sc->sc_gmac_config[0] = bus_space_read_4(sc->sc_iot, sc->sc_gmac_ioh, 825 1.3.2.2 mjf GMAC_CONFIG0); 826 1.3.2.2 mjf sc->sc_dmavr = bus_space_read_4(sc->sc_iot, sc->sc_dma_ioh, GMAC_DMAVR); 827 1.3.2.2 mjf 828 1.3.2.2 mjf /* sc->sc_int_enabled is already zeroed */ 829 1.3.2.2 mjf sc->sc_int_mask[0] = (sc->sc_port1 ? INT0_GMAC1 : INT0_GMAC0); 830 1.3.2.2 mjf sc->sc_int_mask[1] = (sc->sc_port1 ? INT1_GMAC1 : INT1_GMAC0); 831 1.3.2.2 mjf sc->sc_int_mask[2] = (sc->sc_port1 ? INT2_GMAC1 : INT2_GMAC0); 832 1.3.2.2 mjf sc->sc_int_mask[3] = (sc->sc_port1 ? INT3_GMAC1 : INT3_GMAC0); 833 1.3.2.2 mjf sc->sc_int_mask[4] = (sc->sc_port1 ? INT4_GMAC1 : INT4_GMAC0); 834 1.3.2.2 mjf 835 1.3.2.2 mjf if (!sc->sc_port1) { 836 1.3.2.2 mjf sc->sc_ih = intr_establish(gma->gma_intr, IPL_NET, IST_LEVEL_HIGH, 837 1.3.2.2 mjf gmc_intr, sc); 838 1.3.2.2 mjf KASSERT(sc->sc_ih != NULL); 839 1.3.2.2 mjf } 840 1.3.2.2 mjf 841 1.3.2.2 mjf callout_init(&sc->sc_mii_ch, 0); 842 1.3.2.2 mjf callout_setfunc(&sc->sc_mii_ch, gmc_mii_tick, sc); 843 1.3.2.2 mjf 844 1.3.2.2 mjf aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 845 1.3.2.2 mjf ether_sprintf(CLLADDR(sc->sc_if.if_sadl))); 846 1.3.2.2 mjf } 847 1.3.2.2 mjf 848 1.3.2.2 mjf CFATTACH_DECL_NEW(gmc, sizeof(struct gmc_softc), 849 1.3.2.2 mjf gmc_match, gmc_attach, NULL, NULL); 850
Indexes created Tue Oct 21 16:10:11 GMT 2025