files.imx31 revision 1.4
1 # $NetBSD: files.imx31,v 1.4 2010/11/13 06:09:34 bsh Exp $ 2 # 3 # Configuration info for the Freescale i.MX31 4 # 5 6 define bus_dma_generic 7 8 file arch/arm/imx/imx_space.c 9 file arch/arm/imx/imx_dma.c bus_dma_generic 10 11 # iMX L2 Cache Controller 12 device l2cc 13 attach l2cc at mainbus 14 file arch/arm/imx/imx31_l2cc.c l2cc 15 16 # iMX AHB 17 device ahb { [addr=-1], [size=0], [intr=-1], [irqbase=-1]} : bus_space_generic 18 attach ahb at mainbus 19 file arch/arm/imx/imx31_ahb.c ahb 20 21 # iMX AdVanced Interrupt Controller 22 include "arch/arm/pic/files.pic" 23 device avic: pic 24 attach avic at ahb 25 file arch/arm/imx/imx31_icu.c avic needs-flag 26 file arch/arm/arm32/irq_dispatch.S 27 28 # iMX IP bus 29 device aips { [addr=-1], [size=0], [intr=-1]} : bus_space_generic 30 attach aips at ahb 31 file arch/arm/imx/imx31_aips.c aips 32 33 # iMX EMI (external memory interface) 34 device emi { [offset=-1], [size=0], [intr=-1] } : bus_space_generic 35 attach emi at ahb 36 file arch/arm/imx/imx31_emi.c emi 37 38 # iMX GPIO 39 device imxgpio: gpiobus 40 attach imxgpio at ahb 41 file arch/arm/imx/imx31_gpio.c imxgpio needs-flag 42 43 # iMX M3IF - Multi Master Memory Interface 44 # iMX ESDCTL/MDDRC - Enhanced SDRAM/LPDDR memory controller 45 # iMX PCMCIA - PCMCIA memory controller 46 # iMX NANDFC - NAND Flash memory controller 47 # iMX WEIM - Wireless External Interface Module 48 49 # iMX clock 50 file arch/arm/imx/imxclock.c 51 52 # iMX UART 53 device imxuart 54 attach imxuart at aips 55 file arch/arm/imx/imxuart.c imxuart 56 57 attach ehci at ahb with ehci_ahb : bus_dma_generic 58 file arch/arm/imx/echi_ahb.c ehci_ahb 59 60 attach ohci at ahb with ohci_ahb : bus_dma_generic 61 file arch/arm/imx/ochi_ahb.c ohci_ahb 62 63 attach wdc at ahb with wdc_ahb : bus_dma_generic 64 file arch/arm/imx/wdc_ahb.c wdc_ahb 65
Indexes created Tue Sep 23 14:10:03 GMT 2025