imx23_pinctrlreg.h revision 1.2
1 1.2 matt /* $Id: imx23_pinctrlreg.h,v 1.2 2013/10/07 17:36:40 matt Exp $ */ 2 1.1 jkunz 3 1.1 jkunz /* 4 1.1 jkunz * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 1.1 jkunz * All rights reserved. 6 1.1 jkunz * 7 1.1 jkunz * This code is derived from software contributed to The NetBSD Foundation 8 1.1 jkunz * by Petri Laakso. 9 1.1 jkunz * 10 1.1 jkunz * Redistribution and use in source and binary forms, with or without 11 1.1 jkunz * modification, are permitted provided that the following conditions 12 1.1 jkunz * are met: 13 1.1 jkunz * 1. Redistributions of source code must retain the above copyright 14 1.1 jkunz * notice, this list of conditions and the following disclaimer. 15 1.1 jkunz * 2. Redistributions in binary form must reproduce the above copyright 16 1.1 jkunz * notice, this list of conditions and the following disclaimer in the 17 1.1 jkunz * documentation and/or other materials provided with the distribution. 18 1.1 jkunz * 19 1.1 jkunz * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.1 jkunz * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.1 jkunz * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.1 jkunz * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.1 jkunz * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.1 jkunz * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.1 jkunz * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.1 jkunz * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.1 jkunz * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.1 jkunz * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.1 jkunz * POSSIBILITY OF SUCH DAMAGE. 30 1.1 jkunz */ 31 1.1 jkunz 32 1.1 jkunz #ifndef _ARM_IMX_IMX23_PINCTRLREG_H_ 33 1.1 jkunz #define _ARM_IMX_IMX23_PINCTRLREG_H_ 34 1.1 jkunz 35 1.1 jkunz #include <sys/cdefs.h> 36 1.1 jkunz 37 1.1 jkunz #define HW_PINCTRL_BASE 0x80018000 38 1.2 matt #define HW_PINCTRL_SIZE 0x2000 39 1.1 jkunz 40 1.1 jkunz /* 41 1.1 jkunz * PINCTRL Block Control Register. 42 1.1 jkunz */ 43 1.1 jkunz #define HW_PINCTRL_CTRL 0x000 44 1.1 jkunz #define HW_PINCTRL_CTRL_SET 0x004 45 1.1 jkunz #define HW_PINCTRL_CTRL_CLR 0x008 46 1.1 jkunz #define HW_PINCTRL_CTRL_TOG 0x00C 47 1.1 jkunz 48 1.1 jkunz #define HW_PINCTRL_CTRL_SFTRST __BIT(31) 49 1.1 jkunz #define HW_PINCTRL_CTRL_CLKGATE __BIT(30) 50 1.1 jkunz #define HW_PINCTRL_CTRL_RSRVD2 __BITS(29, 28) 51 1.1 jkunz #define HW_PINCTRL_CTRL_PRESENT3 __BIT(27) 52 1.1 jkunz #define HW_PINCTRL_CTRL_PRESENT2 __BIT(26) 53 1.1 jkunz #define HW_PINCTRL_CTRL_PRESENT1 __BIT(25) 54 1.1 jkunz #define HW_PINCTRL_CTRL_PRESENT0 __BIT(24) 55 1.1 jkunz #define HW_PINCTRL_CTRL_RSRVD1 __BIT(23, 3) 56 1.1 jkunz #define HW_PINCTRL_CTRL_IRQOUT2 __BITS(2) 57 1.1 jkunz #define HW_PINCTRL_CTRL_IRQOUT1 __BIT(1) 58 1.1 jkunz #define HW_PINCTRL_CTRL_IRQOUT0 __BIT(0) 59 1.1 jkunz 60 1.1 jkunz /* 61 1.1 jkunz * PINCTRL Pin Mux Select Register 0. 62 1.1 jkunz */ 63 1.1 jkunz #define HW_PINCTRL_MUXSEL0 0x100 64 1.1 jkunz #define HW_PINCTRL_MUXSEL0_SET 0x104 65 1.1 jkunz #define HW_PINCTRL_MUXSEL0_CLR 0x108 66 1.1 jkunz #define HW_PINCTRL_MUXSEL0_TOG 0x10C 67 1.1 jkunz 68 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN15 __BITS(31, 30) 69 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN14 __BITS(29, 28) 70 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN13 __BITS(27, 26) 71 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN12 __BITS(25, 24) 72 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN11 __BITS(23, 22) 73 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN10 __BITS(21, 20) 74 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN09 __BITS(19, 18) 75 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN08 __BITS(17, 16) 76 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN07 __BITS(15, 14) 77 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN06 __BITS(13, 12) 78 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN05 __BITS(11, 10) 79 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN04 __BITS(9, 8) 80 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN03 __BITS(7, 6) 81 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN02 __BITS(5, 4) 82 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN01 __BITS(3, 2) 83 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN00 __BITS(1, 0) 84 1.1 jkunz 85 1.1 jkunz /* Pin 59, GPMI_D15 pin function selection */ 86 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN15_GPMI_DATA15 0x00 87 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN15_AUART2_TX 0x01 88 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN15_GPMI_CE3N 0x02 89 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN15_GPIO 0x03 90 1.1 jkunz 91 1.1 jkunz /* Pin 58, GPMI_D14 pin function selection */ 92 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN14_GPMI_DATA14 0x00 93 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN14_AUART2_RX 0x01 94 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN14_RESERVED 0x02 95 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN14_GPIO 0x03 96 1.1 jkunz 97 1.1 jkunz /* Pin 57, GPMI_D13 pin function selection */ 98 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN13_GPMI_DATA13 0x00 99 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN13_LCD_D23 0x01 100 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN13_RESERVED 0x02 101 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN13_GPIO 0x03 102 1.1 jkunz 103 1.1 jkunz /* Pin 56, GPMI_D12 pin function selection */ 104 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN12_GPMI_DATA12 0x00 105 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN12_LCD_D22 0x01 106 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN12_RESERVED 0x02 107 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN12_GPIO 0x03 108 1.1 jkunz 109 1.1 jkunz /* Pin 55, GPMI_D11 pin function selection */ 110 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN11_GPMI_DATA11 0x00 111 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN11_LCD_D21 0x01 112 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN11_SSP1_D7 0x02 113 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN11_GPIO 0x03 114 1.1 jkunz 115 1.1 jkunz /* Pin 54, GPMI_D10 pin function selection */ 116 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN10_GPMI_DATA10 0x00 117 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN10_LCD_D20 0x01 118 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN10_SSP1_D6 0x02 119 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN10_GPIO 0x03 120 1.1 jkunz 121 1.1 jkunz /* Pin 53, GPMI_D09 pin function selection */ 122 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN09_GPMI_DATA09 0x00 123 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN09_LCD_D19 0x01 124 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN09_SSP1_D5 0x02 125 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN09_GPIO 0x03 126 1.1 jkunz 127 1.1 jkunz /* Pin 52, GPMI_D08 pin function selection */ 128 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN08_GPMI_DATA08 0x00 129 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN08_LCD_D18 0x01 130 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN08_SSP1_D4 0x02 131 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN08_GPIO 0x03 132 1.1 jkunz 133 1.1 jkunz /* Pin 50, GPMI_D07 pin function selection */ 134 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN07_GPMI_DATA07 0x00 135 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN07_LCD_D15 0x01 136 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN07_SSP2_D7 0x02 137 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN07_GPIO 0x03 138 1.1 jkunz 139 1.1 jkunz /* Pin 51, GPMI_D06 pin function selection */ 140 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN06_GPMI_DATA06 0x00 141 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN06_LCD_D14 0x01 142 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN06_SSP2_D6 0x02 143 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN06_GPIO 0x03 144 1.1 jkunz 145 1.1 jkunz /* Pin 48, GPMI_D05 pin function selection */ 146 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN05_GPMI_DATA05 0x00 147 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN05_LCD_D13 0x01 148 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN05_SSP2_D5 0x02 149 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN05_GPIO 0x03 150 1.1 jkunz 151 1.1 jkunz /* Pin 49, GPMI_D04 pin function selection */ 152 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN04_GPMI_DATA04 0x00 153 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN04_LCD_D12 0x01 154 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN04_SSP2_D4 0x02 155 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN04_GPIO 0x03 156 1.1 jkunz 157 1.1 jkunz /* Pin 47, GPMI_D03 pin function selection */ 158 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN03_GPMI_DATA03 0x00 159 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN03_LCD_D11 0x01 160 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN03_SSP2_D3 0x02 161 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN03_GPIO 0x03 162 1.1 jkunz 163 1.1 jkunz /* Pin 46, GPMI_D02 pin function selection */ 164 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN02_GPMI_DATA02 0x00 165 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN02_LCD_D10 0x01 166 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN02_SSP2_D2 0x02 167 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN02_GPIO 0x03 168 1.1 jkunz 169 1.1 jkunz /* Pin 45, GPMI_D01 pin function selection */ 170 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN01_GPMI_DATA01 0x00 171 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN01_LCD_D9 0x01 172 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN01_SSP2_D1 0x02 173 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN01_GPIO 0x03 174 1.1 jkunz 175 1.1 jkunz /* Pin 44, GPMI_D00 pin function selection */ 176 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN00_GPMI_DATA00 0x00 177 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN00_LCD_D8 0x01 178 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN00_SSP2_D0 0x02 179 1.1 jkunz #define HW_PINCTRL_MUXSEL0_BANK0_PIN00_GPIO 0x03 180 1.1 jkunz 181 1.1 jkunz /* 182 1.1 jkunz * PINCTRL Pin Mux Select Register 1. 183 1.1 jkunz */ 184 1.1 jkunz #define HW_PINCTRL_MUXSEL1 0x110 185 1.1 jkunz #define HW_PINCTRL_MUXSEL1_SET 0x114 186 1.1 jkunz #define HW_PINCTRL_MUXSEL1_CLR 0x118 187 1.1 jkunz #define HW_PINCTRL_MUXSEL1_TOG 0x11C 188 1.1 jkunz 189 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN31 __BITS(31, 30) 190 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN30 __BITS(29, 28) 191 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN29 __BITS(27, 26) 192 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN28 __BITS(25, 24) 193 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN27 __BITS(23, 22) 194 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN26 __BITS(21, 20) 195 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN25 __BITS(19, 18) 196 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN24 __BITS(17, 16) 197 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN23 __BITS(15, 14) 198 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN22 __BITS(13, 12) 199 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN21 __BITS(11, 10) 200 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN20 __BITS(9, 8) 201 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN19 __BITS(7, 6) 202 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN18 __BITS(5, 4) 203 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN17 __BITS(3, 2) 204 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN16 __BITS(1, 0) 205 1.1 jkunz 206 1.1 jkunz /* Pin 4, I2C_SDA pin function selection */ 207 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN31_I2C_SD 0x00 208 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN31_GPMI_CE2N 0x01 209 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN31_AUART1_RX 0x02 210 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN31_GPIO 0x03 211 1.1 jkunz 212 1.1 jkunz /* Pin 2, I2C_SCL pin function selection */ 213 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN30_I2C_CLK 0x00 214 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN30_GPMI_READY2 0x01 215 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN30_AUART1_TX 0x02 216 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN30_GPIO 0x03 217 1.1 jkunz 218 1.1 jkunz /* Pin 69, AUART1_TX pin function selection */ 219 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN29_AUART1_TX 0x00 220 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN29_RESERVED 0x01 221 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN29_SSP1_D7 0x02 222 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN29_GPIO 0x03 223 1.1 jkunz 224 1.1 jkunz /* Pin 68, AUART1_RX pin function selection */ 225 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN28_AUART1_RX 0x00 226 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN28_RESERVED 0x01 227 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN28_SSP1_D6 0x02 228 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN28_GPIO 0x03 229 1.1 jkunz 230 1.1 jkunz /* Pin 67, AUART1_RTS pin function selection */ 231 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN27_AUART1_RTS 0x00 232 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN27_RESERVED 0x01 233 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN27_SSP1_D5 0x02 234 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN27_GPIO 0x03 235 1.1 jkunz 236 1.1 jkunz /* Pin 66, AUART1_CTS pin function selection */ 237 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN26_AUART1_CTS 0x00 238 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN26_ESERVED 0x01 239 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN26_SSP1_D4 0x02 240 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN26_GPIO 0x03 241 1.1 jkunz 242 1.1 jkunz /* Pin 60, GPMI_RDN pin function selection */ 243 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN25_GPMI_RDN 0x00 244 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN25_RESERVED1 0x01 245 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN25_RESERVED2 0x02 246 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN25_GPIO 0x03 247 1.1 jkunz 248 1.1 jkunz /* Pin 65, GPMI_WRN pin function selection */ 249 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN24_GPMI_WRN 0x00 250 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN24_RESERVED 0x01 251 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN24_SSP2_SCK 0x02 252 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN24_GPIO 0x03 253 1.1 jkunz 254 1.1 jkunz /* Pin 64, GPMI_WPN pin function selection */ 255 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN23_GPMI_WPN 0x00 256 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN23_RESERVED1 0x01 257 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN23_RESERVED2 0x02 258 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN23_GPIO 0x03 259 1.1 jkunz 260 1.1 jkunz /* Pin 63, GPMI_RDY3 pin function selection */ 261 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN22_GPMI_READY3 0x00 262 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN22_RESERVED1 0x01 263 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN22_RESERVED2 0x02 264 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN22_GPIO 0x03 265 1.1 jkunz 266 1.1 jkunz /* Pin 62, GPMI_RDY2 pin function selection */ 267 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN21_GPMI_READY2 0x00 268 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN21_RESERVED1 0x01 269 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN21_RESERVED2 0x02 270 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN21_GPIO 0x03 271 1.1 jkunz 272 1.1 jkunz /* Pin 43, GPMI_RDY1 pin function selection */ 273 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN20_GPMI_READY1 0x00 274 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN20_RESERVED 0x01 275 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN20_SSP2_CMD 0x02 276 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN20_GPIO 0x03 277 1.1 jkunz 278 1.1 jkunz /* Pin 61, GPMI_RDY0 pin function selection */ 279 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN19_GPMI_READY0 0x00 280 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN19_RESERVED 0x01 281 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN19_SSP2_DETECT 0x02 282 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN19_GPIO 0x03 283 1.1 jkunz 284 1.1 jkunz /* Pin 42, GPMI_CE2N pin function selection */ 285 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN18_GPMI_CE2N 0x00 286 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN18_RESERVED1 0x01 287 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN18_RESERVED2 0x02 288 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN18_GPIO 0x03 289 1.1 jkunz 290 1.1 jkunz /* Pin 41, GPMI_ALE pin function selection */ 291 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN17_GPMI_ALE 0x00 292 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN17_LCD_D17 0x01 293 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN17_RESERVED 0x02 294 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN17_GPIO 0x03 295 1.1 jkunz 296 1.1 jkunz /* Pin 40, GPMI_CLE pin function selection */ 297 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN16_GPMI_CLE 0x00 298 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN16_LCD_D16 0x01 299 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN16_RESERVED 0x02 300 1.1 jkunz #define HW_PINCTRL_MUXSEL1_BANK0_PIN16_GPIO 0x03 301 1.1 jkunz 302 1.1 jkunz /* 303 1.1 jkunz * PINCTRL Pin Mux Select Register 2. 304 1.1 jkunz */ 305 1.1 jkunz #define HW_PINCTRL_MUXSEL2 0x120 306 1.1 jkunz #define HW_PINCTRL_MUXSEL2_SET 0x124 307 1.1 jkunz #define HW_PINCTRL_MUXSEL2_CLR 0x128 308 1.1 jkunz #define HW_PINCTRL_MUXSEL2_TOG 0x12C 309 1.1 jkunz 310 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN15 __BITS(31, 30) 311 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN14 __BITS(29, 28) 312 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN13 __BITS(27, 26) 313 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN12 __BITS(25, 24) 314 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN11 __BITS(23, 22) 315 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN10 __BITS(21, 20) 316 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN09 __BITS(19, 18) 317 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN08 __BITS(17, 16) 318 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN07 __BITS(15, 14) 319 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN06 __BITS(13, 12) 320 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN05 __BITS(11, 10) 321 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN04 __BITS(9, 8) 322 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN03 __BITS(7, 6) 323 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN02 __BITS(5, 4) 324 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN01 __BITS(3, 2) 325 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN00 __BITS(1, 0) 326 1.1 jkunz 327 1.1 jkunz /* Pin 15, LCD_D15 pin function selection */ 328 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN15_LCD_D15 0x00 329 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN15_ETM_DA7 0x01 330 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN15_SAIF1_SDATA1 0x02 331 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN15_GPIO 0x03 332 1.1 jkunz 333 1.1 jkunz /* Pin 17, LCD_D14 pin function selection */ 334 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN14_LCD_D14 0x00 335 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN14_ETM_DA6 0x01 336 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN14_SAIF1_SDATA2 0x02 337 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN14_GPIO 0x03 338 1.1 jkunz 339 1.1 jkunz /* Pin 19, LCD_D13 pin function selection */ 340 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN13_LCD_D13 0x00 341 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN13_ETM_DA5 0x01 342 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN13_SAIF2_SDATA2 0x02 343 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN13_GPIO 0x03 344 1.1 jkunz 345 1.1 jkunz /* Pin 22, LCD_D12 pin function selection */ 346 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN12_LCD_D12 0x00 347 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN12_ETM_DA4 0x01 348 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN12_SAIF2_SDATA1 0x02 349 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN12_GPIO 0x03 350 1.1 jkunz 351 1.1 jkunz /* Pin 24, LCD_D11 pin function selection */ 352 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN11_LCD_D11 0x00 353 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN11_ETM_DA3 0x01 354 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN11_SAIF_LRCLK 0x02 355 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN11_GPIO 0x03 356 1.1 jkunz 357 1.1 jkunz /* Pin 26, LCD_D10 pin function selection */ 358 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN10_LCD_D10 0x00 359 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN10_ETM_DA2 0x01 360 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN10_SAIF_BITCLK 0x02 361 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN10_GPIO 0x03 362 1.1 jkunz 363 1.1 jkunz /* Pin 28, LCD_D09 pin function selection */ 364 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN09_LCD_D9 0x00 365 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN09_ETM_DA1 0x01 366 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN09_SAIF1_SDATA0 0x02 367 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN09_GPIO 0x03 368 1.1 jkunz 369 1.1 jkunz /* Pin 27, LCD_D08 pin function selection */ 370 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN08_LCD_D8 0x00 371 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN08_ETM_DA0 0x01 372 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN08_SAIF2_SDATA0 0x02 373 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN08_GPIO 0x03 374 1.1 jkunz 375 1.1 jkunz /* Pin 25, LCD_D07 pin function selection */ 376 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN07_LCD_D7 0x00 377 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN07_ETM_DA15 0x01 378 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN07_RESERVED 0x02 379 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN07_GPIO 0x03 380 1.1 jkunz 381 1.1 jkunz /* Pin 23, LCD_D06 pin function selection */ 382 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN06_LCD_D6 0x00 383 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN06_ETM_DA14 0x01 384 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN06_RESERVED 0x02 385 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN06_GPIO 0x03 386 1.1 jkunz 387 1.1 jkunz /* Pin 21, LCD_D05 pin function selection */ 388 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN05_LCD_D5 0x00 389 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN05_ETM_DA13 0x01 390 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN05_RESERVED 0x02 391 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN05_GPIO 0x03 392 1.1 jkunz 393 1.1 jkunz /* Pin 18, LCD_D04 pin function selection */ 394 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN04_LCD_D4 0x00 395 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN04_ETM_DA12 0x01 396 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN04_RESERVED 0x02 397 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN04_GPIO 0x03 398 1.1 jkunz 399 1.1 jkunz /* Pin 16, LCD_D03 pin function selection */ 400 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN03_LCD_D3 0x00 401 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN03_ETM_DA11 0x01 402 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN03_RESERVED 0x02 403 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN03_GPIO 0x03 404 1.1 jkunz 405 1.1 jkunz /* Pin 14, LCD_D02 pin function selection */ 406 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN02_LCD_D2 0x00 407 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN02_ETM_DA10 0x01 408 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN02_RESERVED 0x02 409 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN02_GPIO 0x03 410 1.1 jkunz 411 1.1 jkunz /* Pin 12, LCD_D01 pin function selection */ 412 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN01_LCD_D1 0x00 413 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN01_ETM_DA9 0x01 414 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN01_RESERVED 0x02 415 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN01_GPIO 0x03 416 1.1 jkunz 417 1.1 jkunz /* Pin 10, LCD_D00 pin function selection */ 418 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN00_LCD_D0 0x00 419 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN00_ETM_DA8 0x01 420 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN00_RESERVED 0x02 421 1.1 jkunz #define HW_PINCTRL_MUXSEL2_BANK1_PIN00_GPIO 0x03 422 1.1 jkunz 423 1.1 jkunz /* 424 1.1 jkunz * PINCTRL Pin Mux Select Register 3. 425 1.1 jkunz */ 426 1.1 jkunz #define HW_PINCTRL_MUXSEL3 0x130 427 1.1 jkunz #define HW_PINCTRL_MUXSEL3_SET 0x134 428 1.1 jkunz #define HW_PINCTRL_MUXSEL3_CLR 0x138 429 1.1 jkunz #define HW_PINCTRL_MUXSEL3_TOG 0x13C 430 1.1 jkunz 431 1.1 jkunz #define HW_PINCTRL_MUXSEL3_RSRVD0 __BITS(31, 30) 432 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN30 __BITS(29, 28) 433 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN29 __BITS(27, 26) 434 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN28 __BITS(25, 24) 435 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN27 __BITS(23, 22) 436 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN26 __BITS(21, 20) 437 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN25 __BITS(19, 18) 438 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN24 __BITS(17, 16) 439 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN23 __BITS(15, 14) 440 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN22 __BITS(13, 12) 441 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN21 __BITS(11, 10) 442 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN20 __BITS(9, 8) 443 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN19 __BITS(7, 6) 444 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN18 __BITS(5, 4) 445 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN17 __BITS(3, 2) 446 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN16 __BITS(1, 0) 447 1.1 jkunz 448 1.1 jkunz /* Always write zeroes to this field */ 449 1.1 jkunz #define HW_PINCTRL_MUXSEL3_RSRVD0_ZERO 0x00 450 1.1 jkunz 451 1.1 jkunz /* Pin 131, PWM4 pin function selection */ 452 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN30_PWM4 0x00 453 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN30_ETM_TCLK 0x01 454 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN30_AUART1_RTS 0x02 455 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN30_GPIO 0x03 456 1.1 jkunz 457 1.1 jkunz /* Pin 130, PWM3 pin function selection */ 458 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN29_PWM3 0x00 459 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN29_ETM_TCTL 0x01 460 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN29_AUART1_CTS 0x02 461 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN29_GPIO 0x03 462 1.1 jkunz 463 1.1 jkunz /* Pin 129, PWM2 pin function selection */ 464 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN28_PWM2 0x00 465 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN28_GPMI_READY3 0x01 466 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN28_RESERVED 0x02 467 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN28_GPIO 0x03 468 1.1 jkunz 469 1.1 jkunz /* Pin 3, PWM1 pin function selection */ 470 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN27_PWM1 0x00 471 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN27_TIMROT2 0x01 472 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN27_DUART_TX 0x02 473 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN27_GPIO 0x03 474 1.1 jkunz 475 1.1 jkunz /* Pin 1, PWM0 pin function selection */ 476 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN26_PWM0 0x00 477 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN26_TIMROT1 0x01 478 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN26_DUART_RX 0x02 479 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN26_GPIO 0x03 480 1.1 jkunz 481 1.1 jkunz /* Pin 35, LCD_VSYNC pin function selection */ 482 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN25_LCD_VSYNC 0x00 483 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN25_LCD_BUSY 0x01 484 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN25_RESERVED 0x02 485 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN25_GPIO 0x03 486 1.1 jkunz 487 1.1 jkunz /* Pin 34, LCD_HSYNC pin function selection */ 488 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN24_LCD_HSYNC 0x00 489 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN24_I2C_SD 0x01 490 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN24_RESERVED 0x02 491 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN24_GPIO 0x03 492 1.1 jkunz 493 1.1 jkunz /* Pin 30, LCD_ENABLE pin function selection */ 494 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN23_LCD_ENABLE 0x00 495 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN23_I2C_CLK 0x01 496 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN23_RESERVED 0x02 497 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN23_GPIO 0x03 498 1.1 jkunz 499 1.1 jkunz /* Pin 36, LCD_DOTCK pin function selection */ 500 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN22_LCD_DOTCK 0x00 501 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN22_GPMI_READY3 0x01 502 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN22_RESERVED 0x02 503 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN22_GPIO 0x03 504 1.1 jkunz 505 1.1 jkunz /* Pin 29, LCD_CS pin function selection */ 506 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN21_LCD_CS 0x00 507 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN21_RESERVED1 0x01 508 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN21_RESERVED2 0x02 509 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN21_GPIO 0x03 510 1.1 jkunz 511 1.1 jkunz /* Pin 32, LCD_WR pin function selection */ 512 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN20_LCD_WR 0x00 513 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN20_RESERVED1 0x01 514 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN20_RESERVED2 0x02 515 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN20_GPIO 0x03 516 1.1 jkunz 517 1.1 jkunz /* Pin 33, LCD_RS pin function selection */ 518 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN19_LCD_RS 0x00 519 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN19_ETM_TCLK 0x01 520 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN19_RESERVED 0x02 521 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN19_GPIO 0x03 522 1.1 jkunz 523 1.1 jkunz /* Pin 31, LCD_RESET pin function selection */ 524 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN18_LCD_RESET 0x00 525 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN18_ETM_TCTL 0x01 526 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN18_GPMI_CE3N 0x02 527 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN18_GPIO 0x03 528 1.1 jkunz 529 1.1 jkunz /* Pin 11, LCD_D17 pin function selection */ 530 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN17_LCD_D17 0x00 531 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN17_RESERVED1 0x01 532 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN17_RESERVED2 0x02 533 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN17_GPIO 0x03 534 1.1 jkunz 535 1.1 jkunz /* Pin 13, LCD_D16 pin function selection */ 536 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN16_LCD_D16 0x00 537 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN16_RESERVED 0x01 538 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN16_SAIF_ALT_BITCLK 0x02 539 1.1 jkunz #define HW_PINCTRL_MUXSEL3_BANK1_PIN16_GPIO 0x03 540 1.1 jkunz 541 1.1 jkunz /* 542 1.1 jkunz * PINCTRL Pin Mux Select Register 4. 543 1.1 jkunz */ 544 1.1 jkunz #define HW_PINCTRL_MUXSEL4 0x140 545 1.1 jkunz #define HW_PINCTRL_MUXSEL4_SET 0x144 546 1.1 jkunz #define HW_PINCTRL_MUXSEL4_CLR 0x148 547 1.1 jkunz #define HW_PINCTRL_MUXSEL4_TOG 0x14C 548 1.1 jkunz 549 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN15 __BITS(31,30) 550 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN14 __BITS(29,28) 551 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN13 __BITS(27,26) 552 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN12 __BITS(25,24) 553 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN11 __BITS(23,22) 554 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN10 __BITS(21,20) 555 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN09 __BITS(19,18) 556 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN08 __BITS(17,16) 557 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN07 __BITS(15,14) 558 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN06 __BITS(13,12) 559 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN05 __BITS(11,10) 560 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN04 __BITS(9,8) 561 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN03 __BITS(7,6) 562 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN02 __BITS(5,4) 563 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN01 __BITS(3,2) 564 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN00 __BITS(1,0) 565 1.1 jkunz 566 1.1 jkunz /* Pin 108, EMI_A06 pin function selection */ 567 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN15_EMI_ADDR06 0x00 568 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN15_RESERVED1 0x01 569 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN15_RESERVED2 0x02 570 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN15_GPIO 0x03 571 1.1 jkunz 572 1.1 jkunz /* Pin 107, EMI_A05 pin function selection */ 573 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN14_EMI_ADDR05 0x00 574 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN14_RESERVED1 0x01 575 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN14_RESERVED2 0x02 576 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN14_GPIO 0x03 577 1.1 jkunz 578 1.1 jkunz /* Pin 109, EMI_A04 pin function selection */ 579 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN13_EMI_ADDR04 0x00 580 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN13_RESERVED1 0x01 581 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN13_RESERVED2 0x02 582 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN13_GPIO 0x03 583 1.1 jkunz 584 1.1 jkunz /* Pin 110, EMI_A03 pin function selection */ 585 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN12_EMI_ADDR03 0x00 586 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN12_RESERVED1 0x01 587 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN12_RESERVED2 0x02 588 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN12_GPIO 0x03 589 1.1 jkunz 590 1.1 jkunz /* Pin 111, EMI_A02 pin function selection */ 591 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN11_EMI_ADDR02 0x00 592 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN11_RESERVED1 0x01 593 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN11_RESERVED2 0x02 594 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN11_GPIO 0x03 595 1.1 jkunz 596 1.1 jkunz /* Pin 112, EMI_A01 pin function selection */ 597 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN10_EMI_ADDR01 0x00 598 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN10_RESERVED1 0x01 599 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN10_RESERVED2 0x02 600 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN10_GPIO 0x03 601 1.1 jkunz 602 1.1 jkunz /* Pin 113, EMI_A00 pin function selection */ 603 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN09_EMI_ADDR00 0x00 604 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN09_RESERVED1 0x01 605 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN09_RESERVED2 0x02 606 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN09_GPIO 0x03 607 1.1 jkunz 608 1.1 jkunz /* Pin 38, ROTARYB pin function selection */ 609 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN08_TIMROT2 0x00 610 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN08_AUART2_CTS 0x01 611 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN08_GPMI_CE3N 0x02 612 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN08_GPIO 0x03 613 1.1 jkunz 614 1.1 jkunz /* Pin 37, ROTARYA pin function selection */ 615 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN07_TIMROT1 0x00 616 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN07_AUART2_RTS 0x01 617 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN07_SPDIF 0x02 618 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN07_GPIO 0x03 619 1.1 jkunz 620 1.1 jkunz /* Pin 127, SSP1_SCK pin function selection */ 621 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN06_SSP1_SCK 0x00 622 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN06_RESERVED 0x01 623 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN06_ALT_JTAG_TRST_N 0x02 624 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN06_GPIO 0x03 625 1.1 jkunz 626 1.1 jkunz /* Pin 125, SSP1_DATA3 pin function selection */ 627 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN05_SSP1_D3 0x00 628 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN05_RESERVED 0x01 629 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN05_ALT_JTAG_TMS 0x02 630 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN05_GPIO 0x03 631 1.1 jkunz 632 1.1 jkunz /* Pin 124, SSP1_DATA2 pin function selection */ 633 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN04_SSP1_D2 0x00 634 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN04_I2C_SD 0x01 635 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN04_ALT_JTAG_RTCK 0x02 636 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN04_GPIO 0x03 637 1.1 jkunz 638 1.1 jkunz /* Pin 123, SSP1_DATA1 pin function selection */ 639 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN03_SSP1_D1 0x00 640 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN03_I2C_CLK 0x01 641 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN03_ALT_JTAG_TCK 0x02 642 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN03_GPIO 0x03 643 1.1 jkunz 644 1.1 jkunz /* Pin 122, SSP1_DATA0 pin function selection */ 645 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN02_SSP1_D0 0x00 646 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN02_RESERVED 0x01 647 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN02_ALT_JTAG_TDI 0x02 648 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN02_GPIO 0x03 649 1.1 jkunz 650 1.1 jkunz /* Pin 126, SSP1_DETECT pin function selection */ 651 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN01_SSP1_DETECT 0x00 652 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN01_GPMI_CE3N 0x01 653 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN01_USB_ID 0x02 654 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN01_GPIO 0x03 655 1.1 jkunz 656 1.1 jkunz /* Pin 121, SSP1_CMD pin function selection */ 657 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN00_SSP1_CMD 0x00 658 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN00_RESERVED 0x01 659 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN00_ALT_JTAG_TDO 0x02 660 1.1 jkunz #define HW_PINCTRL_MUXSEL4_BANK2_PIN00_GPIO 0x03 661 1.1 jkunz 662 1.1 jkunz /* 663 1.1 jkunz * PINCTRL Pin Mux Select Register 5. 664 1.1 jkunz */ 665 1.1 jkunz #define HW_PINCTRL_MUXSEL5 0x150 666 1.1 jkunz #define HW_PINCTRL_MUXSEL5_SET 0x154 667 1.1 jkunz #define HW_PINCTRL_MUXSEL5_CLR 0x158 668 1.1 jkunz #define HW_PINCTRL_MUXSEL5_TOG 0x15C 669 1.1 jkunz 670 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN31 __BITS(31,30) 671 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN30 __BITS(29,28) 672 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN29 __BITS(27,26) 673 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN28 __BITS(25,24) 674 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN27 __BITS(23,22) 675 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN26 __BITS(21,20) 676 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN25 __BITS(19,18) 677 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN24 __BITS(17,16) 678 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN23 __BITS(15,14) 679 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN22 __BITS(13,12) 680 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN21 __BITS(11,10) 681 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN20 __BITS(9,8) 682 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN19 __BITS(7,6) 683 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN18 __BITS(5,4) 684 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN17 __BITS(3,2) 685 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN16 __BITS(1,0) 686 1.1 jkunz 687 1.1 jkunz /* Pin 114, EMI_WEN pin function selection */ 688 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN31_EMI_WEN 0x00 689 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN31_RESERVED1 0x01 690 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN31_RESERVED2 0x02 691 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN31_GPIO 0x03 692 1.1 jkunz 693 1.1 jkunz /* Pin 98, EMI_RASN pin function selection */ 694 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN30_EMI_RASN 0x00 695 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN30_RESERVED1 0x01 696 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN30_RESERVED2 0x02 697 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN30_GPIO 0x03 698 1.1 jkunz 699 1.1 jkunz /* Pin 115, EMI_CKE pin function selection */ 700 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN29_EMI_CKE 0x00 701 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN29_RESERVED1 0x01 702 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN29_RESERVED2 0x02 703 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN29_GPIO 0x03 704 1.1 jkunz 705 1.1 jkunz /* Pin 120, GPMI_CE0N pin function selection */ 706 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN28_GPMI_CE0N 0x00 707 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN28_RESERVED1 0x01 708 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN28_RESERVED2 0x02 709 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN28_GPIO 0x03 710 1.1 jkunz 711 1.1 jkunz /* Pin 118, GPMI_CE1N pin function selection */ 712 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN27_GPMI_CE1N 0x00 713 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN27_RESERVED1 0x01 714 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN27_RESERVED2 0x02 715 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN27_GPIO 0x03 716 1.1 jkunz 717 1.1 jkunz /* Pin 99, EMI_CE1N pin function selection */ 718 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN26_EMI_CE1N 0x00 719 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN26_RESERVED1 0x01 720 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN26_RESERVED2 0x02 721 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN26_GPIO 0x03 722 1.1 jkunz 723 1.1 jkunz /* Pin 100, EMI_CE0N pin function selection */ 724 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN25_EMI_CE0N 0x00 725 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN25_RESERVED1 0x01 726 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN25_RESERVED2 0x02 727 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN25_GPIO 0x03 728 1.1 jkunz 729 1.1 jkunz /* Pin 97, EMI_CASN pin function selection */ 730 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN24_EMI_CASN 0x00 731 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN24_RESERVED1 0x01 732 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN24_RESERVED2 0x02 733 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN24_GPIO 0x03 734 1.1 jkunz 735 1.1 jkunz /* Pin 117, EMI_BA1 pin function selection */ 736 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN23_EMI_BA1 0x00 737 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN23_RESERVED1 0x01 738 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN23_RESERVED2 0x02 739 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN23_GPIO 0x03 740 1.1 jkunz 741 1.1 jkunz /* Pin 116, EMI_BA0 pin function selection */ 742 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN22_EMI_BA0 0x00 743 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN22_RESERVED1 0x01 744 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN22_RESERVED2 0x02 745 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN22_GPIO 0x03 746 1.1 jkunz 747 1.1 jkunz /* Pin 101, EMI_A12 pin function selection */ 748 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN21_EMI_ADDR12 0x00 749 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN21_RESERVED1 0x01 750 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN21_RESERVED2 0x02 751 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN21_GPIO 0x03 752 1.1 jkunz 753 1.1 jkunz /* Pin 102, EMI_A11 pin function selection */ 754 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN20_EMI_ADDR11 0x00 755 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN20_RESERVED1 0x01 756 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN20_RESERVED2 0x02 757 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN20_GPIO 0x03 758 1.1 jkunz 759 1.1 jkunz /* Pin 104, EMI_A10 pin function selection */ 760 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN19_EMI_ADDR10 0x00 761 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN19_RESERVED1 0x01 762 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN19_RESERVED2 0x02 763 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN19_GPIO 0x03 764 1.1 jkunz 765 1.1 jkunz /* Pin 103, EMI_A09 pin function selection */ 766 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN18_EMI_ADDR09 0x00 767 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN18_RESERVED1 0x01 768 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN18_RESERVED2 0x02 769 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN18_GPIO 0x03 770 1.1 jkunz 771 1.1 jkunz /* Pin 106, EMI_A08 pin function selection */ 772 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN17_EMI_ADDR08 0x00 773 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN17_RESERVED1 0x01 774 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN17_RESERVED2 0x02 775 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN17_GPIO 0x03 776 1.1 jkunz 777 1.1 jkunz /* Pin 105, EMI_A07 pin function selection */ 778 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN16_EMI_ADDR07 0x00 779 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN16_RESERVED1 0x01 780 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN16_RESERVED2 0x02 781 1.1 jkunz #define HW_PINCTRL_MUXSEL5_BANK2_PIN16_GPIO 0x03 782 1.1 jkunz 783 1.1 jkunz /* 784 1.1 jkunz * PINCTRL Pin Mux Select Register 6. 785 1.1 jkunz */ 786 1.1 jkunz #define HW_PINCTRL_MUXSEL6 0x160 787 1.1 jkunz #define HW_PINCTRL_MUXSEL6_SET 0x164 788 1.1 jkunz #define HW_PINCTRL_MUXSEL6_CLR 0x168 789 1.1 jkunz #define HW_PINCTRL_MUXSEL6_TOG 0x16C 790 1.1 jkunz 791 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN15 __BITS(31,30) 792 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN14 __BITS(29,28) 793 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN13 __BITS(27,26) 794 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN12 __BITS(25,24) 795 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN11 __BITS(23,22) 796 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN10 __BITS(21,20) 797 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN09 __BITS(19,18) 798 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN08 __BITS(17,16) 799 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN07 __BITS(15,14) 800 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN06 __BITS(13,12) 801 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN05 __BITS(11,10) 802 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN04 __BITS(9,8) 803 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN03 __BITS(7,6) 804 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN02 __BITS(5,4) 805 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN01 __BITS(3,2) 806 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN00 __BITS(1,0) 807 1.1 jkunz 808 1.1 jkunz /* Pin 95, EMI_D15 pin function selection */ 809 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN15_EMI_DATA15 0x00 810 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN15_RESERVED1 0x01 811 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN15_RESERVED2 0x02 812 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN15_DISABLED 0x03 813 1.1 jkunz 814 1.1 jkunz /* Pin 96, EMI_D14 pin function selection */ 815 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN14_EMI_DATA14 0x00 816 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN14_RESERVED1 0x01 817 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN14_RESERVED2 0x02 818 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN14_DISABLED 0x03 819 1.1 jkunz 820 1.1 jkunz /* Pin 94, EMI_D13 pin function selection */ 821 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN13_EMI_DATA13 0x00 822 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN13_RESERVED1 0x01 823 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN13_RESERVED2 0x02 824 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN13_DISABLED 0x03 825 1.1 jkunz 826 1.1 jkunz /* Pin 93, EMI_D12 pin function selection */ 827 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN12_EMI_DATA12 0x00 828 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN12_RESERVED1 0x01 829 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN12_RESERVED2 0x02 830 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN12_DISABLED 0x03 831 1.1 jkunz 832 1.1 jkunz /* Pin 91, EMI_D11 pin function selection */ 833 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN11_EMI_DATA11 0x00 834 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN11_RESERVED1 0x01 835 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN11_RESERVED2 0x02 836 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN11_DISABLED 0x03 837 1.1 jkunz 838 1.1 jkunz /* Pin 89, EMI_D10 pin function selection */ 839 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN10_EMI_DATA10 0x00 840 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN10_RESERVED1 0x01 841 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN10_RESERVED2 0x02 842 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN10_DISABLED 0x03 843 1.1 jkunz 844 1.1 jkunz /* Pin 87, EMI_D09 pin function selection */ 845 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN09_EMI_DATA09 0x00 846 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN09_RESERVED1 0x01 847 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN09_RESERVED2 0x02 848 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN09_DISABLED 0x03 849 1.1 jkunz 850 1.1 jkunz /* Pin 86, EMI_D08 pin function selection */ 851 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN08_EMI_DATA08 0x00 852 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN08_RESERVED1 0x01 853 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN08_RESERVED2 0x02 854 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN08_DISABLED 0x03 855 1.1 jkunz 856 1.1 jkunz /* Pin 85, EMI_D07 pin function selection */ 857 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN07_EMI_DATA07 0x00 858 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN07_RESERVED1 0x01 859 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN07_RESERVED2 0x02 860 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN07_DISABLED 0x03 861 1.1 jkunz 862 1.1 jkunz /* Pin 84, EMI_D06 pin function selection */ 863 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN06_EMI_DATA06 0x00 864 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN06_RESERVED1 0x01 865 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN06_RESERVED2 0x02 866 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN06_DISABLED 0x03 867 1.1 jkunz 868 1.1 jkunz /* Pin 83, EMI_D05 pin function selection */ 869 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN05_EMI_DATA05 0x00 870 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN05_RESERVED1 0x01 871 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN05_RESERVED2 0x02 872 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN05_DISABLED 0x03 873 1.1 jkunz 874 1.1 jkunz /* Pin 82, EMI_D04 pin function selection */ 875 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN04_EMI_DATA04 0x00 876 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN04_RESERVED1 0x01 877 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN04_RESERVED2 0x02 878 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN04_DISABLED 0x03 879 1.1 jkunz 880 1.1 jkunz /* Pin 79, EMI_D03 pin function selection */ 881 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN03_EMI_DATA03 0x00 882 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN03_RESERVED1 0x01 883 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN03_RESERVED2 0x02 884 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN03_DISABLED 0x03 885 1.1 jkunz 886 1.1 jkunz /* Pin 77, EMI_D02 pin function selection */ 887 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN02_EMI_DATA02 0x00 888 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN02_RESERVED1 0x01 889 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN02_RESERVED2 0x02 890 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN02_DISABLED 0x03 891 1.1 jkunz 892 1.1 jkunz /* Pin 76, EMI_D01 pin function selection */ 893 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN01_EMI_DATA01 0x00 894 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN01_RESERVED1 0x01 895 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN01_RESERVED2 0x02 896 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN01_DISABLED 0x03 897 1.1 jkunz 898 1.1 jkunz /* Pin 75, EMI_D00 pin function selection */ 899 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN00_EMI_DATA00 0x00 900 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN00_RESERVED1 0x01 901 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN00_RESERVED2 0x02 902 1.1 jkunz #define HW_PINCTRL_MUXSEL6_BANK3_PIN00_DISABLED 0x03 903 1.1 jkunz 904 1.1 jkunz /* 905 1.1 jkunz * PINCTRL Pin Mux Select Register 7. 906 1.1 jkunz */ 907 1.1 jkunz #define HW_PINCTRL_MUXSEL7 0x170 908 1.1 jkunz #define HW_PINCTRL_MUXSEL7_SET 0x174 909 1.1 jkunz #define HW_PINCTRL_MUXSEL7_CLR 0x178 910 1.1 jkunz #define HW_PINCTRL_MUXSEL7_TOG 0x17C 911 1.1 jkunz 912 1.1 jkunz #define HW_PINCTRL_MUXSEL7_RSRVD0 __BITS(31,12) 913 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN21 __BITS(11,10) 914 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN20 __BITS(9,8) 915 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN19 __BITS(7,6) 916 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN18 __BITS(5,4) 917 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN17 __BITS(3,2) 918 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN16 __BITS(1,0) 919 1.1 jkunz 920 1.1 jkunz /* Always write zeroes to this field */ 921 1.1 jkunz #define HW_PINCTRL_MUXSEL7_RSRVD0_ZERO 0x00 922 1.1 jkunz 923 1.1 jkunz /* Pin 72, EMI_CLKN pin function selection */ 924 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN21_EMI_CLKN 0x00 925 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN21_RESERVED1 0x01 926 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN21_RESERVED2 0x02 927 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN21_DISABLED 0x03 928 1.1 jkunz 929 1.1 jkunz /* Pin 70, EMI_CLK pin function selection */ 930 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN20_EMI_CLK 0x00 931 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN20_RESERVED1 0x01 932 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN20_RESERVED2 0x02 933 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN20_DISABLED 0x03 934 1.1 jkunz 935 1.1 jkunz /* Pin 74, EMI_DQS1 pin function selection */ 936 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN19_EMI_DQS1 0x00 937 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN19_RESERVED1 0x01 938 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN19_RESERVED2 0x02 939 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN19_DISABLED 0x03 940 1.1 jkunz 941 1.1 jkunz /* Pin 73, EMI_DQS0 pin function selection */ 942 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN18_EMI_DQS0 0x00 943 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN18_RESERVED1 0x01 944 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN18_RESERVED2 0x02 945 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN18_DISABLED 0x03 946 1.1 jkunz 947 1.1 jkunz /* Pin 92, EMI_DQM1 pin function selection */ 948 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN17_EMI_DQM1 0x00 949 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN17_RESERVED1 0x01 950 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN17_RESERVED2 0x02 951 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN17_DISABLED 0x03 952 1.1 jkunz 953 1.1 jkunz /* Pin 81, EMI_DQM0 pin function selection */ 954 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN16_EMI_DQM0 0x00 955 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN16_RESERVED1 0x01 956 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN16_RESERVED2 0x02 957 1.1 jkunz #define HW_PINCTRL_MUXSEL7_BANK3_PIN16_DISABLED 0x03 958 1.1 jkunz 959 1.1 jkunz /* 960 1.2 matt * PINCTRL Drive Strength and Voltage Register 0. 961 1.2 matt */ 962 1.2 matt #define HW_PINCTRL_DRIVE0 0x200 963 1.2 matt #define HW_PINCTRL_DRIVE0_SET 0x204 964 1.2 matt #define HW_PINCTRL_DRIVE0_CLR 0x208 965 1.2 matt #define HW_PINCTRL_DRIVE0_TOG 0x20C 966 1.2 matt 967 1.2 matt /* 968 1.2 matt * PINCTRL Drive Strength and Voltage Register 2. 969 1.2 matt */ 970 1.2 matt #define HW_PINCTRL_DRIVE2 0x220 971 1.2 matt #define HW_PINCTRL_DRIVE2_SET 0x224 972 1.2 matt #define HW_PINCTRL_DRIVE2_CLR 0x228 973 1.2 matt #define HW_PINCTRL_DRIVE2_TOG 0x22C 974 1.2 matt 975 1.2 matt #define HW_PINCTRL_DRIVE2_RSRVD7 __BITS(31, 30) 976 1.2 matt #define HW_PINCTRL_DRIVE2_BANK0_PIN23_MA __BITS(29, 28) 977 1.2 matt #define HW_PINCTRL_DRIVE2_RSRVD6 __BITS(27, 26) 978 1.2 matt #define HW_PINCTRL_DRIVE2_BANK0_PIN22_MA __BITS(25, 24) 979 1.2 matt #define HW_PINCTRL_DRIVE2_RSRVD5 __BITS(23, 22) 980 1.2 matt #define HW_PINCTRL_DRIVE2_BANK0_PIN21_MA __BITS(21, 20) 981 1.2 matt #define HW_PINCTRL_DRIVE2_RSRVD4 __BITS(19, 18) 982 1.2 matt #define HW_PINCTRL_DRIVE2_BANK0_PIN20_MA __BITS(17, 16) 983 1.2 matt #define HW_PINCTRL_DRIVE2_RSRVD3 __BITS(15, 14) 984 1.2 matt #define HW_PINCTRL_DRIVE2_BANK0_PIN19_MA __BITS(13, 12) 985 1.2 matt #define HW_PINCTRL_DRIVE2_RSRVD2 __BITS(11, 10) 986 1.2 matt #define HW_PINCTRL_DRIVE2_BANK0_PIN18_MA __BITS(9, 8) 987 1.2 matt #define HW_PINCTRL_DRIVE2_RSRVD1 __BITS(7, 6) 988 1.2 matt #define HW_PINCTRL_DRIVE2_BANK0_PIN17_MA __BITS(5, 4) 989 1.2 matt #define HW_PINCTRL_DRIVE2_RSRVD0 __BITS(3, 2) 990 1.2 matt #define HW_PINCTRL_DRIVE2_BANK0_PIN16_MA __BITS(1, 0) 991 1.2 matt 992 1.2 matt /* 993 1.1 jkunz * PINCTRL Drive Strength and Voltage Register 8. 994 1.1 jkunz */ 995 1.1 jkunz #define HW_PINCTRL_DRIVE8 0x280 996 1.1 jkunz #define HW_PINCTRL_DRIVE8_SET 0x284 997 1.1 jkunz #define HW_PINCTRL_DRIVE8_CLR 0x288 998 1.1 jkunz #define HW_PINCTRL_DRIVE8_TOG 0x28C 999 1.1 jkunz 1000 1.1 jkunz #define HW_PINCTRL_DRIVE8_RSRVD7 __BITS(31, 30) 1001 1.1 jkunz #define HW_PINCTRL_DRIVE8_BANK2_PIN07_MA __BITS(29, 28) 1002 1.1 jkunz #define HW_PINCTRL_DRIVE8_RSRVD6 __BITS(27, 26) 1003 1.1 jkunz #define HW_PINCTRL_DRIVE8_BANK2_PIN06_MA __BITS(25, 24) 1004 1.1 jkunz #define HW_PINCTRL_DRIVE8_RSRVD5 __BITS(23, 22) 1005 1.1 jkunz #define HW_PINCTRL_DRIVE8_BANK2_PIN05_MA __BITS(21, 20) 1006 1.1 jkunz #define HW_PINCTRL_DRIVE8_RSRVD4 __BITS(19, 18) 1007 1.1 jkunz #define HW_PINCTRL_DRIVE8_BANK2_PIN04_MA __BITS(17, 16) 1008 1.1 jkunz #define HW_PINCTRL_DRIVE8_RSRVD3 __BITS(15, 14) 1009 1.1 jkunz #define HW_PINCTRL_DRIVE8_BANK2_PIN03_MA __BITS(13, 12) 1010 1.1 jkunz #define HW_PINCTRL_DRIVE8_RSRVD2 __BITS(11, 10) 1011 1.1 jkunz #define HW_PINCTRL_DRIVE8_BANK2_PIN02_MA __BITS(9, 8) 1012 1.1 jkunz #define HW_PINCTRL_DRIVE8_RSRVD1 __BITS(7, 6) 1013 1.1 jkunz #define HW_PINCTRL_DRIVE8_BANK2_PIN01_MA __BITS(5, 4) 1014 1.1 jkunz #define HW_PINCTRL_DRIVE8_RSRVD0 __BITS(3, 2) 1015 1.1 jkunz #define HW_PINCTRL_DRIVE8_BANK2_PIN00_MA __BITS(1, 0) 1016 1.1 jkunz 1017 1.1 jkunz /* 1018 1.1 jkunz * PINCTRL Drive Strength and Voltage Register 9. 1019 1.1 jkunz */ 1020 1.1 jkunz #define HW_PINCTRL_DRIVE9 0x290 1021 1.1 jkunz #define HW_PINCTRL_DRIVE9_SET 0x294 1022 1.1 jkunz #define HW_PINCTRL_DRIVE9_CLR 0x298 1023 1.1 jkunz #define HW_PINCTRL_DRIVE9_TOG 0x29C 1024 1.1 jkunz 1025 1.1 jkunz #define HW_PINCTRL_DRIVE9_RSRVD7 __BIT(31) 1026 1.1 jkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN15_V __BIT(30) 1027 1.1 jkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN15_MA __BITS(29, 28) 1028 1.1 jkunz #define HW_PINCTRL_DRIVE9_RSRVD6 __BIT(27) 1029 1.1 jkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN14_V __BIT(26) 1030 1.1 jkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN14_MA __BITS(25, 24) 1031 1.1 jkunz #define HW_PINCTRL_DRIVE9_RSRVD5 __BIT(23) 1032 1.1 jkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN13_V __BIT(22) 1033 1.1 jkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN13_MA __BITS(21, 20) 1034 1.1 jkunz #define HW_PINCTRL_DRIVE9_RSRVD4 __BIT(19) 1035 1.1 jkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN12_V __BIT(18) 1036 1.1 jkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN12_MA __BITS(17, 16) 1037 1.1 jkunz #define HW_PINCTRL_DRIVE9_RSRVD3 __BIT(15) 1038 1.1 jkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN11_V __BIT(14) 1039 1.1 jkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN11_MA __BITS(13, 12) 1040 1.1 jkunz #define HW_PINCTRL_DRIVE9_RSRVD2 __BIT(11) 1041 1.1 jkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN10_V __BIT(10) 1042 1.1 jkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN10_MA __BITS(9, 8) 1043 1.1 jkunz #define HW_PINCTRL_DRIVE9_RSRVD1 __BIT(7) 1044 1.1 jkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN09_V __BIT(6) 1045 1.1 jkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN09_MA __BITS(5, 4) 1046 1.1 jkunz #define HW_PINCTRL_DRIVE9_RSRVD0 __BITS(3, 2) 1047 1.1 jkunz #define HW_PINCTRL_DRIVE9_BANK2_PIN08_MA __BITS(1, 0) 1048 1.1 jkunz 1049 1.1 jkunz /* 1050 1.1 jkunz * PINCTRL Drive Strength and Voltage Register 10. 1051 1.1 jkunz */ 1052 1.1 jkunz #define HW_PINCTRL_DRIVE10 0x2a0 1053 1.1 jkunz #define HW_PINCTRL_DRIVE10_SET 0x2a4 1054 1.1 jkunz #define HW_PINCTRL_DRIVE10_CLR 0x2a8 1055 1.1 jkunz #define HW_PINCTRL_DRIVE10_TOG 0x2ac 1056 1.1 jkunz 1057 1.1 jkunz #define HW_PINCTRL_DRIVE10_RSRVD7 __BIT(31) 1058 1.1 jkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN23_V __BIT(30) 1059 1.1 jkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN23_MA __BITS(29, 28) 1060 1.1 jkunz #define HW_PINCTRL_DRIVE10_RSRVD6 __BIT(27) 1061 1.1 jkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN22_V __BIT(26) 1062 1.1 jkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN22_MA __BITS(25, 24) 1063 1.1 jkunz #define HW_PINCTRL_DRIVE10_RSRVD5 __BIT(23) 1064 1.1 jkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN21_V __BIT(22) 1065 1.1 jkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN21_MA __BITS(21, 20) 1066 1.1 jkunz #define HW_PINCTRL_DRIVE10_RSRVD4 __BIT(19) 1067 1.1 jkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN20_V __BIT(18) 1068 1.1 jkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN20_MA __BITS(17, 16) 1069 1.1 jkunz #define HW_PINCTRL_DRIVE10_RSRVD3 __BIT(15) 1070 1.1 jkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN19_V __BIT(14) 1071 1.1 jkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN19_MA __BITS(13, 12) 1072 1.1 jkunz #define HW_PINCTRL_DRIVE10_RSRVD2 __BIT(11) 1073 1.1 jkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN18_V __BIT(10) 1074 1.1 jkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN18_MA __BITS(9, 8) 1075 1.1 jkunz #define HW_PINCTRL_DRIVE10_RSRVD1 __BIT(7) 1076 1.1 jkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN17_V __BIT(6) 1077 1.1 jkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN17_MA __BITS(5, 4) 1078 1.1 jkunz #define HW_PINCTRL_DRIVE10_RSRVD0 __BIT(3) 1079 1.1 jkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN16_V __BIT(2) 1080 1.1 jkunz #define HW_PINCTRL_DRIVE10_BANK2_PIN16_MA __BITS(1, 0) 1081 1.1 jkunz 1082 1.1 jkunz /* 1083 1.1 jkunz * PINCTRL Drive Strength and Voltage Register 11. 1084 1.1 jkunz */ 1085 1.1 jkunz #define HW_PINCTRL_DRIVE11 0x2b0 1086 1.1 jkunz #define HW_PINCTRL_DRIVE11_SET 0x2b4 1087 1.1 jkunz #define HW_PINCTRL_DRIVE11_CLR 0x2b8 1088 1.1 jkunz #define HW_PINCTRL_DRIVE11_TOG 0x2bC 1089 1.1 jkunz 1090 1.1 jkunz #define HW_PINCTRL_DRIVE11_RSRVD7 __BIT(31) 1091 1.1 jkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN31_V __BIT(30) 1092 1.1 jkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN31_MA __BITS(29, 28) 1093 1.1 jkunz #define HW_PINCTRL_DRIVE11_RSRVD6 __BIT(27) 1094 1.1 jkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN30_V __BIT(26) 1095 1.1 jkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN30_MA __BITS(25, 24) 1096 1.1 jkunz #define HW_PINCTRL_DRIVE11_RSRVD5 __BIT(23) 1097 1.1 jkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN29_V __BIT(22) 1098 1.1 jkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN29_MA __BITS(21, 20) 1099 1.1 jkunz #define HW_PINCTRL_DRIVE11_RSRVD4 __BITS(19, 18) 1100 1.1 jkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN28_MA __BIT(17, 16) 1101 1.1 jkunz #define HW_PINCTRL_DRIVE11_RSRVD3 __BITS(15, 14) 1102 1.1 jkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN27_MA __BITS(13, 12) 1103 1.1 jkunz #define HW_PINCTRL_DRIVE11_RSRVD2 __BIT(11) 1104 1.1 jkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN26_V __BIT(10) 1105 1.1 jkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN26_MA __BITS(9, 8) 1106 1.1 jkunz #define HW_PINCTRL_DRIVE11_RSRVD1 __BIT(7) 1107 1.1 jkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN25_V __BIT(6) 1108 1.1 jkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN25_MA __BITS(5, 4) 1109 1.1 jkunz #define HW_PINCTRL_DRIVE11_RSRVD0 __BIT(3) 1110 1.1 jkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN24_V __BIT(2) 1111 1.1 jkunz #define HW_PINCTRL_DRIVE11_BANK2_PIN24_MA __BITS(1, 0) 1112 1.1 jkunz 1113 1.1 jkunz /* 1114 1.1 jkunz * PINCTRL Drive Strength and Voltage Register 12. 1115 1.1 jkunz */ 1116 1.1 jkunz #define HW_PINCTRL_DRIVE12 0x2c0 1117 1.1 jkunz #define HW_PINCTRL_DRIVE12_SET 0x2c4 1118 1.1 jkunz #define HW_PINCTRL_DRIVE12_CLR 0x2c8 1119 1.1 jkunz #define HW_PINCTRL_DRIVE12_TOG 0x2cC 1120 1.1 jkunz 1121 1.1 jkunz #define HW_PINCTRL_DRIVE12_RSRVD7 __BIT(31) 1122 1.1 jkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN07_V __BIT(30) 1123 1.1 jkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN07_MA __BITS(29, 28) 1124 1.1 jkunz #define HW_PINCTRL_DRIVE12_RSRVD6 __BIT(27) 1125 1.1 jkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN06_V __BIT(26) 1126 1.1 jkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN06_MA __BITS(25, 24) 1127 1.1 jkunz #define HW_PINCTRL_DRIVE12_RSRVD5 __BIT(23) 1128 1.1 jkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN05_V __BIT(22) 1129 1.1 jkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN05_MA __BITS(21, 20) 1130 1.1 jkunz #define HW_PINCTRL_DRIVE12_RSRVD4 __BIT(19) 1131 1.1 jkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN04_V __BIT(18) 1132 1.1 jkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN04_MA __BITS(17, 15) 1133 1.1 jkunz #define HW_PINCTRL_DRIVE12_RSRVD3 __BIT(15) 1134 1.1 jkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN03_V __BIT(14) 1135 1.1 jkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN03_MA __BITS(13, 12) 1136 1.1 jkunz #define HW_PINCTRL_DRIVE12_RSRVD2 __BIT(11) 1137 1.1 jkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN02_V __BIT(10) 1138 1.1 jkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN02_MA __BITS(9, 8) 1139 1.1 jkunz #define HW_PINCTRL_DRIVE12_RSRVD1 __BIT(7) 1140 1.1 jkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN01_V __BIT(6) 1141 1.1 jkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN01_MA __BITS(5, 4) 1142 1.1 jkunz #define HW_PINCTRL_DRIVE12_RSRVD0 __BIT(3) 1143 1.1 jkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN00_V __BIT(2) 1144 1.1 jkunz #define HW_PINCTRL_DRIVE12_BANK3_PIN00_MA __BITS(1, 0) 1145 1.1 jkunz 1146 1.1 jkunz /* 1147 1.1 jkunz * PINCTRL Drive Strength and Voltage Register 13. 1148 1.1 jkunz */ 1149 1.1 jkunz #define HW_PINCTRL_DRIVE13 0x2d0 1150 1.1 jkunz #define HW_PINCTRL_DRIVE13_SET 0x2d4 1151 1.1 jkunz #define HW_PINCTRL_DRIVE13_CLR 0x2d8 1152 1.1 jkunz #define HW_PINCTRL_DRIVE13_TOG 0x2dc 1153 1.1 jkunz 1154 1.1 jkunz #define HW_PINCTRL_DRIVE13_RSRVD7 __BIT(31) 1155 1.1 jkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN15_V __BIT(30) 1156 1.1 jkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN15_MA __BITS(29, 28) 1157 1.1 jkunz #define HW_PINCTRL_DRIVE13_RSRVD6 __BIT(27) 1158 1.1 jkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN14_V __BIT(26) 1159 1.1 jkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN14_MA __BITS(25, 24) 1160 1.1 jkunz #define HW_PINCTRL_DRIVE13_RSRVD5 __BIT(23) 1161 1.1 jkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN13_V __BIT(22) 1162 1.1 jkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN13_MA __BITS(21, 20) 1163 1.1 jkunz #define HW_PINCTRL_DRIVE13_RSRVD4 __BIT(19) 1164 1.1 jkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN12_V __BIT(18) 1165 1.1 jkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN12_MA __BITS(17, 16) 1166 1.1 jkunz #define HW_PINCTRL_DRIVE13_RSRVD3 __BIT(15) 1167 1.1 jkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN11_V __BIT(14) 1168 1.1 jkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN11_MA __BITS(13, 12) 1169 1.1 jkunz #define HW_PINCTRL_DRIVE13_RSRVD2 __BIT(11) 1170 1.1 jkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN10_V __BIT(10) 1171 1.1 jkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN10_MA __BITS(9, 8) 1172 1.1 jkunz #define HW_PINCTRL_DRIVE13_RSRVD1 __BIT(7) 1173 1.1 jkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN09_V __BIT(6) 1174 1.1 jkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN09_MA __BITS(5, 4) 1175 1.1 jkunz #define HW_PINCTRL_DRIVE13_RSRVD0 __BIT(3) 1176 1.1 jkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN08_V __BIT(2) 1177 1.1 jkunz #define HW_PINCTRL_DRIVE13_BANK3_PIN08_MA __BITS(1, 0) 1178 1.1 jkunz 1179 1.1 jkunz /* 1180 1.1 jkunz * PINCTRL Drive Strength and Voltage Register 14. 1181 1.1 jkunz */ 1182 1.1 jkunz #define HW_PINCTRL_DRIVE14 0x2e0 1183 1.1 jkunz #define HW_PINCTRL_DRIVE14_SET 0x2e4 1184 1.1 jkunz #define HW_PINCTRL_DRIVE14_CLR 0x2e8 1185 1.1 jkunz #define HW_PINCTRL_DRIVE14_TOG 0x2ec 1186 1.1 jkunz 1187 1.1 jkunz #define HW_PINCTRL_DRIVE14_RSRVD6 __BITS(31, 24) 1188 1.1 jkunz #define HW_PINCTRL_DRIVE14_RSRVD5 __BIT(23) 1189 1.1 jkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN21_V __BIT(22) 1190 1.1 jkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN21_MA __BITS(21, 20) 1191 1.1 jkunz #define HW_PINCTRL_DRIVE14_RSRVD4 __BIT(19) 1192 1.1 jkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN20_V __BIT(18) 1193 1.1 jkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN20_MA __BITS(17, 16) 1194 1.1 jkunz #define HW_PINCTRL_DRIVE14_RSRVD3 __BIT(15) 1195 1.1 jkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN19_V __BIT(14) 1196 1.1 jkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN19_MA __BITS(13, 12) 1197 1.1 jkunz #define HW_PINCTRL_DRIVE14_RSRVD2 __BIT(11) 1198 1.1 jkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN18_V __BIT(10) 1199 1.1 jkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN18_MA __BITS(9, 8) 1200 1.1 jkunz #define HW_PINCTRL_DRIVE14_RSRVD1 __BIT(7) 1201 1.1 jkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN17_V __BIT(6) 1202 1.1 jkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN17_MA __BITS(5, 4) 1203 1.1 jkunz #define HW_PINCTRL_DRIVE14_RSRVD0 __BIT(3) 1204 1.1 jkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN16_V __BIT(2) 1205 1.1 jkunz #define HW_PINCTRL_DRIVE14_BANK3_PIN16_MA __BITS(1, 0) 1206 1.1 jkunz 1207 1.1 jkunz /* 1208 1.2 matt * PINCTRL Bank 0 Pull Up Resistor Enable Register. 1209 1.2 matt */ 1210 1.2 matt #define HW_PINCTRL_PULL0 0x400 1211 1.2 matt #define HW_PINCTRL_PULL0_SET 0x404 1212 1.2 matt #define HW_PINCTRL_PULL0_CLR 0x408 1213 1.2 matt #define HW_PINCTRL_PULL0_TOG 0x40C 1214 1.2 matt 1215 1.2 matt /* 1216 1.1 jkunz * PINCTRL Bank 2 Pull Up Resistor Enable Register. 1217 1.1 jkunz */ 1218 1.1 jkunz #define HW_PINCTRL_PULL2 0x420 1219 1.1 jkunz #define HW_PINCTRL_PULL2_SET 0x424 1220 1.1 jkunz #define HW_PINCTRL_PULL2_CLR 0x428 1221 1.1 jkunz #define HW_PINCTRL_PULL2_TOG 0x42C 1222 1.1 jkunz 1223 1.1 jkunz #define HW_PINCTRL_PULL2_RSRVD2 __BITS(31, 29) 1224 1.1 jkunz #define HW_PINCTRL_PULL2_BANK2_PIN28 __BIT(28) 1225 1.1 jkunz #define HW_PINCTRL_PULL2_BANK2_PIN27 __BIT(27) 1226 1.1 jkunz #define HW_PINCTRL_PULL2_RSRVD1 __BITS(26, 9) 1227 1.1 jkunz #define HW_PINCTRL_PULL2_BANK2_PIN08 __BIT(8) 1228 1.1 jkunz #define HW_PINCTRL_PULL2_RSRVD0 __BITS(7, 6) 1229 1.1 jkunz #define HW_PINCTRL_PULL2_BANK2_PIN05 __BIT(5) 1230 1.1 jkunz #define HW_PINCTRL_PULL2_BANK2_PIN04 __BIT(4) 1231 1.1 jkunz #define HW_PINCTRL_PULL2_BANK2_PIN03 __BIT(3) 1232 1.1 jkunz #define HW_PINCTRL_PULL2_BANK2_PIN02 __BIT(2) 1233 1.1 jkunz #define HW_PINCTRL_PULL2_BANK2_PIN01 __BIT(1) 1234 1.1 jkunz #define HW_PINCTRL_PULL2_BANK2_PIN00 __BIT(0) 1235 1.1 jkunz 1236 1.1 jkunz /* 1237 1.1 jkunz * PINCTRL Bank 3 Pad Keeper Disable Register. 1238 1.1 jkunz */ 1239 1.1 jkunz #define HW_PINCTRL_PULL3 0x430 1240 1.1 jkunz #define HW_PINCTRL_PULL3_SET 0x434 1241 1.1 jkunz #define HW_PINCTRL_PULL3_CLR 0x438 1242 1.1 jkunz #define HW_PINCTRL_PULL3_TOG 0x43C 1243 1.1 jkunz 1244 1.1 jkunz #define HW_PINCTRL_PULL3_RSRVD0 __BITS(31, 18) 1245 1.1 jkunz #define HW_PINCTRL_PULL3_BANK3_PIN17 __BIT(17) 1246 1.1 jkunz #define HW_PINCTRL_PULL3_BANK3_PIN16 __BIT(16) 1247 1.1 jkunz #define HW_PINCTRL_PULL3_BANK3_PIN15 __BIT(15) 1248 1.1 jkunz #define HW_PINCTRL_PULL3_BANK3_PIN14 __BIT(14) 1249 1.1 jkunz #define HW_PINCTRL_PULL3_BANK3_PIN13 __BIT(13) 1250 1.1 jkunz #define HW_PINCTRL_PULL3_BANK3_PIN12 __BIT(12) 1251 1.1 jkunz #define HW_PINCTRL_PULL3_BANK3_PIN11 __BIT(11) 1252 1.1 jkunz #define HW_PINCTRL_PULL3_BANK3_PIN10 __BIT(10) 1253 1.1 jkunz #define HW_PINCTRL_PULL3_BANK3_PIN09 __BIT(9) 1254 1.1 jkunz #define HW_PINCTRL_PULL3_BANK3_PIN08 __BIT(8) 1255 1.1 jkunz #define HW_PINCTRL_PULL3_BANK3_PIN07 __BIT(7) 1256 1.1 jkunz #define HW_PINCTRL_PULL3_BANK3_PIN06 __BIT(6) 1257 1.1 jkunz #define HW_PINCTRL_PULL3_BANK3_PIN05 __BIT(5) 1258 1.1 jkunz #define HW_PINCTRL_PULL3_BANK3_PIN04 __BIT(4) 1259 1.1 jkunz #define HW_PINCTRL_PULL3_BANK3_PIN03 __BIT(3) 1260 1.1 jkunz #define HW_PINCTRL_PULL3_BANK3_PIN02 __BIT(2) 1261 1.1 jkunz #define HW_PINCTRL_PULL3_BANK3_PIN01 __BIT(1) 1262 1.1 jkunz #define HW_PINCTRL_PULL3_BANK3_PIN00 __BIT(0) 1263 1.1 jkunz 1264 1.2 matt /* 1265 1.2 matt * PINCTRL Bank 0 Data Output Register. 1266 1.2 matt */ 1267 1.2 matt #define HW_PINCTRL_DOUT0 0x500 1268 1.2 matt #define HW_PINCTRL_DOUT0_SET 0x504 1269 1.2 matt #define HW_PINCTRL_DOUT0_CLR 0x508 1270 1.2 matt #define HW_PINCTRL_DOUT0_TOG 0x50C 1271 1.2 matt 1272 1.2 matt #define HW_PINCTRL_DOUT0_DOUT __BITS(31, 0) 1273 1.2 matt 1274 1.2 matt /* 1275 1.2 matt * PINCTRL Bank 1 Data Output Register. 1276 1.2 matt */ 1277 1.2 matt #define HW_PINCTRL_DOUT1 0x510 1278 1.2 matt #define HW_PINCTRL_DOUT1_SET 0x514 1279 1.2 matt #define HW_PINCTRL_DOUT1_CLR 0x518 1280 1.2 matt #define HW_PINCTRL_DOUT1_TOG 0x51C 1281 1.2 matt 1282 1.2 matt #define HW_PINCTRL_DOUT1_DOUT __BITS(31, 0) 1283 1.2 matt 1284 1.2 matt /* 1285 1.2 matt * PINCTRL Bank 0 Data Input Register. 1286 1.2 matt */ 1287 1.2 matt #define HW_PINCTRL_DIN0 0x600 1288 1.2 matt #define HW_PINCTRL_DIN0_SET 0x604 1289 1.2 matt #define HW_PINCTRL_DIN0_CLR 0x608 1290 1.2 matt #define HW_PINCTRL_DIN0_TOG 0x60C 1291 1.2 matt 1292 1.2 matt /* 1293 1.2 matt * PINCTRL Bank 0 Data Output Enable Register. 1294 1.2 matt */ 1295 1.2 matt #define HW_PINCTRL_DOE0 0x700 1296 1.2 matt #define HW_PINCTRL_DOE0_SET 0x704 1297 1.2 matt #define HW_PINCTRL_DOE0_CLR 0x708 1298 1.2 matt #define HW_PINCTRL_DOE0_TOG 0x70C 1299 1.2 matt 1300 1.2 matt #define HW_PINCTRL_DOE0_DOE __BITS(31, 0) 1301 1.2 matt 1302 1.1 jkunz #endif /* !_ARM_IMX_IMX23_PINCTRLREG_H_ */ 1303
Indexes created Fri Sep 26 08:10:20 GMT 2025