imx23_pinctrlreg.h revision 1.1.2.2
1 /* $Id: imx23_pinctrlreg.h,v 1.1.2.2 2013/01/16 05:32:47 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _ARM_IMX_IMX23_PINCTRLREG_H_ 33 #define _ARM_IMX_IMX23_PINCTRLREG_H_ 34 35 #include <sys/cdefs.h> 36 37 #define HW_PINCTRL_BASE 0x80018000 38 39 /* 40 * PINCTRL Block Control Register. 41 */ 42 #define HW_PINCTRL_CTRL 0x000 43 #define HW_PINCTRL_CTRL_SET 0x004 44 #define HW_PINCTRL_CTRL_CLR 0x008 45 #define HW_PINCTRL_CTRL_TOG 0x00C 46 47 #define HW_PINCTRL_CTRL_SFTRST __BIT(31) 48 #define HW_PINCTRL_CTRL_CLKGATE __BIT(30) 49 #define HW_PINCTRL_CTRL_RSRVD2 __BITS(29, 28) 50 #define HW_PINCTRL_CTRL_PRESENT3 __BIT(27) 51 #define HW_PINCTRL_CTRL_PRESENT2 __BIT(26) 52 #define HW_PINCTRL_CTRL_PRESENT1 __BIT(25) 53 #define HW_PINCTRL_CTRL_PRESENT0 __BIT(24) 54 #define HW_PINCTRL_CTRL_RSRVD1 __BIT(23, 3) 55 #define HW_PINCTRL_CTRL_IRQOUT2 __BITS(2) 56 #define HW_PINCTRL_CTRL_IRQOUT1 __BIT(1) 57 #define HW_PINCTRL_CTRL_IRQOUT0 __BIT(0) 58 59 /* 60 * PINCTRL Pin Mux Select Register 0. 61 */ 62 #define HW_PINCTRL_MUXSEL0 0x100 63 #define HW_PINCTRL_MUXSEL0_SET 0x104 64 #define HW_PINCTRL_MUXSEL0_CLR 0x108 65 #define HW_PINCTRL_MUXSEL0_TOG 0x10C 66 67 #define HW_PINCTRL_MUXSEL0_BANK0_PIN15 __BITS(31, 30) 68 #define HW_PINCTRL_MUXSEL0_BANK0_PIN14 __BITS(29, 28) 69 #define HW_PINCTRL_MUXSEL0_BANK0_PIN13 __BITS(27, 26) 70 #define HW_PINCTRL_MUXSEL0_BANK0_PIN12 __BITS(25, 24) 71 #define HW_PINCTRL_MUXSEL0_BANK0_PIN11 __BITS(23, 22) 72 #define HW_PINCTRL_MUXSEL0_BANK0_PIN10 __BITS(21, 20) 73 #define HW_PINCTRL_MUXSEL0_BANK0_PIN09 __BITS(19, 18) 74 #define HW_PINCTRL_MUXSEL0_BANK0_PIN08 __BITS(17, 16) 75 #define HW_PINCTRL_MUXSEL0_BANK0_PIN07 __BITS(15, 14) 76 #define HW_PINCTRL_MUXSEL0_BANK0_PIN06 __BITS(13, 12) 77 #define HW_PINCTRL_MUXSEL0_BANK0_PIN05 __BITS(11, 10) 78 #define HW_PINCTRL_MUXSEL0_BANK0_PIN04 __BITS(9, 8) 79 #define HW_PINCTRL_MUXSEL0_BANK0_PIN03 __BITS(7, 6) 80 #define HW_PINCTRL_MUXSEL0_BANK0_PIN02 __BITS(5, 4) 81 #define HW_PINCTRL_MUXSEL0_BANK0_PIN01 __BITS(3, 2) 82 #define HW_PINCTRL_MUXSEL0_BANK0_PIN00 __BITS(1, 0) 83 84 /* Pin 59, GPMI_D15 pin function selection */ 85 #define HW_PINCTRL_MUXSEL0_BANK0_PIN15_GPMI_DATA15 0x00 86 #define HW_PINCTRL_MUXSEL0_BANK0_PIN15_AUART2_TX 0x01 87 #define HW_PINCTRL_MUXSEL0_BANK0_PIN15_GPMI_CE3N 0x02 88 #define HW_PINCTRL_MUXSEL0_BANK0_PIN15_GPIO 0x03 89 90 /* Pin 58, GPMI_D14 pin function selection */ 91 #define HW_PINCTRL_MUXSEL0_BANK0_PIN14_GPMI_DATA14 0x00 92 #define HW_PINCTRL_MUXSEL0_BANK0_PIN14_AUART2_RX 0x01 93 #define HW_PINCTRL_MUXSEL0_BANK0_PIN14_RESERVED 0x02 94 #define HW_PINCTRL_MUXSEL0_BANK0_PIN14_GPIO 0x03 95 96 /* Pin 57, GPMI_D13 pin function selection */ 97 #define HW_PINCTRL_MUXSEL0_BANK0_PIN13_GPMI_DATA13 0x00 98 #define HW_PINCTRL_MUXSEL0_BANK0_PIN13_LCD_D23 0x01 99 #define HW_PINCTRL_MUXSEL0_BANK0_PIN13_RESERVED 0x02 100 #define HW_PINCTRL_MUXSEL0_BANK0_PIN13_GPIO 0x03 101 102 /* Pin 56, GPMI_D12 pin function selection */ 103 #define HW_PINCTRL_MUXSEL0_BANK0_PIN12_GPMI_DATA12 0x00 104 #define HW_PINCTRL_MUXSEL0_BANK0_PIN12_LCD_D22 0x01 105 #define HW_PINCTRL_MUXSEL0_BANK0_PIN12_RESERVED 0x02 106 #define HW_PINCTRL_MUXSEL0_BANK0_PIN12_GPIO 0x03 107 108 /* Pin 55, GPMI_D11 pin function selection */ 109 #define HW_PINCTRL_MUXSEL0_BANK0_PIN11_GPMI_DATA11 0x00 110 #define HW_PINCTRL_MUXSEL0_BANK0_PIN11_LCD_D21 0x01 111 #define HW_PINCTRL_MUXSEL0_BANK0_PIN11_SSP1_D7 0x02 112 #define HW_PINCTRL_MUXSEL0_BANK0_PIN11_GPIO 0x03 113 114 /* Pin 54, GPMI_D10 pin function selection */ 115 #define HW_PINCTRL_MUXSEL0_BANK0_PIN10_GPMI_DATA10 0x00 116 #define HW_PINCTRL_MUXSEL0_BANK0_PIN10_LCD_D20 0x01 117 #define HW_PINCTRL_MUXSEL0_BANK0_PIN10_SSP1_D6 0x02 118 #define HW_PINCTRL_MUXSEL0_BANK0_PIN10_GPIO 0x03 119 120 /* Pin 53, GPMI_D09 pin function selection */ 121 #define HW_PINCTRL_MUXSEL0_BANK0_PIN09_GPMI_DATA09 0x00 122 #define HW_PINCTRL_MUXSEL0_BANK0_PIN09_LCD_D19 0x01 123 #define HW_PINCTRL_MUXSEL0_BANK0_PIN09_SSP1_D5 0x02 124 #define HW_PINCTRL_MUXSEL0_BANK0_PIN09_GPIO 0x03 125 126 /* Pin 52, GPMI_D08 pin function selection */ 127 #define HW_PINCTRL_MUXSEL0_BANK0_PIN08_GPMI_DATA08 0x00 128 #define HW_PINCTRL_MUXSEL0_BANK0_PIN08_LCD_D18 0x01 129 #define HW_PINCTRL_MUXSEL0_BANK0_PIN08_SSP1_D4 0x02 130 #define HW_PINCTRL_MUXSEL0_BANK0_PIN08_GPIO 0x03 131 132 /* Pin 50, GPMI_D07 pin function selection */ 133 #define HW_PINCTRL_MUXSEL0_BANK0_PIN07_GPMI_DATA07 0x00 134 #define HW_PINCTRL_MUXSEL0_BANK0_PIN07_LCD_D15 0x01 135 #define HW_PINCTRL_MUXSEL0_BANK0_PIN07_SSP2_D7 0x02 136 #define HW_PINCTRL_MUXSEL0_BANK0_PIN07_GPIO 0x03 137 138 /* Pin 51, GPMI_D06 pin function selection */ 139 #define HW_PINCTRL_MUXSEL0_BANK0_PIN06_GPMI_DATA06 0x00 140 #define HW_PINCTRL_MUXSEL0_BANK0_PIN06_LCD_D14 0x01 141 #define HW_PINCTRL_MUXSEL0_BANK0_PIN06_SSP2_D6 0x02 142 #define HW_PINCTRL_MUXSEL0_BANK0_PIN06_GPIO 0x03 143 144 /* Pin 48, GPMI_D05 pin function selection */ 145 #define HW_PINCTRL_MUXSEL0_BANK0_PIN05_GPMI_DATA05 0x00 146 #define HW_PINCTRL_MUXSEL0_BANK0_PIN05_LCD_D13 0x01 147 #define HW_PINCTRL_MUXSEL0_BANK0_PIN05_SSP2_D5 0x02 148 #define HW_PINCTRL_MUXSEL0_BANK0_PIN05_GPIO 0x03 149 150 /* Pin 49, GPMI_D04 pin function selection */ 151 #define HW_PINCTRL_MUXSEL0_BANK0_PIN04_GPMI_DATA04 0x00 152 #define HW_PINCTRL_MUXSEL0_BANK0_PIN04_LCD_D12 0x01 153 #define HW_PINCTRL_MUXSEL0_BANK0_PIN04_SSP2_D4 0x02 154 #define HW_PINCTRL_MUXSEL0_BANK0_PIN04_GPIO 0x03 155 156 /* Pin 47, GPMI_D03 pin function selection */ 157 #define HW_PINCTRL_MUXSEL0_BANK0_PIN03_GPMI_DATA03 0x00 158 #define HW_PINCTRL_MUXSEL0_BANK0_PIN03_LCD_D11 0x01 159 #define HW_PINCTRL_MUXSEL0_BANK0_PIN03_SSP2_D3 0x02 160 #define HW_PINCTRL_MUXSEL0_BANK0_PIN03_GPIO 0x03 161 162 /* Pin 46, GPMI_D02 pin function selection */ 163 #define HW_PINCTRL_MUXSEL0_BANK0_PIN02_GPMI_DATA02 0x00 164 #define HW_PINCTRL_MUXSEL0_BANK0_PIN02_LCD_D10 0x01 165 #define HW_PINCTRL_MUXSEL0_BANK0_PIN02_SSP2_D2 0x02 166 #define HW_PINCTRL_MUXSEL0_BANK0_PIN02_GPIO 0x03 167 168 /* Pin 45, GPMI_D01 pin function selection */ 169 #define HW_PINCTRL_MUXSEL0_BANK0_PIN01_GPMI_DATA01 0x00 170 #define HW_PINCTRL_MUXSEL0_BANK0_PIN01_LCD_D9 0x01 171 #define HW_PINCTRL_MUXSEL0_BANK0_PIN01_SSP2_D1 0x02 172 #define HW_PINCTRL_MUXSEL0_BANK0_PIN01_GPIO 0x03 173 174 /* Pin 44, GPMI_D00 pin function selection */ 175 #define HW_PINCTRL_MUXSEL0_BANK0_PIN00_GPMI_DATA00 0x00 176 #define HW_PINCTRL_MUXSEL0_BANK0_PIN00_LCD_D8 0x01 177 #define HW_PINCTRL_MUXSEL0_BANK0_PIN00_SSP2_D0 0x02 178 #define HW_PINCTRL_MUXSEL0_BANK0_PIN00_GPIO 0x03 179 180 /* 181 * PINCTRL Pin Mux Select Register 1. 182 */ 183 #define HW_PINCTRL_MUXSEL1 0x110 184 #define HW_PINCTRL_MUXSEL1_SET 0x114 185 #define HW_PINCTRL_MUXSEL1_CLR 0x118 186 #define HW_PINCTRL_MUXSEL1_TOG 0x11C 187 188 #define HW_PINCTRL_MUXSEL1_BANK0_PIN31 __BITS(31, 30) 189 #define HW_PINCTRL_MUXSEL1_BANK0_PIN30 __BITS(29, 28) 190 #define HW_PINCTRL_MUXSEL1_BANK0_PIN29 __BITS(27, 26) 191 #define HW_PINCTRL_MUXSEL1_BANK0_PIN28 __BITS(25, 24) 192 #define HW_PINCTRL_MUXSEL1_BANK0_PIN27 __BITS(23, 22) 193 #define HW_PINCTRL_MUXSEL1_BANK0_PIN26 __BITS(21, 20) 194 #define HW_PINCTRL_MUXSEL1_BANK0_PIN25 __BITS(19, 18) 195 #define HW_PINCTRL_MUXSEL1_BANK0_PIN24 __BITS(17, 16) 196 #define HW_PINCTRL_MUXSEL1_BANK0_PIN23 __BITS(15, 14) 197 #define HW_PINCTRL_MUXSEL1_BANK0_PIN22 __BITS(13, 12) 198 #define HW_PINCTRL_MUXSEL1_BANK0_PIN21 __BITS(11, 10) 199 #define HW_PINCTRL_MUXSEL1_BANK0_PIN20 __BITS(9, 8) 200 #define HW_PINCTRL_MUXSEL1_BANK0_PIN19 __BITS(7, 6) 201 #define HW_PINCTRL_MUXSEL1_BANK0_PIN18 __BITS(5, 4) 202 #define HW_PINCTRL_MUXSEL1_BANK0_PIN17 __BITS(3, 2) 203 #define HW_PINCTRL_MUXSEL1_BANK0_PIN16 __BITS(1, 0) 204 205 /* Pin 4, I2C_SDA pin function selection */ 206 #define HW_PINCTRL_MUXSEL1_BANK0_PIN31_I2C_SD 0x00 207 #define HW_PINCTRL_MUXSEL1_BANK0_PIN31_GPMI_CE2N 0x01 208 #define HW_PINCTRL_MUXSEL1_BANK0_PIN31_AUART1_RX 0x02 209 #define HW_PINCTRL_MUXSEL1_BANK0_PIN31_GPIO 0x03 210 211 /* Pin 2, I2C_SCL pin function selection */ 212 #define HW_PINCTRL_MUXSEL1_BANK0_PIN30_I2C_CLK 0x00 213 #define HW_PINCTRL_MUXSEL1_BANK0_PIN30_GPMI_READY2 0x01 214 #define HW_PINCTRL_MUXSEL1_BANK0_PIN30_AUART1_TX 0x02 215 #define HW_PINCTRL_MUXSEL1_BANK0_PIN30_GPIO 0x03 216 217 /* Pin 69, AUART1_TX pin function selection */ 218 #define HW_PINCTRL_MUXSEL1_BANK0_PIN29_AUART1_TX 0x00 219 #define HW_PINCTRL_MUXSEL1_BANK0_PIN29_RESERVED 0x01 220 #define HW_PINCTRL_MUXSEL1_BANK0_PIN29_SSP1_D7 0x02 221 #define HW_PINCTRL_MUXSEL1_BANK0_PIN29_GPIO 0x03 222 223 /* Pin 68, AUART1_RX pin function selection */ 224 #define HW_PINCTRL_MUXSEL1_BANK0_PIN28_AUART1_RX 0x00 225 #define HW_PINCTRL_MUXSEL1_BANK0_PIN28_RESERVED 0x01 226 #define HW_PINCTRL_MUXSEL1_BANK0_PIN28_SSP1_D6 0x02 227 #define HW_PINCTRL_MUXSEL1_BANK0_PIN28_GPIO 0x03 228 229 /* Pin 67, AUART1_RTS pin function selection */ 230 #define HW_PINCTRL_MUXSEL1_BANK0_PIN27_AUART1_RTS 0x00 231 #define HW_PINCTRL_MUXSEL1_BANK0_PIN27_RESERVED 0x01 232 #define HW_PINCTRL_MUXSEL1_BANK0_PIN27_SSP1_D5 0x02 233 #define HW_PINCTRL_MUXSEL1_BANK0_PIN27_GPIO 0x03 234 235 /* Pin 66, AUART1_CTS pin function selection */ 236 #define HW_PINCTRL_MUXSEL1_BANK0_PIN26_AUART1_CTS 0x00 237 #define HW_PINCTRL_MUXSEL1_BANK0_PIN26_ESERVED 0x01 238 #define HW_PINCTRL_MUXSEL1_BANK0_PIN26_SSP1_D4 0x02 239 #define HW_PINCTRL_MUXSEL1_BANK0_PIN26_GPIO 0x03 240 241 /* Pin 60, GPMI_RDN pin function selection */ 242 #define HW_PINCTRL_MUXSEL1_BANK0_PIN25_GPMI_RDN 0x00 243 #define HW_PINCTRL_MUXSEL1_BANK0_PIN25_RESERVED1 0x01 244 #define HW_PINCTRL_MUXSEL1_BANK0_PIN25_RESERVED2 0x02 245 #define HW_PINCTRL_MUXSEL1_BANK0_PIN25_GPIO 0x03 246 247 /* Pin 65, GPMI_WRN pin function selection */ 248 #define HW_PINCTRL_MUXSEL1_BANK0_PIN24_GPMI_WRN 0x00 249 #define HW_PINCTRL_MUXSEL1_BANK0_PIN24_RESERVED 0x01 250 #define HW_PINCTRL_MUXSEL1_BANK0_PIN24_SSP2_SCK 0x02 251 #define HW_PINCTRL_MUXSEL1_BANK0_PIN24_GPIO 0x03 252 253 /* Pin 64, GPMI_WPN pin function selection */ 254 #define HW_PINCTRL_MUXSEL1_BANK0_PIN23_GPMI_WPN 0x00 255 #define HW_PINCTRL_MUXSEL1_BANK0_PIN23_RESERVED1 0x01 256 #define HW_PINCTRL_MUXSEL1_BANK0_PIN23_RESERVED2 0x02 257 #define HW_PINCTRL_MUXSEL1_BANK0_PIN23_GPIO 0x03 258 259 /* Pin 63, GPMI_RDY3 pin function selection */ 260 #define HW_PINCTRL_MUXSEL1_BANK0_PIN22_GPMI_READY3 0x00 261 #define HW_PINCTRL_MUXSEL1_BANK0_PIN22_RESERVED1 0x01 262 #define HW_PINCTRL_MUXSEL1_BANK0_PIN22_RESERVED2 0x02 263 #define HW_PINCTRL_MUXSEL1_BANK0_PIN22_GPIO 0x03 264 265 /* Pin 62, GPMI_RDY2 pin function selection */ 266 #define HW_PINCTRL_MUXSEL1_BANK0_PIN21_GPMI_READY2 0x00 267 #define HW_PINCTRL_MUXSEL1_BANK0_PIN21_RESERVED1 0x01 268 #define HW_PINCTRL_MUXSEL1_BANK0_PIN21_RESERVED2 0x02 269 #define HW_PINCTRL_MUXSEL1_BANK0_PIN21_GPIO 0x03 270 271 /* Pin 43, GPMI_RDY1 pin function selection */ 272 #define HW_PINCTRL_MUXSEL1_BANK0_PIN20_GPMI_READY1 0x00 273 #define HW_PINCTRL_MUXSEL1_BANK0_PIN20_RESERVED 0x01 274 #define HW_PINCTRL_MUXSEL1_BANK0_PIN20_SSP2_CMD 0x02 275 #define HW_PINCTRL_MUXSEL1_BANK0_PIN20_GPIO 0x03 276 277 /* Pin 61, GPMI_RDY0 pin function selection */ 278 #define HW_PINCTRL_MUXSEL1_BANK0_PIN19_GPMI_READY0 0x00 279 #define HW_PINCTRL_MUXSEL1_BANK0_PIN19_RESERVED 0x01 280 #define HW_PINCTRL_MUXSEL1_BANK0_PIN19_SSP2_DETECT 0x02 281 #define HW_PINCTRL_MUXSEL1_BANK0_PIN19_GPIO 0x03 282 283 /* Pin 42, GPMI_CE2N pin function selection */ 284 #define HW_PINCTRL_MUXSEL1_BANK0_PIN18_GPMI_CE2N 0x00 285 #define HW_PINCTRL_MUXSEL1_BANK0_PIN18_RESERVED1 0x01 286 #define HW_PINCTRL_MUXSEL1_BANK0_PIN18_RESERVED2 0x02 287 #define HW_PINCTRL_MUXSEL1_BANK0_PIN18_GPIO 0x03 288 289 /* Pin 41, GPMI_ALE pin function selection */ 290 #define HW_PINCTRL_MUXSEL1_BANK0_PIN17_GPMI_ALE 0x00 291 #define HW_PINCTRL_MUXSEL1_BANK0_PIN17_LCD_D17 0x01 292 #define HW_PINCTRL_MUXSEL1_BANK0_PIN17_RESERVED 0x02 293 #define HW_PINCTRL_MUXSEL1_BANK0_PIN17_GPIO 0x03 294 295 /* Pin 40, GPMI_CLE pin function selection */ 296 #define HW_PINCTRL_MUXSEL1_BANK0_PIN16_GPMI_CLE 0x00 297 #define HW_PINCTRL_MUXSEL1_BANK0_PIN16_LCD_D16 0x01 298 #define HW_PINCTRL_MUXSEL1_BANK0_PIN16_RESERVED 0x02 299 #define HW_PINCTRL_MUXSEL1_BANK0_PIN16_GPIO 0x03 300 301 /* 302 * PINCTRL Pin Mux Select Register 2. 303 */ 304 #define HW_PINCTRL_MUXSEL2 0x120 305 #define HW_PINCTRL_MUXSEL2_SET 0x124 306 #define HW_PINCTRL_MUXSEL2_CLR 0x128 307 #define HW_PINCTRL_MUXSEL2_TOG 0x12C 308 309 #define HW_PINCTRL_MUXSEL2_BANK1_PIN15 __BITS(31, 30) 310 #define HW_PINCTRL_MUXSEL2_BANK1_PIN14 __BITS(29, 28) 311 #define HW_PINCTRL_MUXSEL2_BANK1_PIN13 __BITS(27, 26) 312 #define HW_PINCTRL_MUXSEL2_BANK1_PIN12 __BITS(25, 24) 313 #define HW_PINCTRL_MUXSEL2_BANK1_PIN11 __BITS(23, 22) 314 #define HW_PINCTRL_MUXSEL2_BANK1_PIN10 __BITS(21, 20) 315 #define HW_PINCTRL_MUXSEL2_BANK1_PIN09 __BITS(19, 18) 316 #define HW_PINCTRL_MUXSEL2_BANK1_PIN08 __BITS(17, 16) 317 #define HW_PINCTRL_MUXSEL2_BANK1_PIN07 __BITS(15, 14) 318 #define HW_PINCTRL_MUXSEL2_BANK1_PIN06 __BITS(13, 12) 319 #define HW_PINCTRL_MUXSEL2_BANK1_PIN05 __BITS(11, 10) 320 #define HW_PINCTRL_MUXSEL2_BANK1_PIN04 __BITS(9, 8) 321 #define HW_PINCTRL_MUXSEL2_BANK1_PIN03 __BITS(7, 6) 322 #define HW_PINCTRL_MUXSEL2_BANK1_PIN02 __BITS(5, 4) 323 #define HW_PINCTRL_MUXSEL2_BANK1_PIN01 __BITS(3, 2) 324 #define HW_PINCTRL_MUXSEL2_BANK1_PIN00 __BITS(1, 0) 325 326 /* Pin 15, LCD_D15 pin function selection */ 327 #define HW_PINCTRL_MUXSEL2_BANK1_PIN15_LCD_D15 0x00 328 #define HW_PINCTRL_MUXSEL2_BANK1_PIN15_ETM_DA7 0x01 329 #define HW_PINCTRL_MUXSEL2_BANK1_PIN15_SAIF1_SDATA1 0x02 330 #define HW_PINCTRL_MUXSEL2_BANK1_PIN15_GPIO 0x03 331 332 /* Pin 17, LCD_D14 pin function selection */ 333 #define HW_PINCTRL_MUXSEL2_BANK1_PIN14_LCD_D14 0x00 334 #define HW_PINCTRL_MUXSEL2_BANK1_PIN14_ETM_DA6 0x01 335 #define HW_PINCTRL_MUXSEL2_BANK1_PIN14_SAIF1_SDATA2 0x02 336 #define HW_PINCTRL_MUXSEL2_BANK1_PIN14_GPIO 0x03 337 338 /* Pin 19, LCD_D13 pin function selection */ 339 #define HW_PINCTRL_MUXSEL2_BANK1_PIN13_LCD_D13 0x00 340 #define HW_PINCTRL_MUXSEL2_BANK1_PIN13_ETM_DA5 0x01 341 #define HW_PINCTRL_MUXSEL2_BANK1_PIN13_SAIF2_SDATA2 0x02 342 #define HW_PINCTRL_MUXSEL2_BANK1_PIN13_GPIO 0x03 343 344 /* Pin 22, LCD_D12 pin function selection */ 345 #define HW_PINCTRL_MUXSEL2_BANK1_PIN12_LCD_D12 0x00 346 #define HW_PINCTRL_MUXSEL2_BANK1_PIN12_ETM_DA4 0x01 347 #define HW_PINCTRL_MUXSEL2_BANK1_PIN12_SAIF2_SDATA1 0x02 348 #define HW_PINCTRL_MUXSEL2_BANK1_PIN12_GPIO 0x03 349 350 /* Pin 24, LCD_D11 pin function selection */ 351 #define HW_PINCTRL_MUXSEL2_BANK1_PIN11_LCD_D11 0x00 352 #define HW_PINCTRL_MUXSEL2_BANK1_PIN11_ETM_DA3 0x01 353 #define HW_PINCTRL_MUXSEL2_BANK1_PIN11_SAIF_LRCLK 0x02 354 #define HW_PINCTRL_MUXSEL2_BANK1_PIN11_GPIO 0x03 355 356 /* Pin 26, LCD_D10 pin function selection */ 357 #define HW_PINCTRL_MUXSEL2_BANK1_PIN10_LCD_D10 0x00 358 #define HW_PINCTRL_MUXSEL2_BANK1_PIN10_ETM_DA2 0x01 359 #define HW_PINCTRL_MUXSEL2_BANK1_PIN10_SAIF_BITCLK 0x02 360 #define HW_PINCTRL_MUXSEL2_BANK1_PIN10_GPIO 0x03 361 362 /* Pin 28, LCD_D09 pin function selection */ 363 #define HW_PINCTRL_MUXSEL2_BANK1_PIN09_LCD_D9 0x00 364 #define HW_PINCTRL_MUXSEL2_BANK1_PIN09_ETM_DA1 0x01 365 #define HW_PINCTRL_MUXSEL2_BANK1_PIN09_SAIF1_SDATA0 0x02 366 #define HW_PINCTRL_MUXSEL2_BANK1_PIN09_GPIO 0x03 367 368 /* Pin 27, LCD_D08 pin function selection */ 369 #define HW_PINCTRL_MUXSEL2_BANK1_PIN08_LCD_D8 0x00 370 #define HW_PINCTRL_MUXSEL2_BANK1_PIN08_ETM_DA0 0x01 371 #define HW_PINCTRL_MUXSEL2_BANK1_PIN08_SAIF2_SDATA0 0x02 372 #define HW_PINCTRL_MUXSEL2_BANK1_PIN08_GPIO 0x03 373 374 /* Pin 25, LCD_D07 pin function selection */ 375 #define HW_PINCTRL_MUXSEL2_BANK1_PIN07_LCD_D7 0x00 376 #define HW_PINCTRL_MUXSEL2_BANK1_PIN07_ETM_DA15 0x01 377 #define HW_PINCTRL_MUXSEL2_BANK1_PIN07_RESERVED 0x02 378 #define HW_PINCTRL_MUXSEL2_BANK1_PIN07_GPIO 0x03 379 380 /* Pin 23, LCD_D06 pin function selection */ 381 #define HW_PINCTRL_MUXSEL2_BANK1_PIN06_LCD_D6 0x00 382 #define HW_PINCTRL_MUXSEL2_BANK1_PIN06_ETM_DA14 0x01 383 #define HW_PINCTRL_MUXSEL2_BANK1_PIN06_RESERVED 0x02 384 #define HW_PINCTRL_MUXSEL2_BANK1_PIN06_GPIO 0x03 385 386 /* Pin 21, LCD_D05 pin function selection */ 387 #define HW_PINCTRL_MUXSEL2_BANK1_PIN05_LCD_D5 0x00 388 #define HW_PINCTRL_MUXSEL2_BANK1_PIN05_ETM_DA13 0x01 389 #define HW_PINCTRL_MUXSEL2_BANK1_PIN05_RESERVED 0x02 390 #define HW_PINCTRL_MUXSEL2_BANK1_PIN05_GPIO 0x03 391 392 /* Pin 18, LCD_D04 pin function selection */ 393 #define HW_PINCTRL_MUXSEL2_BANK1_PIN04_LCD_D4 0x00 394 #define HW_PINCTRL_MUXSEL2_BANK1_PIN04_ETM_DA12 0x01 395 #define HW_PINCTRL_MUXSEL2_BANK1_PIN04_RESERVED 0x02 396 #define HW_PINCTRL_MUXSEL2_BANK1_PIN04_GPIO 0x03 397 398 /* Pin 16, LCD_D03 pin function selection */ 399 #define HW_PINCTRL_MUXSEL2_BANK1_PIN03_LCD_D3 0x00 400 #define HW_PINCTRL_MUXSEL2_BANK1_PIN03_ETM_DA11 0x01 401 #define HW_PINCTRL_MUXSEL2_BANK1_PIN03_RESERVED 0x02 402 #define HW_PINCTRL_MUXSEL2_BANK1_PIN03_GPIO 0x03 403 404 /* Pin 14, LCD_D02 pin function selection */ 405 #define HW_PINCTRL_MUXSEL2_BANK1_PIN02_LCD_D2 0x00 406 #define HW_PINCTRL_MUXSEL2_BANK1_PIN02_ETM_DA10 0x01 407 #define HW_PINCTRL_MUXSEL2_BANK1_PIN02_RESERVED 0x02 408 #define HW_PINCTRL_MUXSEL2_BANK1_PIN02_GPIO 0x03 409 410 /* Pin 12, LCD_D01 pin function selection */ 411 #define HW_PINCTRL_MUXSEL2_BANK1_PIN01_LCD_D1 0x00 412 #define HW_PINCTRL_MUXSEL2_BANK1_PIN01_ETM_DA9 0x01 413 #define HW_PINCTRL_MUXSEL2_BANK1_PIN01_RESERVED 0x02 414 #define HW_PINCTRL_MUXSEL2_BANK1_PIN01_GPIO 0x03 415 416 /* Pin 10, LCD_D00 pin function selection */ 417 #define HW_PINCTRL_MUXSEL2_BANK1_PIN00_LCD_D0 0x00 418 #define HW_PINCTRL_MUXSEL2_BANK1_PIN00_ETM_DA8 0x01 419 #define HW_PINCTRL_MUXSEL2_BANK1_PIN00_RESERVED 0x02 420 #define HW_PINCTRL_MUXSEL2_BANK1_PIN00_GPIO 0x03 421 422 /* 423 * PINCTRL Pin Mux Select Register 3. 424 */ 425 #define HW_PINCTRL_MUXSEL3 0x130 426 #define HW_PINCTRL_MUXSEL3_SET 0x134 427 #define HW_PINCTRL_MUXSEL3_CLR 0x138 428 #define HW_PINCTRL_MUXSEL3_TOG 0x13C 429 430 #define HW_PINCTRL_MUXSEL3_RSRVD0 __BITS(31, 30) 431 #define HW_PINCTRL_MUXSEL3_BANK1_PIN30 __BITS(29, 28) 432 #define HW_PINCTRL_MUXSEL3_BANK1_PIN29 __BITS(27, 26) 433 #define HW_PINCTRL_MUXSEL3_BANK1_PIN28 __BITS(25, 24) 434 #define HW_PINCTRL_MUXSEL3_BANK1_PIN27 __BITS(23, 22) 435 #define HW_PINCTRL_MUXSEL3_BANK1_PIN26 __BITS(21, 20) 436 #define HW_PINCTRL_MUXSEL3_BANK1_PIN25 __BITS(19, 18) 437 #define HW_PINCTRL_MUXSEL3_BANK1_PIN24 __BITS(17, 16) 438 #define HW_PINCTRL_MUXSEL3_BANK1_PIN23 __BITS(15, 14) 439 #define HW_PINCTRL_MUXSEL3_BANK1_PIN22 __BITS(13, 12) 440 #define HW_PINCTRL_MUXSEL3_BANK1_PIN21 __BITS(11, 10) 441 #define HW_PINCTRL_MUXSEL3_BANK1_PIN20 __BITS(9, 8) 442 #define HW_PINCTRL_MUXSEL3_BANK1_PIN19 __BITS(7, 6) 443 #define HW_PINCTRL_MUXSEL3_BANK1_PIN18 __BITS(5, 4) 444 #define HW_PINCTRL_MUXSEL3_BANK1_PIN17 __BITS(3, 2) 445 #define HW_PINCTRL_MUXSEL3_BANK1_PIN16 __BITS(1, 0) 446 447 /* Always write zeroes to this field */ 448 #define HW_PINCTRL_MUXSEL3_RSRVD0_ZERO 0x00 449 450 /* Pin 131, PWM4 pin function selection */ 451 #define HW_PINCTRL_MUXSEL3_BANK1_PIN30_PWM4 0x00 452 #define HW_PINCTRL_MUXSEL3_BANK1_PIN30_ETM_TCLK 0x01 453 #define HW_PINCTRL_MUXSEL3_BANK1_PIN30_AUART1_RTS 0x02 454 #define HW_PINCTRL_MUXSEL3_BANK1_PIN30_GPIO 0x03 455 456 /* Pin 130, PWM3 pin function selection */ 457 #define HW_PINCTRL_MUXSEL3_BANK1_PIN29_PWM3 0x00 458 #define HW_PINCTRL_MUXSEL3_BANK1_PIN29_ETM_TCTL 0x01 459 #define HW_PINCTRL_MUXSEL3_BANK1_PIN29_AUART1_CTS 0x02 460 #define HW_PINCTRL_MUXSEL3_BANK1_PIN29_GPIO 0x03 461 462 /* Pin 129, PWM2 pin function selection */ 463 #define HW_PINCTRL_MUXSEL3_BANK1_PIN28_PWM2 0x00 464 #define HW_PINCTRL_MUXSEL3_BANK1_PIN28_GPMI_READY3 0x01 465 #define HW_PINCTRL_MUXSEL3_BANK1_PIN28_RESERVED 0x02 466 #define HW_PINCTRL_MUXSEL3_BANK1_PIN28_GPIO 0x03 467 468 /* Pin 3, PWM1 pin function selection */ 469 #define HW_PINCTRL_MUXSEL3_BANK1_PIN27_PWM1 0x00 470 #define HW_PINCTRL_MUXSEL3_BANK1_PIN27_TIMROT2 0x01 471 #define HW_PINCTRL_MUXSEL3_BANK1_PIN27_DUART_TX 0x02 472 #define HW_PINCTRL_MUXSEL3_BANK1_PIN27_GPIO 0x03 473 474 /* Pin 1, PWM0 pin function selection */ 475 #define HW_PINCTRL_MUXSEL3_BANK1_PIN26_PWM0 0x00 476 #define HW_PINCTRL_MUXSEL3_BANK1_PIN26_TIMROT1 0x01 477 #define HW_PINCTRL_MUXSEL3_BANK1_PIN26_DUART_RX 0x02 478 #define HW_PINCTRL_MUXSEL3_BANK1_PIN26_GPIO 0x03 479 480 /* Pin 35, LCD_VSYNC pin function selection */ 481 #define HW_PINCTRL_MUXSEL3_BANK1_PIN25_LCD_VSYNC 0x00 482 #define HW_PINCTRL_MUXSEL3_BANK1_PIN25_LCD_BUSY 0x01 483 #define HW_PINCTRL_MUXSEL3_BANK1_PIN25_RESERVED 0x02 484 #define HW_PINCTRL_MUXSEL3_BANK1_PIN25_GPIO 0x03 485 486 /* Pin 34, LCD_HSYNC pin function selection */ 487 #define HW_PINCTRL_MUXSEL3_BANK1_PIN24_LCD_HSYNC 0x00 488 #define HW_PINCTRL_MUXSEL3_BANK1_PIN24_I2C_SD 0x01 489 #define HW_PINCTRL_MUXSEL3_BANK1_PIN24_RESERVED 0x02 490 #define HW_PINCTRL_MUXSEL3_BANK1_PIN24_GPIO 0x03 491 492 /* Pin 30, LCD_ENABLE pin function selection */ 493 #define HW_PINCTRL_MUXSEL3_BANK1_PIN23_LCD_ENABLE 0x00 494 #define HW_PINCTRL_MUXSEL3_BANK1_PIN23_I2C_CLK 0x01 495 #define HW_PINCTRL_MUXSEL3_BANK1_PIN23_RESERVED 0x02 496 #define HW_PINCTRL_MUXSEL3_BANK1_PIN23_GPIO 0x03 497 498 /* Pin 36, LCD_DOTCK pin function selection */ 499 #define HW_PINCTRL_MUXSEL3_BANK1_PIN22_LCD_DOTCK 0x00 500 #define HW_PINCTRL_MUXSEL3_BANK1_PIN22_GPMI_READY3 0x01 501 #define HW_PINCTRL_MUXSEL3_BANK1_PIN22_RESERVED 0x02 502 #define HW_PINCTRL_MUXSEL3_BANK1_PIN22_GPIO 0x03 503 504 /* Pin 29, LCD_CS pin function selection */ 505 #define HW_PINCTRL_MUXSEL3_BANK1_PIN21_LCD_CS 0x00 506 #define HW_PINCTRL_MUXSEL3_BANK1_PIN21_RESERVED1 0x01 507 #define HW_PINCTRL_MUXSEL3_BANK1_PIN21_RESERVED2 0x02 508 #define HW_PINCTRL_MUXSEL3_BANK1_PIN21_GPIO 0x03 509 510 /* Pin 32, LCD_WR pin function selection */ 511 #define HW_PINCTRL_MUXSEL3_BANK1_PIN20_LCD_WR 0x00 512 #define HW_PINCTRL_MUXSEL3_BANK1_PIN20_RESERVED1 0x01 513 #define HW_PINCTRL_MUXSEL3_BANK1_PIN20_RESERVED2 0x02 514 #define HW_PINCTRL_MUXSEL3_BANK1_PIN20_GPIO 0x03 515 516 /* Pin 33, LCD_RS pin function selection */ 517 #define HW_PINCTRL_MUXSEL3_BANK1_PIN19_LCD_RS 0x00 518 #define HW_PINCTRL_MUXSEL3_BANK1_PIN19_ETM_TCLK 0x01 519 #define HW_PINCTRL_MUXSEL3_BANK1_PIN19_RESERVED 0x02 520 #define HW_PINCTRL_MUXSEL3_BANK1_PIN19_GPIO 0x03 521 522 /* Pin 31, LCD_RESET pin function selection */ 523 #define HW_PINCTRL_MUXSEL3_BANK1_PIN18_LCD_RESET 0x00 524 #define HW_PINCTRL_MUXSEL3_BANK1_PIN18_ETM_TCTL 0x01 525 #define HW_PINCTRL_MUXSEL3_BANK1_PIN18_GPMI_CE3N 0x02 526 #define HW_PINCTRL_MUXSEL3_BANK1_PIN18_GPIO 0x03 527 528 /* Pin 11, LCD_D17 pin function selection */ 529 #define HW_PINCTRL_MUXSEL3_BANK1_PIN17_LCD_D17 0x00 530 #define HW_PINCTRL_MUXSEL3_BANK1_PIN17_RESERVED1 0x01 531 #define HW_PINCTRL_MUXSEL3_BANK1_PIN17_RESERVED2 0x02 532 #define HW_PINCTRL_MUXSEL3_BANK1_PIN17_GPIO 0x03 533 534 /* Pin 13, LCD_D16 pin function selection */ 535 #define HW_PINCTRL_MUXSEL3_BANK1_PIN16_LCD_D16 0x00 536 #define HW_PINCTRL_MUXSEL3_BANK1_PIN16_RESERVED 0x01 537 #define HW_PINCTRL_MUXSEL3_BANK1_PIN16_SAIF_ALT_BITCLK 0x02 538 #define HW_PINCTRL_MUXSEL3_BANK1_PIN16_GPIO 0x03 539 540 /* 541 * PINCTRL Pin Mux Select Register 4. 542 */ 543 #define HW_PINCTRL_MUXSEL4 0x140 544 #define HW_PINCTRL_MUXSEL4_SET 0x144 545 #define HW_PINCTRL_MUXSEL4_CLR 0x148 546 #define HW_PINCTRL_MUXSEL4_TOG 0x14C 547 548 #define HW_PINCTRL_MUXSEL4_BANK2_PIN15 __BITS(31,30) 549 #define HW_PINCTRL_MUXSEL4_BANK2_PIN14 __BITS(29,28) 550 #define HW_PINCTRL_MUXSEL4_BANK2_PIN13 __BITS(27,26) 551 #define HW_PINCTRL_MUXSEL4_BANK2_PIN12 __BITS(25,24) 552 #define HW_PINCTRL_MUXSEL4_BANK2_PIN11 __BITS(23,22) 553 #define HW_PINCTRL_MUXSEL4_BANK2_PIN10 __BITS(21,20) 554 #define HW_PINCTRL_MUXSEL4_BANK2_PIN09 __BITS(19,18) 555 #define HW_PINCTRL_MUXSEL4_BANK2_PIN08 __BITS(17,16) 556 #define HW_PINCTRL_MUXSEL4_BANK2_PIN07 __BITS(15,14) 557 #define HW_PINCTRL_MUXSEL4_BANK2_PIN06 __BITS(13,12) 558 #define HW_PINCTRL_MUXSEL4_BANK2_PIN05 __BITS(11,10) 559 #define HW_PINCTRL_MUXSEL4_BANK2_PIN04 __BITS(9,8) 560 #define HW_PINCTRL_MUXSEL4_BANK2_PIN03 __BITS(7,6) 561 #define HW_PINCTRL_MUXSEL4_BANK2_PIN02 __BITS(5,4) 562 #define HW_PINCTRL_MUXSEL4_BANK2_PIN01 __BITS(3,2) 563 #define HW_PINCTRL_MUXSEL4_BANK2_PIN00 __BITS(1,0) 564 565 /* Pin 108, EMI_A06 pin function selection */ 566 #define HW_PINCTRL_MUXSEL4_BANK2_PIN15_EMI_ADDR06 0x00 567 #define HW_PINCTRL_MUXSEL4_BANK2_PIN15_RESERVED1 0x01 568 #define HW_PINCTRL_MUXSEL4_BANK2_PIN15_RESERVED2 0x02 569 #define HW_PINCTRL_MUXSEL4_BANK2_PIN15_GPIO 0x03 570 571 /* Pin 107, EMI_A05 pin function selection */ 572 #define HW_PINCTRL_MUXSEL4_BANK2_PIN14_EMI_ADDR05 0x00 573 #define HW_PINCTRL_MUXSEL4_BANK2_PIN14_RESERVED1 0x01 574 #define HW_PINCTRL_MUXSEL4_BANK2_PIN14_RESERVED2 0x02 575 #define HW_PINCTRL_MUXSEL4_BANK2_PIN14_GPIO 0x03 576 577 /* Pin 109, EMI_A04 pin function selection */ 578 #define HW_PINCTRL_MUXSEL4_BANK2_PIN13_EMI_ADDR04 0x00 579 #define HW_PINCTRL_MUXSEL4_BANK2_PIN13_RESERVED1 0x01 580 #define HW_PINCTRL_MUXSEL4_BANK2_PIN13_RESERVED2 0x02 581 #define HW_PINCTRL_MUXSEL4_BANK2_PIN13_GPIO 0x03 582 583 /* Pin 110, EMI_A03 pin function selection */ 584 #define HW_PINCTRL_MUXSEL4_BANK2_PIN12_EMI_ADDR03 0x00 585 #define HW_PINCTRL_MUXSEL4_BANK2_PIN12_RESERVED1 0x01 586 #define HW_PINCTRL_MUXSEL4_BANK2_PIN12_RESERVED2 0x02 587 #define HW_PINCTRL_MUXSEL4_BANK2_PIN12_GPIO 0x03 588 589 /* Pin 111, EMI_A02 pin function selection */ 590 #define HW_PINCTRL_MUXSEL4_BANK2_PIN11_EMI_ADDR02 0x00 591 #define HW_PINCTRL_MUXSEL4_BANK2_PIN11_RESERVED1 0x01 592 #define HW_PINCTRL_MUXSEL4_BANK2_PIN11_RESERVED2 0x02 593 #define HW_PINCTRL_MUXSEL4_BANK2_PIN11_GPIO 0x03 594 595 /* Pin 112, EMI_A01 pin function selection */ 596 #define HW_PINCTRL_MUXSEL4_BANK2_PIN10_EMI_ADDR01 0x00 597 #define HW_PINCTRL_MUXSEL4_BANK2_PIN10_RESERVED1 0x01 598 #define HW_PINCTRL_MUXSEL4_BANK2_PIN10_RESERVED2 0x02 599 #define HW_PINCTRL_MUXSEL4_BANK2_PIN10_GPIO 0x03 600 601 /* Pin 113, EMI_A00 pin function selection */ 602 #define HW_PINCTRL_MUXSEL4_BANK2_PIN09_EMI_ADDR00 0x00 603 #define HW_PINCTRL_MUXSEL4_BANK2_PIN09_RESERVED1 0x01 604 #define HW_PINCTRL_MUXSEL4_BANK2_PIN09_RESERVED2 0x02 605 #define HW_PINCTRL_MUXSEL4_BANK2_PIN09_GPIO 0x03 606 607 /* Pin 38, ROTARYB pin function selection */ 608 #define HW_PINCTRL_MUXSEL4_BANK2_PIN08_TIMROT2 0x00 609 #define HW_PINCTRL_MUXSEL4_BANK2_PIN08_AUART2_CTS 0x01 610 #define HW_PINCTRL_MUXSEL4_BANK2_PIN08_GPMI_CE3N 0x02 611 #define HW_PINCTRL_MUXSEL4_BANK2_PIN08_GPIO 0x03 612 613 /* Pin 37, ROTARYA pin function selection */ 614 #define HW_PINCTRL_MUXSEL4_BANK2_PIN07_TIMROT1 0x00 615 #define HW_PINCTRL_MUXSEL4_BANK2_PIN07_AUART2_RTS 0x01 616 #define HW_PINCTRL_MUXSEL4_BANK2_PIN07_SPDIF 0x02 617 #define HW_PINCTRL_MUXSEL4_BANK2_PIN07_GPIO 0x03 618 619 /* Pin 127, SSP1_SCK pin function selection */ 620 #define HW_PINCTRL_MUXSEL4_BANK2_PIN06_SSP1_SCK 0x00 621 #define HW_PINCTRL_MUXSEL4_BANK2_PIN06_RESERVED 0x01 622 #define HW_PINCTRL_MUXSEL4_BANK2_PIN06_ALT_JTAG_TRST_N 0x02 623 #define HW_PINCTRL_MUXSEL4_BANK2_PIN06_GPIO 0x03 624 625 /* Pin 125, SSP1_DATA3 pin function selection */ 626 #define HW_PINCTRL_MUXSEL4_BANK2_PIN05_SSP1_D3 0x00 627 #define HW_PINCTRL_MUXSEL4_BANK2_PIN05_RESERVED 0x01 628 #define HW_PINCTRL_MUXSEL4_BANK2_PIN05_ALT_JTAG_TMS 0x02 629 #define HW_PINCTRL_MUXSEL4_BANK2_PIN05_GPIO 0x03 630 631 /* Pin 124, SSP1_DATA2 pin function selection */ 632 #define HW_PINCTRL_MUXSEL4_BANK2_PIN04_SSP1_D2 0x00 633 #define HW_PINCTRL_MUXSEL4_BANK2_PIN04_I2C_SD 0x01 634 #define HW_PINCTRL_MUXSEL4_BANK2_PIN04_ALT_JTAG_RTCK 0x02 635 #define HW_PINCTRL_MUXSEL4_BANK2_PIN04_GPIO 0x03 636 637 /* Pin 123, SSP1_DATA1 pin function selection */ 638 #define HW_PINCTRL_MUXSEL4_BANK2_PIN03_SSP1_D1 0x00 639 #define HW_PINCTRL_MUXSEL4_BANK2_PIN03_I2C_CLK 0x01 640 #define HW_PINCTRL_MUXSEL4_BANK2_PIN03_ALT_JTAG_TCK 0x02 641 #define HW_PINCTRL_MUXSEL4_BANK2_PIN03_GPIO 0x03 642 643 /* Pin 122, SSP1_DATA0 pin function selection */ 644 #define HW_PINCTRL_MUXSEL4_BANK2_PIN02_SSP1_D0 0x00 645 #define HW_PINCTRL_MUXSEL4_BANK2_PIN02_RESERVED 0x01 646 #define HW_PINCTRL_MUXSEL4_BANK2_PIN02_ALT_JTAG_TDI 0x02 647 #define HW_PINCTRL_MUXSEL4_BANK2_PIN02_GPIO 0x03 648 649 /* Pin 126, SSP1_DETECT pin function selection */ 650 #define HW_PINCTRL_MUXSEL4_BANK2_PIN01_SSP1_DETECT 0x00 651 #define HW_PINCTRL_MUXSEL4_BANK2_PIN01_GPMI_CE3N 0x01 652 #define HW_PINCTRL_MUXSEL4_BANK2_PIN01_USB_ID 0x02 653 #define HW_PINCTRL_MUXSEL4_BANK2_PIN01_GPIO 0x03 654 655 /* Pin 121, SSP1_CMD pin function selection */ 656 #define HW_PINCTRL_MUXSEL4_BANK2_PIN00_SSP1_CMD 0x00 657 #define HW_PINCTRL_MUXSEL4_BANK2_PIN00_RESERVED 0x01 658 #define HW_PINCTRL_MUXSEL4_BANK2_PIN00_ALT_JTAG_TDO 0x02 659 #define HW_PINCTRL_MUXSEL4_BANK2_PIN00_GPIO 0x03 660 661 /* 662 * PINCTRL Pin Mux Select Register 5. 663 */ 664 #define HW_PINCTRL_MUXSEL5 0x150 665 #define HW_PINCTRL_MUXSEL5_SET 0x154 666 #define HW_PINCTRL_MUXSEL5_CLR 0x158 667 #define HW_PINCTRL_MUXSEL5_TOG 0x15C 668 669 #define HW_PINCTRL_MUXSEL5_BANK2_PIN31 __BITS(31,30) 670 #define HW_PINCTRL_MUXSEL5_BANK2_PIN30 __BITS(29,28) 671 #define HW_PINCTRL_MUXSEL5_BANK2_PIN29 __BITS(27,26) 672 #define HW_PINCTRL_MUXSEL5_BANK2_PIN28 __BITS(25,24) 673 #define HW_PINCTRL_MUXSEL5_BANK2_PIN27 __BITS(23,22) 674 #define HW_PINCTRL_MUXSEL5_BANK2_PIN26 __BITS(21,20) 675 #define HW_PINCTRL_MUXSEL5_BANK2_PIN25 __BITS(19,18) 676 #define HW_PINCTRL_MUXSEL5_BANK2_PIN24 __BITS(17,16) 677 #define HW_PINCTRL_MUXSEL5_BANK2_PIN23 __BITS(15,14) 678 #define HW_PINCTRL_MUXSEL5_BANK2_PIN22 __BITS(13,12) 679 #define HW_PINCTRL_MUXSEL5_BANK2_PIN21 __BITS(11,10) 680 #define HW_PINCTRL_MUXSEL5_BANK2_PIN20 __BITS(9,8) 681 #define HW_PINCTRL_MUXSEL5_BANK2_PIN19 __BITS(7,6) 682 #define HW_PINCTRL_MUXSEL5_BANK2_PIN18 __BITS(5,4) 683 #define HW_PINCTRL_MUXSEL5_BANK2_PIN17 __BITS(3,2) 684 #define HW_PINCTRL_MUXSEL5_BANK2_PIN16 __BITS(1,0) 685 686 /* Pin 114, EMI_WEN pin function selection */ 687 #define HW_PINCTRL_MUXSEL5_BANK2_PIN31_EMI_WEN 0x00 688 #define HW_PINCTRL_MUXSEL5_BANK2_PIN31_RESERVED1 0x01 689 #define HW_PINCTRL_MUXSEL5_BANK2_PIN31_RESERVED2 0x02 690 #define HW_PINCTRL_MUXSEL5_BANK2_PIN31_GPIO 0x03 691 692 /* Pin 98, EMI_RASN pin function selection */ 693 #define HW_PINCTRL_MUXSEL5_BANK2_PIN30_EMI_RASN 0x00 694 #define HW_PINCTRL_MUXSEL5_BANK2_PIN30_RESERVED1 0x01 695 #define HW_PINCTRL_MUXSEL5_BANK2_PIN30_RESERVED2 0x02 696 #define HW_PINCTRL_MUXSEL5_BANK2_PIN30_GPIO 0x03 697 698 /* Pin 115, EMI_CKE pin function selection */ 699 #define HW_PINCTRL_MUXSEL5_BANK2_PIN29_EMI_CKE 0x00 700 #define HW_PINCTRL_MUXSEL5_BANK2_PIN29_RESERVED1 0x01 701 #define HW_PINCTRL_MUXSEL5_BANK2_PIN29_RESERVED2 0x02 702 #define HW_PINCTRL_MUXSEL5_BANK2_PIN29_GPIO 0x03 703 704 /* Pin 120, GPMI_CE0N pin function selection */ 705 #define HW_PINCTRL_MUXSEL5_BANK2_PIN28_GPMI_CE0N 0x00 706 #define HW_PINCTRL_MUXSEL5_BANK2_PIN28_RESERVED1 0x01 707 #define HW_PINCTRL_MUXSEL5_BANK2_PIN28_RESERVED2 0x02 708 #define HW_PINCTRL_MUXSEL5_BANK2_PIN28_GPIO 0x03 709 710 /* Pin 118, GPMI_CE1N pin function selection */ 711 #define HW_PINCTRL_MUXSEL5_BANK2_PIN27_GPMI_CE1N 0x00 712 #define HW_PINCTRL_MUXSEL5_BANK2_PIN27_RESERVED1 0x01 713 #define HW_PINCTRL_MUXSEL5_BANK2_PIN27_RESERVED2 0x02 714 #define HW_PINCTRL_MUXSEL5_BANK2_PIN27_GPIO 0x03 715 716 /* Pin 99, EMI_CE1N pin function selection */ 717 #define HW_PINCTRL_MUXSEL5_BANK2_PIN26_EMI_CE1N 0x00 718 #define HW_PINCTRL_MUXSEL5_BANK2_PIN26_RESERVED1 0x01 719 #define HW_PINCTRL_MUXSEL5_BANK2_PIN26_RESERVED2 0x02 720 #define HW_PINCTRL_MUXSEL5_BANK2_PIN26_GPIO 0x03 721 722 /* Pin 100, EMI_CE0N pin function selection */ 723 #define HW_PINCTRL_MUXSEL5_BANK2_PIN25_EMI_CE0N 0x00 724 #define HW_PINCTRL_MUXSEL5_BANK2_PIN25_RESERVED1 0x01 725 #define HW_PINCTRL_MUXSEL5_BANK2_PIN25_RESERVED2 0x02 726 #define HW_PINCTRL_MUXSEL5_BANK2_PIN25_GPIO 0x03 727 728 /* Pin 97, EMI_CASN pin function selection */ 729 #define HW_PINCTRL_MUXSEL5_BANK2_PIN24_EMI_CASN 0x00 730 #define HW_PINCTRL_MUXSEL5_BANK2_PIN24_RESERVED1 0x01 731 #define HW_PINCTRL_MUXSEL5_BANK2_PIN24_RESERVED2 0x02 732 #define HW_PINCTRL_MUXSEL5_BANK2_PIN24_GPIO 0x03 733 734 /* Pin 117, EMI_BA1 pin function selection */ 735 #define HW_PINCTRL_MUXSEL5_BANK2_PIN23_EMI_BA1 0x00 736 #define HW_PINCTRL_MUXSEL5_BANK2_PIN23_RESERVED1 0x01 737 #define HW_PINCTRL_MUXSEL5_BANK2_PIN23_RESERVED2 0x02 738 #define HW_PINCTRL_MUXSEL5_BANK2_PIN23_GPIO 0x03 739 740 /* Pin 116, EMI_BA0 pin function selection */ 741 #define HW_PINCTRL_MUXSEL5_BANK2_PIN22_EMI_BA0 0x00 742 #define HW_PINCTRL_MUXSEL5_BANK2_PIN22_RESERVED1 0x01 743 #define HW_PINCTRL_MUXSEL5_BANK2_PIN22_RESERVED2 0x02 744 #define HW_PINCTRL_MUXSEL5_BANK2_PIN22_GPIO 0x03 745 746 /* Pin 101, EMI_A12 pin function selection */ 747 #define HW_PINCTRL_MUXSEL5_BANK2_PIN21_EMI_ADDR12 0x00 748 #define HW_PINCTRL_MUXSEL5_BANK2_PIN21_RESERVED1 0x01 749 #define HW_PINCTRL_MUXSEL5_BANK2_PIN21_RESERVED2 0x02 750 #define HW_PINCTRL_MUXSEL5_BANK2_PIN21_GPIO 0x03 751 752 /* Pin 102, EMI_A11 pin function selection */ 753 #define HW_PINCTRL_MUXSEL5_BANK2_PIN20_EMI_ADDR11 0x00 754 #define HW_PINCTRL_MUXSEL5_BANK2_PIN20_RESERVED1 0x01 755 #define HW_PINCTRL_MUXSEL5_BANK2_PIN20_RESERVED2 0x02 756 #define HW_PINCTRL_MUXSEL5_BANK2_PIN20_GPIO 0x03 757 758 /* Pin 104, EMI_A10 pin function selection */ 759 #define HW_PINCTRL_MUXSEL5_BANK2_PIN19_EMI_ADDR10 0x00 760 #define HW_PINCTRL_MUXSEL5_BANK2_PIN19_RESERVED1 0x01 761 #define HW_PINCTRL_MUXSEL5_BANK2_PIN19_RESERVED2 0x02 762 #define HW_PINCTRL_MUXSEL5_BANK2_PIN19_GPIO 0x03 763 764 /* Pin 103, EMI_A09 pin function selection */ 765 #define HW_PINCTRL_MUXSEL5_BANK2_PIN18_EMI_ADDR09 0x00 766 #define HW_PINCTRL_MUXSEL5_BANK2_PIN18_RESERVED1 0x01 767 #define HW_PINCTRL_MUXSEL5_BANK2_PIN18_RESERVED2 0x02 768 #define HW_PINCTRL_MUXSEL5_BANK2_PIN18_GPIO 0x03 769 770 /* Pin 106, EMI_A08 pin function selection */ 771 #define HW_PINCTRL_MUXSEL5_BANK2_PIN17_EMI_ADDR08 0x00 772 #define HW_PINCTRL_MUXSEL5_BANK2_PIN17_RESERVED1 0x01 773 #define HW_PINCTRL_MUXSEL5_BANK2_PIN17_RESERVED2 0x02 774 #define HW_PINCTRL_MUXSEL5_BANK2_PIN17_GPIO 0x03 775 776 /* Pin 105, EMI_A07 pin function selection */ 777 #define HW_PINCTRL_MUXSEL5_BANK2_PIN16_EMI_ADDR07 0x00 778 #define HW_PINCTRL_MUXSEL5_BANK2_PIN16_RESERVED1 0x01 779 #define HW_PINCTRL_MUXSEL5_BANK2_PIN16_RESERVED2 0x02 780 #define HW_PINCTRL_MUXSEL5_BANK2_PIN16_GPIO 0x03 781 782 /* 783 * PINCTRL Pin Mux Select Register 6. 784 */ 785 #define HW_PINCTRL_MUXSEL6 0x160 786 #define HW_PINCTRL_MUXSEL6_SET 0x164 787 #define HW_PINCTRL_MUXSEL6_CLR 0x168 788 #define HW_PINCTRL_MUXSEL6_TOG 0x16C 789 790 #define HW_PINCTRL_MUXSEL6_BANK3_PIN15 __BITS(31,30) 791 #define HW_PINCTRL_MUXSEL6_BANK3_PIN14 __BITS(29,28) 792 #define HW_PINCTRL_MUXSEL6_BANK3_PIN13 __BITS(27,26) 793 #define HW_PINCTRL_MUXSEL6_BANK3_PIN12 __BITS(25,24) 794 #define HW_PINCTRL_MUXSEL6_BANK3_PIN11 __BITS(23,22) 795 #define HW_PINCTRL_MUXSEL6_BANK3_PIN10 __BITS(21,20) 796 #define HW_PINCTRL_MUXSEL6_BANK3_PIN09 __BITS(19,18) 797 #define HW_PINCTRL_MUXSEL6_BANK3_PIN08 __BITS(17,16) 798 #define HW_PINCTRL_MUXSEL6_BANK3_PIN07 __BITS(15,14) 799 #define HW_PINCTRL_MUXSEL6_BANK3_PIN06 __BITS(13,12) 800 #define HW_PINCTRL_MUXSEL6_BANK3_PIN05 __BITS(11,10) 801 #define HW_PINCTRL_MUXSEL6_BANK3_PIN04 __BITS(9,8) 802 #define HW_PINCTRL_MUXSEL6_BANK3_PIN03 __BITS(7,6) 803 #define HW_PINCTRL_MUXSEL6_BANK3_PIN02 __BITS(5,4) 804 #define HW_PINCTRL_MUXSEL6_BANK3_PIN01 __BITS(3,2) 805 #define HW_PINCTRL_MUXSEL6_BANK3_PIN00 __BITS(1,0) 806 807 /* Pin 95, EMI_D15 pin function selection */ 808 #define HW_PINCTRL_MUXSEL6_BANK3_PIN15_EMI_DATA15 0x00 809 #define HW_PINCTRL_MUXSEL6_BANK3_PIN15_RESERVED1 0x01 810 #define HW_PINCTRL_MUXSEL6_BANK3_PIN15_RESERVED2 0x02 811 #define HW_PINCTRL_MUXSEL6_BANK3_PIN15_DISABLED 0x03 812 813 /* Pin 96, EMI_D14 pin function selection */ 814 #define HW_PINCTRL_MUXSEL6_BANK3_PIN14_EMI_DATA14 0x00 815 #define HW_PINCTRL_MUXSEL6_BANK3_PIN14_RESERVED1 0x01 816 #define HW_PINCTRL_MUXSEL6_BANK3_PIN14_RESERVED2 0x02 817 #define HW_PINCTRL_MUXSEL6_BANK3_PIN14_DISABLED 0x03 818 819 /* Pin 94, EMI_D13 pin function selection */ 820 #define HW_PINCTRL_MUXSEL6_BANK3_PIN13_EMI_DATA13 0x00 821 #define HW_PINCTRL_MUXSEL6_BANK3_PIN13_RESERVED1 0x01 822 #define HW_PINCTRL_MUXSEL6_BANK3_PIN13_RESERVED2 0x02 823 #define HW_PINCTRL_MUXSEL6_BANK3_PIN13_DISABLED 0x03 824 825 /* Pin 93, EMI_D12 pin function selection */ 826 #define HW_PINCTRL_MUXSEL6_BANK3_PIN12_EMI_DATA12 0x00 827 #define HW_PINCTRL_MUXSEL6_BANK3_PIN12_RESERVED1 0x01 828 #define HW_PINCTRL_MUXSEL6_BANK3_PIN12_RESERVED2 0x02 829 #define HW_PINCTRL_MUXSEL6_BANK3_PIN12_DISABLED 0x03 830 831 /* Pin 91, EMI_D11 pin function selection */ 832 #define HW_PINCTRL_MUXSEL6_BANK3_PIN11_EMI_DATA11 0x00 833 #define HW_PINCTRL_MUXSEL6_BANK3_PIN11_RESERVED1 0x01 834 #define HW_PINCTRL_MUXSEL6_BANK3_PIN11_RESERVED2 0x02 835 #define HW_PINCTRL_MUXSEL6_BANK3_PIN11_DISABLED 0x03 836 837 /* Pin 89, EMI_D10 pin function selection */ 838 #define HW_PINCTRL_MUXSEL6_BANK3_PIN10_EMI_DATA10 0x00 839 #define HW_PINCTRL_MUXSEL6_BANK3_PIN10_RESERVED1 0x01 840 #define HW_PINCTRL_MUXSEL6_BANK3_PIN10_RESERVED2 0x02 841 #define HW_PINCTRL_MUXSEL6_BANK3_PIN10_DISABLED 0x03 842 843 /* Pin 87, EMI_D09 pin function selection */ 844 #define HW_PINCTRL_MUXSEL6_BANK3_PIN09_EMI_DATA09 0x00 845 #define HW_PINCTRL_MUXSEL6_BANK3_PIN09_RESERVED1 0x01 846 #define HW_PINCTRL_MUXSEL6_BANK3_PIN09_RESERVED2 0x02 847 #define HW_PINCTRL_MUXSEL6_BANK3_PIN09_DISABLED 0x03 848 849 /* Pin 86, EMI_D08 pin function selection */ 850 #define HW_PINCTRL_MUXSEL6_BANK3_PIN08_EMI_DATA08 0x00 851 #define HW_PINCTRL_MUXSEL6_BANK3_PIN08_RESERVED1 0x01 852 #define HW_PINCTRL_MUXSEL6_BANK3_PIN08_RESERVED2 0x02 853 #define HW_PINCTRL_MUXSEL6_BANK3_PIN08_DISABLED 0x03 854 855 /* Pin 85, EMI_D07 pin function selection */ 856 #define HW_PINCTRL_MUXSEL6_BANK3_PIN07_EMI_DATA07 0x00 857 #define HW_PINCTRL_MUXSEL6_BANK3_PIN07_RESERVED1 0x01 858 #define HW_PINCTRL_MUXSEL6_BANK3_PIN07_RESERVED2 0x02 859 #define HW_PINCTRL_MUXSEL6_BANK3_PIN07_DISABLED 0x03 860 861 /* Pin 84, EMI_D06 pin function selection */ 862 #define HW_PINCTRL_MUXSEL6_BANK3_PIN06_EMI_DATA06 0x00 863 #define HW_PINCTRL_MUXSEL6_BANK3_PIN06_RESERVED1 0x01 864 #define HW_PINCTRL_MUXSEL6_BANK3_PIN06_RESERVED2 0x02 865 #define HW_PINCTRL_MUXSEL6_BANK3_PIN06_DISABLED 0x03 866 867 /* Pin 83, EMI_D05 pin function selection */ 868 #define HW_PINCTRL_MUXSEL6_BANK3_PIN05_EMI_DATA05 0x00 869 #define HW_PINCTRL_MUXSEL6_BANK3_PIN05_RESERVED1 0x01 870 #define HW_PINCTRL_MUXSEL6_BANK3_PIN05_RESERVED2 0x02 871 #define HW_PINCTRL_MUXSEL6_BANK3_PIN05_DISABLED 0x03 872 873 /* Pin 82, EMI_D04 pin function selection */ 874 #define HW_PINCTRL_MUXSEL6_BANK3_PIN04_EMI_DATA04 0x00 875 #define HW_PINCTRL_MUXSEL6_BANK3_PIN04_RESERVED1 0x01 876 #define HW_PINCTRL_MUXSEL6_BANK3_PIN04_RESERVED2 0x02 877 #define HW_PINCTRL_MUXSEL6_BANK3_PIN04_DISABLED 0x03 878 879 /* Pin 79, EMI_D03 pin function selection */ 880 #define HW_PINCTRL_MUXSEL6_BANK3_PIN03_EMI_DATA03 0x00 881 #define HW_PINCTRL_MUXSEL6_BANK3_PIN03_RESERVED1 0x01 882 #define HW_PINCTRL_MUXSEL6_BANK3_PIN03_RESERVED2 0x02 883 #define HW_PINCTRL_MUXSEL6_BANK3_PIN03_DISABLED 0x03 884 885 /* Pin 77, EMI_D02 pin function selection */ 886 #define HW_PINCTRL_MUXSEL6_BANK3_PIN02_EMI_DATA02 0x00 887 #define HW_PINCTRL_MUXSEL6_BANK3_PIN02_RESERVED1 0x01 888 #define HW_PINCTRL_MUXSEL6_BANK3_PIN02_RESERVED2 0x02 889 #define HW_PINCTRL_MUXSEL6_BANK3_PIN02_DISABLED 0x03 890 891 /* Pin 76, EMI_D01 pin function selection */ 892 #define HW_PINCTRL_MUXSEL6_BANK3_PIN01_EMI_DATA01 0x00 893 #define HW_PINCTRL_MUXSEL6_BANK3_PIN01_RESERVED1 0x01 894 #define HW_PINCTRL_MUXSEL6_BANK3_PIN01_RESERVED2 0x02 895 #define HW_PINCTRL_MUXSEL6_BANK3_PIN01_DISABLED 0x03 896 897 /* Pin 75, EMI_D00 pin function selection */ 898 #define HW_PINCTRL_MUXSEL6_BANK3_PIN00_EMI_DATA00 0x00 899 #define HW_PINCTRL_MUXSEL6_BANK3_PIN00_RESERVED1 0x01 900 #define HW_PINCTRL_MUXSEL6_BANK3_PIN00_RESERVED2 0x02 901 #define HW_PINCTRL_MUXSEL6_BANK3_PIN00_DISABLED 0x03 902 903 /* 904 * PINCTRL Pin Mux Select Register 7. 905 */ 906 #define HW_PINCTRL_MUXSEL7 0x170 907 #define HW_PINCTRL_MUXSEL7_SET 0x174 908 #define HW_PINCTRL_MUXSEL7_CLR 0x178 909 #define HW_PINCTRL_MUXSEL7_TOG 0x17C 910 911 #define HW_PINCTRL_MUXSEL7_RSRVD0 __BITS(31,12) 912 #define HW_PINCTRL_MUXSEL7_BANK3_PIN21 __BITS(11,10) 913 #define HW_PINCTRL_MUXSEL7_BANK3_PIN20 __BITS(9,8) 914 #define HW_PINCTRL_MUXSEL7_BANK3_PIN19 __BITS(7,6) 915 #define HW_PINCTRL_MUXSEL7_BANK3_PIN18 __BITS(5,4) 916 #define HW_PINCTRL_MUXSEL7_BANK3_PIN17 __BITS(3,2) 917 #define HW_PINCTRL_MUXSEL7_BANK3_PIN16 __BITS(1,0) 918 919 /* Always write zeroes to this field */ 920 #define HW_PINCTRL_MUXSEL7_RSRVD0_ZERO 0x00 921 922 /* Pin 72, EMI_CLKN pin function selection */ 923 #define HW_PINCTRL_MUXSEL7_BANK3_PIN21_EMI_CLKN 0x00 924 #define HW_PINCTRL_MUXSEL7_BANK3_PIN21_RESERVED1 0x01 925 #define HW_PINCTRL_MUXSEL7_BANK3_PIN21_RESERVED2 0x02 926 #define HW_PINCTRL_MUXSEL7_BANK3_PIN21_DISABLED 0x03 927 928 /* Pin 70, EMI_CLK pin function selection */ 929 #define HW_PINCTRL_MUXSEL7_BANK3_PIN20_EMI_CLK 0x00 930 #define HW_PINCTRL_MUXSEL7_BANK3_PIN20_RESERVED1 0x01 931 #define HW_PINCTRL_MUXSEL7_BANK3_PIN20_RESERVED2 0x02 932 #define HW_PINCTRL_MUXSEL7_BANK3_PIN20_DISABLED 0x03 933 934 /* Pin 74, EMI_DQS1 pin function selection */ 935 #define HW_PINCTRL_MUXSEL7_BANK3_PIN19_EMI_DQS1 0x00 936 #define HW_PINCTRL_MUXSEL7_BANK3_PIN19_RESERVED1 0x01 937 #define HW_PINCTRL_MUXSEL7_BANK3_PIN19_RESERVED2 0x02 938 #define HW_PINCTRL_MUXSEL7_BANK3_PIN19_DISABLED 0x03 939 940 /* Pin 73, EMI_DQS0 pin function selection */ 941 #define HW_PINCTRL_MUXSEL7_BANK3_PIN18_EMI_DQS0 0x00 942 #define HW_PINCTRL_MUXSEL7_BANK3_PIN18_RESERVED1 0x01 943 #define HW_PINCTRL_MUXSEL7_BANK3_PIN18_RESERVED2 0x02 944 #define HW_PINCTRL_MUXSEL7_BANK3_PIN18_DISABLED 0x03 945 946 /* Pin 92, EMI_DQM1 pin function selection */ 947 #define HW_PINCTRL_MUXSEL7_BANK3_PIN17_EMI_DQM1 0x00 948 #define HW_PINCTRL_MUXSEL7_BANK3_PIN17_RESERVED1 0x01 949 #define HW_PINCTRL_MUXSEL7_BANK3_PIN17_RESERVED2 0x02 950 #define HW_PINCTRL_MUXSEL7_BANK3_PIN17_DISABLED 0x03 951 952 /* Pin 81, EMI_DQM0 pin function selection */ 953 #define HW_PINCTRL_MUXSEL7_BANK3_PIN16_EMI_DQM0 0x00 954 #define HW_PINCTRL_MUXSEL7_BANK3_PIN16_RESERVED1 0x01 955 #define HW_PINCTRL_MUXSEL7_BANK3_PIN16_RESERVED2 0x02 956 #define HW_PINCTRL_MUXSEL7_BANK3_PIN16_DISABLED 0x03 957 958 /* 959 * PINCTRL Drive Strength and Voltage Register 8. 960 */ 961 #define HW_PINCTRL_DRIVE8 0x280 962 #define HW_PINCTRL_DRIVE8_SET 0x284 963 #define HW_PINCTRL_DRIVE8_CLR 0x288 964 #define HW_PINCTRL_DRIVE8_TOG 0x28C 965 966 #define HW_PINCTRL_DRIVE8_RSRVD7 __BITS(31, 30) 967 #define HW_PINCTRL_DRIVE8_BANK2_PIN07_MA __BITS(29, 28) 968 #define HW_PINCTRL_DRIVE8_RSRVD6 __BITS(27, 26) 969 #define HW_PINCTRL_DRIVE8_BANK2_PIN06_MA __BITS(25, 24) 970 #define HW_PINCTRL_DRIVE8_RSRVD5 __BITS(23, 22) 971 #define HW_PINCTRL_DRIVE8_BANK2_PIN05_MA __BITS(21, 20) 972 #define HW_PINCTRL_DRIVE8_RSRVD4 __BITS(19, 18) 973 #define HW_PINCTRL_DRIVE8_BANK2_PIN04_MA __BITS(17, 16) 974 #define HW_PINCTRL_DRIVE8_RSRVD3 __BITS(15, 14) 975 #define HW_PINCTRL_DRIVE8_BANK2_PIN03_MA __BITS(13, 12) 976 #define HW_PINCTRL_DRIVE8_RSRVD2 __BITS(11, 10) 977 #define HW_PINCTRL_DRIVE8_BANK2_PIN02_MA __BITS(9, 8) 978 #define HW_PINCTRL_DRIVE8_RSRVD1 __BITS(7, 6) 979 #define HW_PINCTRL_DRIVE8_BANK2_PIN01_MA __BITS(5, 4) 980 #define HW_PINCTRL_DRIVE8_RSRVD0 __BITS(3, 2) 981 #define HW_PINCTRL_DRIVE8_BANK2_PIN00_MA __BITS(1, 0) 982 983 /* 984 * PINCTRL Drive Strength and Voltage Register 9. 985 */ 986 #define HW_PINCTRL_DRIVE9 0x290 987 #define HW_PINCTRL_DRIVE9_SET 0x294 988 #define HW_PINCTRL_DRIVE9_CLR 0x298 989 #define HW_PINCTRL_DRIVE9_TOG 0x29C 990 991 #define HW_PINCTRL_DRIVE9_RSRVD7 __BIT(31) 992 #define HW_PINCTRL_DRIVE9_BANK2_PIN15_V __BIT(30) 993 #define HW_PINCTRL_DRIVE9_BANK2_PIN15_MA __BITS(29, 28) 994 #define HW_PINCTRL_DRIVE9_RSRVD6 __BIT(27) 995 #define HW_PINCTRL_DRIVE9_BANK2_PIN14_V __BIT(26) 996 #define HW_PINCTRL_DRIVE9_BANK2_PIN14_MA __BITS(25, 24) 997 #define HW_PINCTRL_DRIVE9_RSRVD5 __BIT(23) 998 #define HW_PINCTRL_DRIVE9_BANK2_PIN13_V __BIT(22) 999 #define HW_PINCTRL_DRIVE9_BANK2_PIN13_MA __BITS(21, 20) 1000 #define HW_PINCTRL_DRIVE9_RSRVD4 __BIT(19) 1001 #define HW_PINCTRL_DRIVE9_BANK2_PIN12_V __BIT(18) 1002 #define HW_PINCTRL_DRIVE9_BANK2_PIN12_MA __BITS(17, 16) 1003 #define HW_PINCTRL_DRIVE9_RSRVD3 __BIT(15) 1004 #define HW_PINCTRL_DRIVE9_BANK2_PIN11_V __BIT(14) 1005 #define HW_PINCTRL_DRIVE9_BANK2_PIN11_MA __BITS(13, 12) 1006 #define HW_PINCTRL_DRIVE9_RSRVD2 __BIT(11) 1007 #define HW_PINCTRL_DRIVE9_BANK2_PIN10_V __BIT(10) 1008 #define HW_PINCTRL_DRIVE9_BANK2_PIN10_MA __BITS(9, 8) 1009 #define HW_PINCTRL_DRIVE9_RSRVD1 __BIT(7) 1010 #define HW_PINCTRL_DRIVE9_BANK2_PIN09_V __BIT(6) 1011 #define HW_PINCTRL_DRIVE9_BANK2_PIN09_MA __BITS(5, 4) 1012 #define HW_PINCTRL_DRIVE9_RSRVD0 __BITS(3, 2) 1013 #define HW_PINCTRL_DRIVE9_BANK2_PIN08_MA __BITS(1, 0) 1014 1015 /* 1016 * PINCTRL Drive Strength and Voltage Register 10. 1017 */ 1018 #define HW_PINCTRL_DRIVE10 0x2a0 1019 #define HW_PINCTRL_DRIVE10_SET 0x2a4 1020 #define HW_PINCTRL_DRIVE10_CLR 0x2a8 1021 #define HW_PINCTRL_DRIVE10_TOG 0x2ac 1022 1023 #define HW_PINCTRL_DRIVE10_RSRVD7 __BIT(31) 1024 #define HW_PINCTRL_DRIVE10_BANK2_PIN23_V __BIT(30) 1025 #define HW_PINCTRL_DRIVE10_BANK2_PIN23_MA __BITS(29, 28) 1026 #define HW_PINCTRL_DRIVE10_RSRVD6 __BIT(27) 1027 #define HW_PINCTRL_DRIVE10_BANK2_PIN22_V __BIT(26) 1028 #define HW_PINCTRL_DRIVE10_BANK2_PIN22_MA __BITS(25, 24) 1029 #define HW_PINCTRL_DRIVE10_RSRVD5 __BIT(23) 1030 #define HW_PINCTRL_DRIVE10_BANK2_PIN21_V __BIT(22) 1031 #define HW_PINCTRL_DRIVE10_BANK2_PIN21_MA __BITS(21, 20) 1032 #define HW_PINCTRL_DRIVE10_RSRVD4 __BIT(19) 1033 #define HW_PINCTRL_DRIVE10_BANK2_PIN20_V __BIT(18) 1034 #define HW_PINCTRL_DRIVE10_BANK2_PIN20_MA __BITS(17, 16) 1035 #define HW_PINCTRL_DRIVE10_RSRVD3 __BIT(15) 1036 #define HW_PINCTRL_DRIVE10_BANK2_PIN19_V __BIT(14) 1037 #define HW_PINCTRL_DRIVE10_BANK2_PIN19_MA __BITS(13, 12) 1038 #define HW_PINCTRL_DRIVE10_RSRVD2 __BIT(11) 1039 #define HW_PINCTRL_DRIVE10_BANK2_PIN18_V __BIT(10) 1040 #define HW_PINCTRL_DRIVE10_BANK2_PIN18_MA __BITS(9, 8) 1041 #define HW_PINCTRL_DRIVE10_RSRVD1 __BIT(7) 1042 #define HW_PINCTRL_DRIVE10_BANK2_PIN17_V __BIT(6) 1043 #define HW_PINCTRL_DRIVE10_BANK2_PIN17_MA __BITS(5, 4) 1044 #define HW_PINCTRL_DRIVE10_RSRVD0 __BIT(3) 1045 #define HW_PINCTRL_DRIVE10_BANK2_PIN16_V __BIT(2) 1046 #define HW_PINCTRL_DRIVE10_BANK2_PIN16_MA __BITS(1, 0) 1047 1048 /* 1049 * PINCTRL Drive Strength and Voltage Register 11. 1050 */ 1051 #define HW_PINCTRL_DRIVE11 0x2b0 1052 #define HW_PINCTRL_DRIVE11_SET 0x2b4 1053 #define HW_PINCTRL_DRIVE11_CLR 0x2b8 1054 #define HW_PINCTRL_DRIVE11_TOG 0x2bC 1055 1056 #define HW_PINCTRL_DRIVE11_RSRVD7 __BIT(31) 1057 #define HW_PINCTRL_DRIVE11_BANK2_PIN31_V __BIT(30) 1058 #define HW_PINCTRL_DRIVE11_BANK2_PIN31_MA __BITS(29, 28) 1059 #define HW_PINCTRL_DRIVE11_RSRVD6 __BIT(27) 1060 #define HW_PINCTRL_DRIVE11_BANK2_PIN30_V __BIT(26) 1061 #define HW_PINCTRL_DRIVE11_BANK2_PIN30_MA __BITS(25, 24) 1062 #define HW_PINCTRL_DRIVE11_RSRVD5 __BIT(23) 1063 #define HW_PINCTRL_DRIVE11_BANK2_PIN29_V __BIT(22) 1064 #define HW_PINCTRL_DRIVE11_BANK2_PIN29_MA __BITS(21, 20) 1065 #define HW_PINCTRL_DRIVE11_RSRVD4 __BITS(19, 18) 1066 #define HW_PINCTRL_DRIVE11_BANK2_PIN28_MA __BIT(17, 16) 1067 #define HW_PINCTRL_DRIVE11_RSRVD3 __BITS(15, 14) 1068 #define HW_PINCTRL_DRIVE11_BANK2_PIN27_MA __BITS(13, 12) 1069 #define HW_PINCTRL_DRIVE11_RSRVD2 __BIT(11) 1070 #define HW_PINCTRL_DRIVE11_BANK2_PIN26_V __BIT(10) 1071 #define HW_PINCTRL_DRIVE11_BANK2_PIN26_MA __BITS(9, 8) 1072 #define HW_PINCTRL_DRIVE11_RSRVD1 __BIT(7) 1073 #define HW_PINCTRL_DRIVE11_BANK2_PIN25_V __BIT(6) 1074 #define HW_PINCTRL_DRIVE11_BANK2_PIN25_MA __BITS(5, 4) 1075 #define HW_PINCTRL_DRIVE11_RSRVD0 __BIT(3) 1076 #define HW_PINCTRL_DRIVE11_BANK2_PIN24_V __BIT(2) 1077 #define HW_PINCTRL_DRIVE11_BANK2_PIN24_MA __BITS(1, 0) 1078 1079 /* 1080 * PINCTRL Drive Strength and Voltage Register 12. 1081 */ 1082 #define HW_PINCTRL_DRIVE12 0x2c0 1083 #define HW_PINCTRL_DRIVE12_SET 0x2c4 1084 #define HW_PINCTRL_DRIVE12_CLR 0x2c8 1085 #define HW_PINCTRL_DRIVE12_TOG 0x2cC 1086 1087 #define HW_PINCTRL_DRIVE12_RSRVD7 __BIT(31) 1088 #define HW_PINCTRL_DRIVE12_BANK3_PIN07_V __BIT(30) 1089 #define HW_PINCTRL_DRIVE12_BANK3_PIN07_MA __BITS(29, 28) 1090 #define HW_PINCTRL_DRIVE12_RSRVD6 __BIT(27) 1091 #define HW_PINCTRL_DRIVE12_BANK3_PIN06_V __BIT(26) 1092 #define HW_PINCTRL_DRIVE12_BANK3_PIN06_MA __BITS(25, 24) 1093 #define HW_PINCTRL_DRIVE12_RSRVD5 __BIT(23) 1094 #define HW_PINCTRL_DRIVE12_BANK3_PIN05_V __BIT(22) 1095 #define HW_PINCTRL_DRIVE12_BANK3_PIN05_MA __BITS(21, 20) 1096 #define HW_PINCTRL_DRIVE12_RSRVD4 __BIT(19) 1097 #define HW_PINCTRL_DRIVE12_BANK3_PIN04_V __BIT(18) 1098 #define HW_PINCTRL_DRIVE12_BANK3_PIN04_MA __BITS(17, 15) 1099 #define HW_PINCTRL_DRIVE12_RSRVD3 __BIT(15) 1100 #define HW_PINCTRL_DRIVE12_BANK3_PIN03_V __BIT(14) 1101 #define HW_PINCTRL_DRIVE12_BANK3_PIN03_MA __BITS(13, 12) 1102 #define HW_PINCTRL_DRIVE12_RSRVD2 __BIT(11) 1103 #define HW_PINCTRL_DRIVE12_BANK3_PIN02_V __BIT(10) 1104 #define HW_PINCTRL_DRIVE12_BANK3_PIN02_MA __BITS(9, 8) 1105 #define HW_PINCTRL_DRIVE12_RSRVD1 __BIT(7) 1106 #define HW_PINCTRL_DRIVE12_BANK3_PIN01_V __BIT(6) 1107 #define HW_PINCTRL_DRIVE12_BANK3_PIN01_MA __BITS(5, 4) 1108 #define HW_PINCTRL_DRIVE12_RSRVD0 __BIT(3) 1109 #define HW_PINCTRL_DRIVE12_BANK3_PIN00_V __BIT(2) 1110 #define HW_PINCTRL_DRIVE12_BANK3_PIN00_MA __BITS(1, 0) 1111 1112 /* 1113 * PINCTRL Drive Strength and Voltage Register 13. 1114 */ 1115 #define HW_PINCTRL_DRIVE13 0x2d0 1116 #define HW_PINCTRL_DRIVE13_SET 0x2d4 1117 #define HW_PINCTRL_DRIVE13_CLR 0x2d8 1118 #define HW_PINCTRL_DRIVE13_TOG 0x2dc 1119 1120 #define HW_PINCTRL_DRIVE13_RSRVD7 __BIT(31) 1121 #define HW_PINCTRL_DRIVE13_BANK3_PIN15_V __BIT(30) 1122 #define HW_PINCTRL_DRIVE13_BANK3_PIN15_MA __BITS(29, 28) 1123 #define HW_PINCTRL_DRIVE13_RSRVD6 __BIT(27) 1124 #define HW_PINCTRL_DRIVE13_BANK3_PIN14_V __BIT(26) 1125 #define HW_PINCTRL_DRIVE13_BANK3_PIN14_MA __BITS(25, 24) 1126 #define HW_PINCTRL_DRIVE13_RSRVD5 __BIT(23) 1127 #define HW_PINCTRL_DRIVE13_BANK3_PIN13_V __BIT(22) 1128 #define HW_PINCTRL_DRIVE13_BANK3_PIN13_MA __BITS(21, 20) 1129 #define HW_PINCTRL_DRIVE13_RSRVD4 __BIT(19) 1130 #define HW_PINCTRL_DRIVE13_BANK3_PIN12_V __BIT(18) 1131 #define HW_PINCTRL_DRIVE13_BANK3_PIN12_MA __BITS(17, 16) 1132 #define HW_PINCTRL_DRIVE13_RSRVD3 __BIT(15) 1133 #define HW_PINCTRL_DRIVE13_BANK3_PIN11_V __BIT(14) 1134 #define HW_PINCTRL_DRIVE13_BANK3_PIN11_MA __BITS(13, 12) 1135 #define HW_PINCTRL_DRIVE13_RSRVD2 __BIT(11) 1136 #define HW_PINCTRL_DRIVE13_BANK3_PIN10_V __BIT(10) 1137 #define HW_PINCTRL_DRIVE13_BANK3_PIN10_MA __BITS(9, 8) 1138 #define HW_PINCTRL_DRIVE13_RSRVD1 __BIT(7) 1139 #define HW_PINCTRL_DRIVE13_BANK3_PIN09_V __BIT(6) 1140 #define HW_PINCTRL_DRIVE13_BANK3_PIN09_MA __BITS(5, 4) 1141 #define HW_PINCTRL_DRIVE13_RSRVD0 __BIT(3) 1142 #define HW_PINCTRL_DRIVE13_BANK3_PIN08_V __BIT(2) 1143 #define HW_PINCTRL_DRIVE13_BANK3_PIN08_MA __BITS(1, 0) 1144 1145 /* 1146 * PINCTRL Drive Strength and Voltage Register 14. 1147 */ 1148 #define HW_PINCTRL_DRIVE14 0x2e0 1149 #define HW_PINCTRL_DRIVE14_SET 0x2e4 1150 #define HW_PINCTRL_DRIVE14_CLR 0x2e8 1151 #define HW_PINCTRL_DRIVE14_TOG 0x2ec 1152 1153 #define HW_PINCTRL_DRIVE14_RSRVD6 __BITS(31, 24) 1154 #define HW_PINCTRL_DRIVE14_RSRVD5 __BIT(23) 1155 #define HW_PINCTRL_DRIVE14_BANK3_PIN21_V __BIT(22) 1156 #define HW_PINCTRL_DRIVE14_BANK3_PIN21_MA __BITS(21, 20) 1157 #define HW_PINCTRL_DRIVE14_RSRVD4 __BIT(19) 1158 #define HW_PINCTRL_DRIVE14_BANK3_PIN20_V __BIT(18) 1159 #define HW_PINCTRL_DRIVE14_BANK3_PIN20_MA __BITS(17, 16) 1160 #define HW_PINCTRL_DRIVE14_RSRVD3 __BIT(15) 1161 #define HW_PINCTRL_DRIVE14_BANK3_PIN19_V __BIT(14) 1162 #define HW_PINCTRL_DRIVE14_BANK3_PIN19_MA __BITS(13, 12) 1163 #define HW_PINCTRL_DRIVE14_RSRVD2 __BIT(11) 1164 #define HW_PINCTRL_DRIVE14_BANK3_PIN18_V __BIT(10) 1165 #define HW_PINCTRL_DRIVE14_BANK3_PIN18_MA __BITS(9, 8) 1166 #define HW_PINCTRL_DRIVE14_RSRVD1 __BIT(7) 1167 #define HW_PINCTRL_DRIVE14_BANK3_PIN17_V __BIT(6) 1168 #define HW_PINCTRL_DRIVE14_BANK3_PIN17_MA __BITS(5, 4) 1169 #define HW_PINCTRL_DRIVE14_RSRVD0 __BIT(3) 1170 #define HW_PINCTRL_DRIVE14_BANK3_PIN16_V __BIT(2) 1171 #define HW_PINCTRL_DRIVE14_BANK3_PIN16_MA __BITS(1, 0) 1172 1173 /* 1174 * PINCTRL Bank 2 Pull Up Resistor Enable Register. 1175 */ 1176 #define HW_PINCTRL_PULL2 0x420 1177 #define HW_PINCTRL_PULL2_SET 0x424 1178 #define HW_PINCTRL_PULL2_CLR 0x428 1179 #define HW_PINCTRL_PULL2_TOG 0x42C 1180 1181 #define HW_PINCTRL_PULL2_RSRVD2 __BITS(31, 29) 1182 #define HW_PINCTRL_PULL2_BANK2_PIN28 __BIT(28) 1183 #define HW_PINCTRL_PULL2_BANK2_PIN27 __BIT(27) 1184 #define HW_PINCTRL_PULL2_RSRVD1 __BITS(26, 9) 1185 #define HW_PINCTRL_PULL2_BANK2_PIN08 __BIT(8) 1186 #define HW_PINCTRL_PULL2_RSRVD0 __BITS(7, 6) 1187 #define HW_PINCTRL_PULL2_BANK2_PIN05 __BIT(5) 1188 #define HW_PINCTRL_PULL2_BANK2_PIN04 __BIT(4) 1189 #define HW_PINCTRL_PULL2_BANK2_PIN03 __BIT(3) 1190 #define HW_PINCTRL_PULL2_BANK2_PIN02 __BIT(2) 1191 #define HW_PINCTRL_PULL2_BANK2_PIN01 __BIT(1) 1192 #define HW_PINCTRL_PULL2_BANK2_PIN00 __BIT(0) 1193 1194 /* 1195 * PINCTRL Bank 3 Pad Keeper Disable Register. 1196 */ 1197 #define HW_PINCTRL_PULL3 0x430 1198 #define HW_PINCTRL_PULL3_SET 0x434 1199 #define HW_PINCTRL_PULL3_CLR 0x438 1200 #define HW_PINCTRL_PULL3_TOG 0x43C 1201 1202 #define HW_PINCTRL_PULL3_RSRVD0 __BITS(31, 18) 1203 #define HW_PINCTRL_PULL3_BANK3_PIN17 __BIT(17) 1204 #define HW_PINCTRL_PULL3_BANK3_PIN16 __BIT(16) 1205 #define HW_PINCTRL_PULL3_BANK3_PIN15 __BIT(15) 1206 #define HW_PINCTRL_PULL3_BANK3_PIN14 __BIT(14) 1207 #define HW_PINCTRL_PULL3_BANK3_PIN13 __BIT(13) 1208 #define HW_PINCTRL_PULL3_BANK3_PIN12 __BIT(12) 1209 #define HW_PINCTRL_PULL3_BANK3_PIN11 __BIT(11) 1210 #define HW_PINCTRL_PULL3_BANK3_PIN10 __BIT(10) 1211 #define HW_PINCTRL_PULL3_BANK3_PIN09 __BIT(9) 1212 #define HW_PINCTRL_PULL3_BANK3_PIN08 __BIT(8) 1213 #define HW_PINCTRL_PULL3_BANK3_PIN07 __BIT(7) 1214 #define HW_PINCTRL_PULL3_BANK3_PIN06 __BIT(6) 1215 #define HW_PINCTRL_PULL3_BANK3_PIN05 __BIT(5) 1216 #define HW_PINCTRL_PULL3_BANK3_PIN04 __BIT(4) 1217 #define HW_PINCTRL_PULL3_BANK3_PIN03 __BIT(3) 1218 #define HW_PINCTRL_PULL3_BANK3_PIN02 __BIT(2) 1219 #define HW_PINCTRL_PULL3_BANK3_PIN01 __BIT(1) 1220 #define HW_PINCTRL_PULL3_BANK3_PIN00 __BIT(0) 1221 1222 #endif /* !_ARM_IMX_IMX23_PINCTRLREG_H_ */ 1223
Indexes created Wed Oct 15 16:09:53 GMT 2025