imx23_ssp.c revision 1.2.2.2
1 1.2.2.2 yamt /* $Id: imx23_ssp.c,v 1.2.2.2 2013/01/16 05:32:47 yamt Exp $ */ 2 1.2.2.2 yamt 3 1.2.2.2 yamt /* 4 1.2.2.2 yamt * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 1.2.2.2 yamt * All rights reserved. 6 1.2.2.2 yamt * 7 1.2.2.2 yamt * This code is derived from software contributed to The NetBSD Foundation 8 1.2.2.2 yamt * by Petri Laakso. 9 1.2.2.2 yamt * 10 1.2.2.2 yamt * Redistribution and use in source and binary forms, with or without 11 1.2.2.2 yamt * modification, are permitted provided that the following conditions 12 1.2.2.2 yamt * are met: 13 1.2.2.2 yamt * 1. Redistributions of source code must retain the above copyright 14 1.2.2.2 yamt * notice, this list of conditions and the following disclaimer. 15 1.2.2.2 yamt * 2. Redistributions in binary form must reproduce the above copyright 16 1.2.2.2 yamt * notice, this list of conditions and the following disclaimer in the 17 1.2.2.2 yamt * documentation and/or other materials provided with the distribution. 18 1.2.2.2 yamt * 19 1.2.2.2 yamt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.2.2.2 yamt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.2.2.2 yamt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.2.2.2 yamt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.2.2.2 yamt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.2.2.2 yamt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.2.2.2 yamt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.2.2.2 yamt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.2.2.2 yamt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.2.2.2 yamt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.2.2.2 yamt * POSSIBILITY OF SUCH DAMAGE. 30 1.2.2.2 yamt */ 31 1.2.2.2 yamt 32 1.2.2.2 yamt #include <sys/param.h> 33 1.2.2.2 yamt #include <sys/types.h> 34 1.2.2.2 yamt #include <sys/bus.h> 35 1.2.2.2 yamt #include <sys/cdefs.h> 36 1.2.2.2 yamt #include <sys/cpu.h> 37 1.2.2.2 yamt #include <sys/device.h> 38 1.2.2.2 yamt #include <sys/errno.h> 39 1.2.2.2 yamt #include <sys/systm.h> 40 1.2.2.2 yamt 41 1.2.2.2 yamt #include <arm/pic/picvar.h> 42 1.2.2.2 yamt 43 1.2.2.2 yamt #include <arm/imx/imx23_apbdma.h> 44 1.2.2.2 yamt #include <arm/imx/imx23_icollreg.h> 45 1.2.2.2 yamt #include <arm/imx/imx23_sspreg.h> 46 1.2.2.2 yamt #include <arm/imx/imx23var.h> 47 1.2.2.2 yamt 48 1.2.2.2 yamt #include <dev/sdmmc/sdmmcchip.h> 49 1.2.2.2 yamt #include <dev/sdmmc/sdmmcreg.h> 50 1.2.2.2 yamt #include <dev/sdmmc/sdmmcvar.h> 51 1.2.2.2 yamt 52 1.2.2.2 yamt /* 53 1.2.2.2 yamt * SD/MMC host controller driver for i.MX233. 54 1.2.2.2 yamt */ 55 1.2.2.2 yamt 56 1.2.2.2 yamt struct issp_softc { 57 1.2.2.2 yamt device_t sc_dev; 58 1.2.2.2 yamt bus_space_tag_t sc_iot; 59 1.2.2.2 yamt bus_space_handle_t sc_hdl; 60 1.2.2.2 yamt device_t sc_sdmmc; 61 1.2.2.2 yamt device_t dmac; 62 1.2.2.2 yamt }; 63 1.2.2.2 yamt 64 1.2.2.2 yamt static int issp_match(device_t, cfdata_t, void *); 65 1.2.2.2 yamt static void issp_attach(device_t, device_t, void *); 66 1.2.2.2 yamt static int issp_activate(device_t, enum devact); 67 1.2.2.2 yamt 68 1.2.2.2 yamt /* sdmmc chip function prototypes. */ 69 1.2.2.2 yamt static int issp_host_reset(sdmmc_chipset_handle_t); 70 1.2.2.2 yamt static uint32_t issp_host_ocr(sdmmc_chipset_handle_t); 71 1.2.2.2 yamt static int issp_host_maxblklen(sdmmc_chipset_handle_t); 72 1.2.2.2 yamt static int issp_card_detect(sdmmc_chipset_handle_t); 73 1.2.2.2 yamt static int issp_write_protect(sdmmc_chipset_handle_t); 74 1.2.2.2 yamt static int issp_bus_power(sdmmc_chipset_handle_t, uint32_t); 75 1.2.2.2 yamt static int issp_bus_clock(sdmmc_chipset_handle_t, int); 76 1.2.2.2 yamt static int issp_bus_width(sdmmc_chipset_handle_t, int); 77 1.2.2.2 yamt static int issp_bus_rod(sdmmc_chipset_handle_t, int); 78 1.2.2.2 yamt static void issp_exec_command(sdmmc_chipset_handle_t, 79 1.2.2.2 yamt struct sdmmc_command *); 80 1.2.2.2 yamt static void issp_card_enable_intr(sdmmc_chipset_handle_t, int); 81 1.2.2.2 yamt static void issp_card_intr_ack(sdmmc_chipset_handle_t); 82 1.2.2.2 yamt 83 1.2.2.2 yamt /* Used from the above callbacks. */ 84 1.2.2.2 yamt static void issp_reset(struct issp_softc *); 85 1.2.2.2 yamt static void issp_init(struct issp_softc *); 86 1.2.2.2 yamt static uint32_t issp_set_sck(struct issp_softc *, uint32_t target); 87 1.2.2.2 yamt 88 1.2.2.2 yamt #define SSP_SOFT_RST_LOOP 455 /* At least 1 us ... */ 89 1.2.2.2 yamt 90 1.2.2.2 yamt CFATTACH_DECL3_NEW(ssp, 91 1.2.2.2 yamt sizeof(struct issp_softc), 92 1.2.2.2 yamt issp_match, 93 1.2.2.2 yamt issp_attach, 94 1.2.2.2 yamt NULL, 95 1.2.2.2 yamt issp_activate, 96 1.2.2.2 yamt NULL, 97 1.2.2.2 yamt NULL, 98 1.2.2.2 yamt 0); 99 1.2.2.2 yamt 100 1.2.2.2 yamt static struct sdmmc_chip_functions issp_functions = { 101 1.2.2.2 yamt .host_reset = issp_host_reset, 102 1.2.2.2 yamt .host_ocr = issp_host_ocr, 103 1.2.2.2 yamt .host_maxblklen = issp_host_maxblklen, 104 1.2.2.2 yamt .card_detect = issp_card_detect, 105 1.2.2.2 yamt .write_protect = issp_write_protect, 106 1.2.2.2 yamt .bus_power = issp_bus_power, 107 1.2.2.2 yamt .bus_clock = issp_bus_clock, 108 1.2.2.2 yamt .bus_width = issp_bus_width, 109 1.2.2.2 yamt .bus_rod = issp_bus_rod, 110 1.2.2.2 yamt .exec_command = issp_exec_command, 111 1.2.2.2 yamt .card_enable_intr = issp_card_enable_intr, 112 1.2.2.2 yamt .card_intr_ack = issp_card_intr_ack 113 1.2.2.2 yamt }; 114 1.2.2.2 yamt 115 1.2.2.2 yamt #define SSP_READ(sc, reg) \ 116 1.2.2.2 yamt bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg)) 117 1.2.2.2 yamt #define SSP_WRITE(sc, reg, val) \ 118 1.2.2.2 yamt bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val)) 119 1.2.2.2 yamt 120 1.2.2.2 yamt #define SSP_CLK 96000000 /* CLK_SSP from PLL is 96 MHz */ 121 1.2.2.2 yamt #define SSP_CLK_MIN 2 /* 2 kHz */ 122 1.2.2.2 yamt #define SSP_CLK_MAX 48000 /* 48 MHz */ 123 1.2.2.2 yamt /* SSP_CMD_TIMEOUT is calculated as (1.0/SSP_SCK)*(SSP_CMD_TIMEOUT*4096) */ 124 1.2.2.2 yamt #define SSP_CMD_TIMEOUT 0xffff /* 2.8 seconds. */ 125 1.2.2.2 yamt #define SSP_STATUS_ERR (HW_SSP_STATUS_RESP_CRC_ERR | \ 126 1.2.2.2 yamt HW_SSP_STATUS_RESP_ERR | \ 127 1.2.2.2 yamt HW_SSP_STATUS_RESP_TIMEOUT | \ 128 1.2.2.2 yamt HW_SSP_STATUS_DATA_CRC_ERR | \ 129 1.2.2.2 yamt HW_SSP_STATUS_TIMEOUT) 130 1.2.2.2 yamt 131 1.2.2.2 yamt static int 132 1.2.2.2 yamt issp_match(device_t parent, cfdata_t match, void *aux) 133 1.2.2.2 yamt { 134 1.2.2.2 yamt struct apb_attach_args *aa = aux; 135 1.2.2.2 yamt 136 1.2.2.2 yamt if ((aa->aa_addr == HW_SSP1_BASE) && (aa->aa_size == HW_SSP1_SIZE)) 137 1.2.2.2 yamt return 1; 138 1.2.2.2 yamt 139 1.2.2.2 yamt if ((aa->aa_addr == HW_SSP2_BASE) && (aa->aa_size == HW_SSP2_SIZE)) 140 1.2.2.2 yamt return 1; 141 1.2.2.2 yamt 142 1.2.2.2 yamt return 0; 143 1.2.2.2 yamt } 144 1.2.2.2 yamt 145 1.2.2.2 yamt static void 146 1.2.2.2 yamt issp_attach(device_t parent, device_t self, void *aux) 147 1.2.2.2 yamt { 148 1.2.2.2 yamt static int issp_attached = 0; 149 1.2.2.2 yamt struct issp_softc *sc = device_private(self); 150 1.2.2.2 yamt struct apb_softc *scp = device_private(parent); 151 1.2.2.2 yamt struct apb_attach_args *aa = aux; 152 1.2.2.2 yamt struct sdmmcbus_attach_args saa; 153 1.2.2.2 yamt 154 1.2.2.2 yamt 155 1.2.2.2 yamt if (issp_attached) 156 1.2.2.2 yamt return; 157 1.2.2.2 yamt 158 1.2.2.2 yamt //XXX: 159 1.2.2.2 yamt if (scp == NULL) 160 1.2.2.2 yamt printf("ISSP_ATTACH: scp == NULL\n"); 161 1.2.2.2 yamt if (scp->dmac == NULL) 162 1.2.2.2 yamt printf("ISSP_ATTACH: scp->dmac == NULL\n"); 163 1.2.2.2 yamt 164 1.2.2.2 yamt sc->sc_dev = self; 165 1.2.2.2 yamt sc->sc_iot = aa->aa_iot; 166 1.2.2.2 yamt sc->dmac = scp->dmac; 167 1.2.2.2 yamt 168 1.2.2.2 yamt if (bus_space_map(sc->sc_iot, 169 1.2.2.2 yamt aa->aa_addr, aa->aa_size, 0, &(sc->sc_hdl))) { 170 1.2.2.2 yamt aprint_error_dev(sc->sc_dev, "unable to map bus space\n"); 171 1.2.2.2 yamt return; 172 1.2.2.2 yamt } 173 1.2.2.2 yamt 174 1.2.2.2 yamt issp_reset(sc); 175 1.2.2.2 yamt issp_init(sc); 176 1.2.2.2 yamt 177 1.2.2.2 yamt uint32_t issp_vers = SSP_READ(sc, HW_SSP_VERSION); 178 1.2.2.2 yamt aprint_normal(": SSP Block v%" __PRIuBIT ".%" __PRIuBIT "\n", 179 1.2.2.2 yamt __SHIFTOUT(issp_vers, HW_SSP_VERSION_MAJOR), 180 1.2.2.2 yamt __SHIFTOUT(issp_vers, HW_SSP_VERSION_MINOR)); 181 1.2.2.2 yamt 182 1.2.2.2 yamt saa.saa_busname = "sdmmc"; 183 1.2.2.2 yamt saa.saa_sct = &issp_functions; 184 1.2.2.2 yamt saa.saa_spi_sct = NULL; 185 1.2.2.2 yamt saa.saa_sch = sc; 186 1.2.2.2 yamt saa.saa_dmat = aa->aa_dmat; 187 1.2.2.2 yamt saa.saa_clkmin = SSP_CLK_MIN; 188 1.2.2.2 yamt saa.saa_clkmax = SSP_CLK_MAX; 189 1.2.2.2 yamt saa.saa_caps = SMC_CAPS_4BIT_MODE | SMC_CAPS_DMA; 190 1.2.2.2 yamt 191 1.2.2.2 yamt sc->sc_sdmmc = config_found(sc->sc_dev, &saa, NULL); 192 1.2.2.2 yamt if (sc->sc_sdmmc == NULL) { 193 1.2.2.2 yamt aprint_error_dev(sc->sc_dev, "unable to attach sdmmc\n"); 194 1.2.2.2 yamt return; 195 1.2.2.2 yamt } 196 1.2.2.2 yamt 197 1.2.2.2 yamt issp_attached = 1; 198 1.2.2.2 yamt 199 1.2.2.2 yamt return; 200 1.2.2.2 yamt } 201 1.2.2.2 yamt 202 1.2.2.2 yamt static int 203 1.2.2.2 yamt issp_activate(device_t self, enum devact act) 204 1.2.2.2 yamt { 205 1.2.2.2 yamt return EOPNOTSUPP; 206 1.2.2.2 yamt } 207 1.2.2.2 yamt 208 1.2.2.2 yamt /* 209 1.2.2.2 yamt * sdmmc chip functions. 210 1.2.2.2 yamt */ 211 1.2.2.2 yamt static int 212 1.2.2.2 yamt issp_host_reset(sdmmc_chipset_handle_t sch) 213 1.2.2.2 yamt { 214 1.2.2.2 yamt struct issp_softc *sc = sch; 215 1.2.2.2 yamt 216 1.2.2.2 yamt issp_reset(sc); 217 1.2.2.2 yamt 218 1.2.2.2 yamt return 0; 219 1.2.2.2 yamt } 220 1.2.2.2 yamt 221 1.2.2.2 yamt static uint32_t 222 1.2.2.2 yamt issp_host_ocr(sdmmc_chipset_handle_t sch) 223 1.2.2.2 yamt { 224 1.2.2.2 yamt /* SSP supports at least 3.2-3.3v */ 225 1.2.2.2 yamt return MMC_OCR_3_2V_3_3V; 226 1.2.2.2 yamt } 227 1.2.2.2 yamt 228 1.2.2.2 yamt static int 229 1.2.2.2 yamt issp_host_maxblklen(sdmmc_chipset_handle_t sch) 230 1.2.2.2 yamt { 231 1.2.2.2 yamt /* XXX: This value was made up. */ 232 1.2.2.2 yamt return 512; 233 1.2.2.2 yamt } 234 1.2.2.2 yamt 235 1.2.2.2 yamt /* 236 1.2.2.2 yamt * Called at the beginning of sdmmc_task_thread to detect the presence 237 1.2.2.2 yamt * of the SD card. 238 1.2.2.2 yamt */ 239 1.2.2.2 yamt static int 240 1.2.2.2 yamt issp_card_detect(sdmmc_chipset_handle_t sch) 241 1.2.2.2 yamt { 242 1.2.2.2 yamt /* struct issp_softc *sc = sch; 243 1.2.2.2 yamt * 244 1.2.2.2 yamt * In the perfect world I'll just: 245 1.2.2.2 yamt * return SSP_READ(sc, HW_SSP_STATUS) & HW_SSP_STATUS_CARD_DETECT; 246 1.2.2.2 yamt * and call it a day. 247 1.2.2.2 yamt * 248 1.2.2.2 yamt * But on i.MX233 OLinuXino MAXI, SSP1_DETECT is not used for the SD 249 1.2.2.2 yamt * card detection but SSP1_DATA3 is, as Tsvetan put it: 250 1.2.2.2 yamt * 251 1.2.2.2 yamt * < Tsvetan> if you want to know if SD card is inserted watch 252 1.2.2.2 yamt * CD/DAT3/CS port 253 1.2.2.2 yamt * < Tsvetan> without card there is R20 weak pulldown 254 1.2.2.2 yamt * < Tsvetan> all cards have 40K pullup to this pin 255 1.2.2.2 yamt * < Tsvetan> so when card is inserted you will read it high 256 1.2.2.2 yamt * 257 1.2.2.2 yamt * Which means I should to do something like this: 258 1.2.2.2 yamt * #if BOARDTYPE == MAXI (Possibly MINI & MICRO) 259 1.2.2.2 yamt * return GPIO_READ(PIN_125) & PIN_125 260 1.2.2.2 yamt * #else 261 1.2.2.2 yamt * return SSP_READ(sc, STATUS) & CARD_DETECT; 262 1.2.2.2 yamt * #endif 263 1.2.2.2 yamt * Until GPIO functionality is not present I am just going to */ 264 1.2.2.2 yamt 265 1.2.2.2 yamt return 1; 266 1.2.2.2 yamt } 267 1.2.2.2 yamt 268 1.2.2.2 yamt static int 269 1.2.2.2 yamt issp_write_protect(sdmmc_chipset_handle_t sch) 270 1.2.2.2 yamt { 271 1.2.2.2 yamt /* The device is not write protected. */ 272 1.2.2.2 yamt return 0; 273 1.2.2.2 yamt } 274 1.2.2.2 yamt 275 1.2.2.2 yamt static int 276 1.2.2.2 yamt issp_bus_power(sdmmc_chipset_handle_t sch, uint32_t power) 277 1.2.2.2 yamt { 278 1.2.2.2 yamt /* i.MX233 does not support setting bus power. */ 279 1.2.2.2 yamt return 0; 280 1.2.2.2 yamt } 281 1.2.2.2 yamt 282 1.2.2.2 yamt static int 283 1.2.2.2 yamt issp_bus_clock(sdmmc_chipset_handle_t sch, int clock) 284 1.2.2.2 yamt { 285 1.2.2.2 yamt struct issp_softc *sc = sch; 286 1.2.2.2 yamt uint32_t sck; 287 1.2.2.2 yamt 288 1.2.2.2 yamt aprint_normal_dev(sc->sc_dev, "requested clock %d Hz", clock * 1000); 289 1.2.2.2 yamt sck = issp_set_sck(sc, clock * 1000); 290 1.2.2.2 yamt aprint_normal(", got %d Hz\n", sck); 291 1.2.2.2 yamt 292 1.2.2.2 yamt return 0; 293 1.2.2.2 yamt } 294 1.2.2.2 yamt 295 1.2.2.2 yamt static int 296 1.2.2.2 yamt issp_bus_width(sdmmc_chipset_handle_t sch, int width) 297 1.2.2.2 yamt { 298 1.2.2.2 yamt /* Return error if other than 4-bit width is requested. */ 299 1.2.2.2 yamt return width - 4; 300 1.2.2.2 yamt } 301 1.2.2.2 yamt 302 1.2.2.2 yamt static int 303 1.2.2.2 yamt issp_bus_rod(sdmmc_chipset_handle_t sch, int rod) 304 1.2.2.2 yamt { 305 1.2.2.2 yamt /* Go to data transfer mode. */ 306 1.2.2.2 yamt return 0; 307 1.2.2.2 yamt } 308 1.2.2.2 yamt 309 1.2.2.2 yamt static void 310 1.2.2.2 yamt issp_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 311 1.2.2.2 yamt { 312 1.2.2.2 yamt struct issp_softc *sc = sch; 313 1.2.2.2 yamt uint32_t reg; 314 1.2.2.2 yamt 315 1.2.2.2 yamt /* Set excepted response type. */ 316 1.2.2.2 yamt SSP_WRITE(sc, HW_SSP_CTRL0_CLR, 317 1.2.2.2 yamt HW_SSP_CTRL0_GET_RESP | HW_SSP_CTRL0_LONG_RESP); 318 1.2.2.2 yamt 319 1.2.2.2 yamt if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 320 1.2.2.2 yamt SSP_WRITE(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_GET_RESP); 321 1.2.2.2 yamt if (ISSET(cmd->c_flags, SCF_RSP_136)) 322 1.2.2.2 yamt SSP_WRITE(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_LONG_RESP); 323 1.2.2.2 yamt } 324 1.2.2.2 yamt 325 1.2.2.2 yamt /* If CMD does not need CRC validation, tell it to SSP. */ 326 1.2.2.2 yamt if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 327 1.2.2.2 yamt SSP_WRITE(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_IGNORE_CRC); 328 1.2.2.2 yamt else 329 1.2.2.2 yamt SSP_WRITE(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_IGNORE_CRC); 330 1.2.2.2 yamt 331 1.2.2.2 yamt /* Set command. */ 332 1.2.2.2 yamt SSP_WRITE(sc, HW_SSP_CMD0_CLR, HW_SSP_CMD0_CMD); 333 1.2.2.2 yamt SSP_WRITE(sc, HW_SSP_CMD0_SET, 334 1.2.2.2 yamt __SHIFTIN(cmd->c_opcode, HW_SSP_CMD0_CMD)); 335 1.2.2.2 yamt 336 1.2.2.2 yamt /* Set command argument. */ 337 1.2.2.2 yamt SSP_WRITE(sc, HW_SSP_CMD1, cmd->c_arg); 338 1.2.2.2 yamt 339 1.2.2.2 yamt /* Run the command. */ 340 1.2.2.2 yamt SSP_WRITE(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_RUN); 341 1.2.2.2 yamt 342 1.2.2.2 yamt /* Wait until SSP has processed the command. */ 343 1.2.2.2 yamt while (SSP_READ(sc, HW_SSP_STATUS) & 344 1.2.2.2 yamt (HW_SSP_STATUS_CMD_BUSY | HW_SSP_STATUS_BUSY)) 345 1.2.2.2 yamt ; 346 1.2.2.2 yamt 347 1.2.2.2 yamt /* Check if the command ran without errors. */ 348 1.2.2.2 yamt reg = SSP_READ(sc, HW_SSP_STATUS); 349 1.2.2.2 yamt 350 1.2.2.2 yamt if (reg & SSP_STATUS_ERR) 351 1.2.2.2 yamt cmd->c_error = reg & SSP_STATUS_ERR; 352 1.2.2.2 yamt 353 1.2.2.2 yamt /* Read response if such was requested. */ 354 1.2.2.2 yamt if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 355 1.2.2.2 yamt cmd->c_resp[0] = SSP_READ(sc, HW_SSP_SDRESP0); 356 1.2.2.2 yamt if (ISSET(cmd->c_flags, SCF_RSP_136)) { 357 1.2.2.2 yamt cmd->c_resp[1] = SSP_READ(sc, HW_SSP_SDRESP1); 358 1.2.2.2 yamt cmd->c_resp[2] = SSP_READ(sc, HW_SSP_SDRESP2); 359 1.2.2.2 yamt cmd->c_resp[3] = SSP_READ(sc, HW_SSP_SDRESP3); 360 1.2.2.2 yamt } 361 1.2.2.2 yamt } 362 1.2.2.2 yamt 363 1.2.2.2 yamt /* 364 1.2.2.2 yamt apbdma_dmamem_alloc() 365 1.2.2.2 yamt apbdma_do_dma() 366 1.2.2.2 yamt wait_until_done() 367 1.2.2.2 yamt */ 368 1.2.2.2 yamt return; 369 1.2.2.2 yamt } 370 1.2.2.2 yamt 371 1.2.2.2 yamt static void 372 1.2.2.2 yamt issp_card_enable_intr(sdmmc_chipset_handle_t sch, int irq) 373 1.2.2.2 yamt { 374 1.2.2.2 yamt struct issp_softc *sc = sch; 375 1.2.2.2 yamt 376 1.2.2.2 yamt aprint_normal_dev(sc->sc_dev, 377 1.2.2.2 yamt "issp_card_enable_intr NOT IMPLEMENTED!\n"); 378 1.2.2.2 yamt 379 1.2.2.2 yamt return; 380 1.2.2.2 yamt } 381 1.2.2.2 yamt 382 1.2.2.2 yamt static void 383 1.2.2.2 yamt issp_card_intr_ack(sdmmc_chipset_handle_t sch) 384 1.2.2.2 yamt { 385 1.2.2.2 yamt struct issp_softc *sc = sch; 386 1.2.2.2 yamt 387 1.2.2.2 yamt aprint_normal_dev(sc->sc_dev, "issp_card_intr_ack NOT IMPLEMENTED!\n"); 388 1.2.2.2 yamt 389 1.2.2.2 yamt return; 390 1.2.2.2 yamt } 391 1.2.2.2 yamt 392 1.2.2.2 yamt /* 393 1.2.2.2 yamt * Reset the SSP block. 394 1.2.2.2 yamt * 395 1.2.2.2 yamt * Inspired by i.MX233 RM "39.3.10 Correct Way to Soft Reset a Block" 396 1.2.2.2 yamt */ 397 1.2.2.2 yamt static void 398 1.2.2.2 yamt issp_reset(struct issp_softc *sc) 399 1.2.2.2 yamt { 400 1.2.2.2 yamt unsigned int loop; 401 1.2.2.2 yamt 402 1.2.2.2 yamt /* Prepare for soft-reset by making sure that SFTRST is not currently 403 1.2.2.2 yamt * asserted. Also clear CLKGATE so we can wait for its assertion below. 404 1.2.2.2 yamt */ 405 1.2.2.2 yamt SSP_WRITE(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_SFTRST); 406 1.2.2.2 yamt 407 1.2.2.2 yamt /* Wait at least a microsecond for SFTRST to deassert. */ 408 1.2.2.2 yamt loop = 0; 409 1.2.2.2 yamt while ((SSP_READ(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_SFTRST) || 410 1.2.2.2 yamt (loop < SSP_SOFT_RST_LOOP)) 411 1.2.2.2 yamt loop++; 412 1.2.2.2 yamt 413 1.2.2.2 yamt /* Clear CLKGATE so we can wait for its assertion below. */ 414 1.2.2.2 yamt SSP_WRITE(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_CLKGATE); 415 1.2.2.2 yamt 416 1.2.2.2 yamt /* Soft-reset the block. */ 417 1.2.2.2 yamt SSP_WRITE(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_SFTRST); 418 1.2.2.2 yamt 419 1.2.2.2 yamt /* Wait until clock is in the gated state. */ 420 1.2.2.2 yamt while (!(SSP_READ(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_CLKGATE)); 421 1.2.2.2 yamt 422 1.2.2.2 yamt /* Bring block out of reset. */ 423 1.2.2.2 yamt SSP_WRITE(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_SFTRST); 424 1.2.2.2 yamt 425 1.2.2.2 yamt loop = 0; 426 1.2.2.2 yamt while ((SSP_READ(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_SFTRST) || 427 1.2.2.2 yamt (loop < SSP_SOFT_RST_LOOP)) 428 1.2.2.2 yamt loop++; 429 1.2.2.2 yamt 430 1.2.2.2 yamt SSP_WRITE(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_CLKGATE); 431 1.2.2.2 yamt 432 1.2.2.2 yamt /* Wait until clock is in the NON-gated state. */ 433 1.2.2.2 yamt while (SSP_READ(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_CLKGATE); 434 1.2.2.2 yamt 435 1.2.2.2 yamt return; 436 1.2.2.2 yamt } 437 1.2.2.2 yamt 438 1.2.2.2 yamt /* 439 1.2.2.2 yamt * Initialize common options. 440 1.2.2.2 yamt */ 441 1.2.2.2 yamt static void 442 1.2.2.2 yamt issp_init(struct issp_softc *sc) 443 1.2.2.2 yamt { 444 1.2.2.2 yamt uint32_t reg; 445 1.2.2.2 yamt 446 1.2.2.2 yamt /* Initialize SD/MMC controller. */ 447 1.2.2.2 yamt reg = SSP_READ(sc, HW_SSP_CTRL0); 448 1.2.2.2 yamt reg &= ~(HW_SSP_CTRL0_BUS_WIDTH); 449 1.2.2.2 yamt reg |= __SHIFTIN(0x1, HW_SSP_CTRL0_BUS_WIDTH) | HW_SSP_CTRL0_ENABLE; 450 1.2.2.2 yamt SSP_WRITE(sc, HW_SSP_CTRL0, reg); 451 1.2.2.2 yamt 452 1.2.2.2 yamt reg = SSP_READ(sc, HW_SSP_CTRL1); 453 1.2.2.2 yamt reg &= ~(HW_SSP_CTRL1_WORD_LENGTH | HW_SSP_CTRL1_SSP_MODE); 454 1.2.2.2 yamt reg |= HW_SSP_CTRL1_POLARITY | 455 1.2.2.2 yamt __SHIFTIN(0x7, HW_SSP_CTRL1_WORD_LENGTH) | 456 1.2.2.2 yamt __SHIFTIN(0x3, HW_SSP_CTRL1_SSP_MODE); 457 1.2.2.2 yamt SSP_WRITE(sc, HW_SSP_CTRL1, reg); 458 1.2.2.2 yamt 459 1.2.2.2 yamt /* Set command timeout. */ 460 1.2.2.2 yamt reg = SSP_READ(sc, HW_SSP_TIMING); 461 1.2.2.2 yamt reg &= ~(HW_SSP_TIMING_TIMEOUT); 462 1.2.2.2 yamt reg |= __SHIFTIN(SSP_CMD_TIMEOUT, HW_SSP_TIMING_TIMEOUT); 463 1.2.2.2 yamt SSP_WRITE(sc, HW_SSP_TIMING, reg); 464 1.2.2.2 yamt 465 1.2.2.2 yamt return; 466 1.2.2.2 yamt } 467 1.2.2.2 yamt 468 1.2.2.2 yamt /* 469 1.2.2.2 yamt * Set SSP_SCK clock rate to the value specified in target. 470 1.2.2.2 yamt * 471 1.2.2.2 yamt * SSP_SCK is calculated as: SSP_CLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)) 472 1.2.2.2 yamt * 473 1.2.2.2 yamt * issp_set_sck find the most suitable CLOCK_DIVIDE and CLOCK_RATE register 474 1.2.2.2 yamt * values for the target clock rate by iterating through all possible register 475 1.2.2.2 yamt * values. 476 1.2.2.2 yamt */ 477 1.2.2.2 yamt static uint32_t 478 1.2.2.2 yamt issp_set_sck(struct issp_softc *sc, uint32_t target) 479 1.2.2.2 yamt { 480 1.2.2.2 yamt uint32_t newclk, found, reg; 481 1.2.2.2 yamt uint8_t div, rate, d, r; 482 1.2.2.2 yamt 483 1.2.2.2 yamt found = div = rate = 0; 484 1.2.2.2 yamt 485 1.2.2.2 yamt for (d = 2; d < 254; d++) { 486 1.2.2.2 yamt for (r = 0; r < 255; r++) { 487 1.2.2.2 yamt newclk = SSP_CLK / (d * (1 + r)); 488 1.2.2.2 yamt if (newclk == target) { 489 1.2.2.2 yamt found = newclk; 490 1.2.2.2 yamt div = d; 491 1.2.2.2 yamt rate = r; 492 1.2.2.2 yamt goto out; 493 1.2.2.2 yamt } 494 1.2.2.2 yamt if (newclk < target && newclk > found) { 495 1.2.2.2 yamt found = newclk; 496 1.2.2.2 yamt div = d; 497 1.2.2.2 yamt rate = r; 498 1.2.2.2 yamt } 499 1.2.2.2 yamt } 500 1.2.2.2 yamt } 501 1.2.2.2 yamt out: 502 1.2.2.2 yamt reg = SSP_READ(sc, HW_SSP_TIMING); 503 1.2.2.2 yamt reg &= ~(HW_SSP_TIMING_CLOCK_DIVIDE | HW_SSP_TIMING_CLOCK_RATE); 504 1.2.2.2 yamt reg |= __SHIFTIN(div, HW_SSP_TIMING_CLOCK_DIVIDE) | 505 1.2.2.2 yamt __SHIFTIN(rate, HW_SSP_TIMING_CLOCK_RATE); 506 1.2.2.2 yamt SSP_WRITE(sc, HW_SSP_TIMING, reg); 507 1.2.2.2 yamt 508 1.2.2.2 yamt return SSP_CLK / (d * (1 + r)); 509 1.2.2.2 yamt } 510
Indexes created Sun Oct 19 02:09:48 GMT 2025