imx23_ssp.c revision 1.2.2.3
1 1.2.2.2 yamt /* $Id: imx23_ssp.c,v 1.2.2.3 2013/01/23 00:05:41 yamt Exp $ */ 2 1.2.2.2 yamt 3 1.2.2.2 yamt /* 4 1.2.2.2 yamt * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 1.2.2.2 yamt * All rights reserved. 6 1.2.2.2 yamt * 7 1.2.2.2 yamt * This code is derived from software contributed to The NetBSD Foundation 8 1.2.2.2 yamt * by Petri Laakso. 9 1.2.2.2 yamt * 10 1.2.2.2 yamt * Redistribution and use in source and binary forms, with or without 11 1.2.2.2 yamt * modification, are permitted provided that the following conditions 12 1.2.2.2 yamt * are met: 13 1.2.2.2 yamt * 1. Redistributions of source code must retain the above copyright 14 1.2.2.2 yamt * notice, this list of conditions and the following disclaimer. 15 1.2.2.2 yamt * 2. Redistributions in binary form must reproduce the above copyright 16 1.2.2.2 yamt * notice, this list of conditions and the following disclaimer in the 17 1.2.2.2 yamt * documentation and/or other materials provided with the distribution. 18 1.2.2.2 yamt * 19 1.2.2.2 yamt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.2.2.2 yamt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.2.2.2 yamt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.2.2.2 yamt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.2.2.2 yamt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.2.2.2 yamt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.2.2.2 yamt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.2.2.2 yamt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.2.2.2 yamt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.2.2.2 yamt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.2.2.2 yamt * POSSIBILITY OF SUCH DAMAGE. 30 1.2.2.2 yamt */ 31 1.2.2.2 yamt 32 1.2.2.2 yamt #include <sys/param.h> 33 1.2.2.2 yamt #include <sys/types.h> 34 1.2.2.2 yamt #include <sys/bus.h> 35 1.2.2.2 yamt #include <sys/cdefs.h> 36 1.2.2.2 yamt #include <sys/device.h> 37 1.2.2.2 yamt #include <sys/errno.h> 38 1.2.2.2 yamt #include <sys/systm.h> 39 1.2.2.2 yamt 40 1.2.2.2 yamt #include <arm/imx/imx23_sspreg.h> 41 1.2.2.2 yamt #include <arm/imx/imx23var.h> 42 1.2.2.2 yamt 43 1.2.2.2 yamt #include <dev/sdmmc/sdmmcchip.h> 44 1.2.2.2 yamt #include <dev/sdmmc/sdmmcreg.h> 45 1.2.2.2 yamt #include <dev/sdmmc/sdmmcvar.h> 46 1.2.2.2 yamt 47 1.2.2.2 yamt /* 48 1.2.2.3 yamt * SD/MMC host controller driver for i.MX23. 49 1.2.2.2 yamt */ 50 1.2.2.2 yamt 51 1.2.2.2 yamt struct issp_softc { 52 1.2.2.2 yamt device_t sc_dev; 53 1.2.2.2 yamt bus_space_tag_t sc_iot; 54 1.2.2.2 yamt bus_space_handle_t sc_hdl; 55 1.2.2.2 yamt device_t sc_sdmmc; 56 1.2.2.2 yamt device_t dmac; 57 1.2.2.2 yamt }; 58 1.2.2.2 yamt 59 1.2.2.2 yamt static int issp_match(device_t, cfdata_t, void *); 60 1.2.2.2 yamt static void issp_attach(device_t, device_t, void *); 61 1.2.2.2 yamt static int issp_activate(device_t, enum devact); 62 1.2.2.2 yamt 63 1.2.2.3 yamt static void issp_reset(struct issp_softc *); 64 1.2.2.3 yamt static void issp_init(struct issp_softc *); 65 1.2.2.3 yamt static uint32_t issp_set_sck(struct issp_softc *, uint32_t target); 66 1.2.2.3 yamt 67 1.2.2.3 yamt /* sdmmc(4) driver chip function prototypes. */ 68 1.2.2.2 yamt static int issp_host_reset(sdmmc_chipset_handle_t); 69 1.2.2.2 yamt static uint32_t issp_host_ocr(sdmmc_chipset_handle_t); 70 1.2.2.2 yamt static int issp_host_maxblklen(sdmmc_chipset_handle_t); 71 1.2.2.2 yamt static int issp_card_detect(sdmmc_chipset_handle_t); 72 1.2.2.2 yamt static int issp_write_protect(sdmmc_chipset_handle_t); 73 1.2.2.2 yamt static int issp_bus_power(sdmmc_chipset_handle_t, uint32_t); 74 1.2.2.2 yamt static int issp_bus_clock(sdmmc_chipset_handle_t, int); 75 1.2.2.2 yamt static int issp_bus_width(sdmmc_chipset_handle_t, int); 76 1.2.2.2 yamt static int issp_bus_rod(sdmmc_chipset_handle_t, int); 77 1.2.2.2 yamt static void issp_exec_command(sdmmc_chipset_handle_t, 78 1.2.2.2 yamt struct sdmmc_command *); 79 1.2.2.2 yamt static void issp_card_enable_intr(sdmmc_chipset_handle_t, int); 80 1.2.2.2 yamt static void issp_card_intr_ack(sdmmc_chipset_handle_t); 81 1.2.2.2 yamt 82 1.2.2.2 yamt static struct sdmmc_chip_functions issp_functions = { 83 1.2.2.2 yamt .host_reset = issp_host_reset, 84 1.2.2.2 yamt .host_ocr = issp_host_ocr, 85 1.2.2.2 yamt .host_maxblklen = issp_host_maxblklen, 86 1.2.2.2 yamt .card_detect = issp_card_detect, 87 1.2.2.2 yamt .write_protect = issp_write_protect, 88 1.2.2.2 yamt .bus_power = issp_bus_power, 89 1.2.2.2 yamt .bus_clock = issp_bus_clock, 90 1.2.2.2 yamt .bus_width = issp_bus_width, 91 1.2.2.2 yamt .bus_rod = issp_bus_rod, 92 1.2.2.2 yamt .exec_command = issp_exec_command, 93 1.2.2.2 yamt .card_enable_intr = issp_card_enable_intr, 94 1.2.2.2 yamt .card_intr_ack = issp_card_intr_ack 95 1.2.2.2 yamt }; 96 1.2.2.2 yamt 97 1.2.2.3 yamt CFATTACH_DECL3_NEW(ssp, 98 1.2.2.3 yamt sizeof(struct issp_softc), 99 1.2.2.3 yamt issp_match, 100 1.2.2.3 yamt issp_attach, 101 1.2.2.3 yamt NULL, 102 1.2.2.3 yamt issp_activate, 103 1.2.2.3 yamt NULL, 104 1.2.2.3 yamt NULL, 105 1.2.2.3 yamt 0); 106 1.2.2.3 yamt 107 1.2.2.3 yamt #define SSP_SOFT_RST_LOOP 455 /* At least 1 us ... */ 108 1.2.2.3 yamt 109 1.2.2.3 yamt #define SSP_RD(sc, reg) \ 110 1.2.2.2 yamt bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg)) 111 1.2.2.3 yamt #define SSP_WR(sc, reg, val) \ 112 1.2.2.2 yamt bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val)) 113 1.2.2.2 yamt 114 1.2.2.3 yamt #define SSP_CLK 96000000 /* CLK_SSP from PLL is 96 MHz */ 115 1.2.2.3 yamt #define SSP_CLK_MIN 400 /* 400 kHz */ 116 1.2.2.3 yamt #define SSP_CLK_MAX 48000 /* 48 MHz */ 117 1.2.2.3 yamt 118 1.2.2.3 yamt #define SSP_BUSY (HW_SSP_STATUS_CMD_BUSY | \ 119 1.2.2.3 yamt HW_SSP_STATUS_DATA_BUSY | \ 120 1.2.2.3 yamt HW_SSP_STATUS_BUSY) 121 1.2.2.3 yamt 122 1.2.2.3 yamt #define SSP_RUN_ERR (HW_SSP_STATUS_RESP_CRC_ERR | \ 123 1.2.2.2 yamt HW_SSP_STATUS_RESP_ERR | \ 124 1.2.2.2 yamt HW_SSP_STATUS_RESP_TIMEOUT | \ 125 1.2.2.2 yamt HW_SSP_STATUS_DATA_CRC_ERR | \ 126 1.2.2.2 yamt HW_SSP_STATUS_TIMEOUT) 127 1.2.2.2 yamt 128 1.2.2.3 yamt #define BLKIO_NONE 0 129 1.2.2.3 yamt #define BLKIO_RD 1 130 1.2.2.3 yamt #define BLKIO_WR 2 131 1.2.2.3 yamt 132 1.2.2.3 yamt #define BUS_WIDTH_1_BIT 0x0 133 1.2.2.3 yamt #define BUS_WIDTH_4_BIT 0x1 134 1.2.2.3 yamt #define BUS_WIDTH_8_BIT 0x2 135 1.2.2.3 yamt 136 1.2.2.2 yamt static int 137 1.2.2.2 yamt issp_match(device_t parent, cfdata_t match, void *aux) 138 1.2.2.2 yamt { 139 1.2.2.2 yamt struct apb_attach_args *aa = aux; 140 1.2.2.2 yamt 141 1.2.2.2 yamt if ((aa->aa_addr == HW_SSP1_BASE) && (aa->aa_size == HW_SSP1_SIZE)) 142 1.2.2.2 yamt return 1; 143 1.2.2.2 yamt 144 1.2.2.2 yamt if ((aa->aa_addr == HW_SSP2_BASE) && (aa->aa_size == HW_SSP2_SIZE)) 145 1.2.2.2 yamt return 1; 146 1.2.2.2 yamt 147 1.2.2.2 yamt return 0; 148 1.2.2.2 yamt } 149 1.2.2.2 yamt 150 1.2.2.2 yamt static void 151 1.2.2.2 yamt issp_attach(device_t parent, device_t self, void *aux) 152 1.2.2.2 yamt { 153 1.2.2.2 yamt struct issp_softc *sc = device_private(self); 154 1.2.2.3 yamt struct apb_softc *sc_parent = device_private(parent); 155 1.2.2.2 yamt struct apb_attach_args *aa = aux; 156 1.2.2.2 yamt struct sdmmcbus_attach_args saa; 157 1.2.2.3 yamt static int issp_attached = 0; 158 1.2.2.3 yamt 159 1.2.2.2 yamt if (issp_attached) 160 1.2.2.2 yamt return; 161 1.2.2.2 yamt 162 1.2.2.2 yamt sc->sc_dev = self; 163 1.2.2.2 yamt sc->sc_iot = aa->aa_iot; 164 1.2.2.3 yamt sc->dmac = sc_parent->dmac; 165 1.2.2.2 yamt 166 1.2.2.2 yamt if (bus_space_map(sc->sc_iot, 167 1.2.2.2 yamt aa->aa_addr, aa->aa_size, 0, &(sc->sc_hdl))) { 168 1.2.2.2 yamt aprint_error_dev(sc->sc_dev, "unable to map bus space\n"); 169 1.2.2.2 yamt return; 170 1.2.2.2 yamt } 171 1.2.2.2 yamt 172 1.2.2.2 yamt issp_reset(sc); 173 1.2.2.3 yamt issp_init(sc); 174 1.2.2.2 yamt 175 1.2.2.3 yamt uint32_t issp_vers = SSP_RD(sc, HW_SSP_VERSION); 176 1.2.2.2 yamt aprint_normal(": SSP Block v%" __PRIuBIT ".%" __PRIuBIT "\n", 177 1.2.2.2 yamt __SHIFTOUT(issp_vers, HW_SSP_VERSION_MAJOR), 178 1.2.2.2 yamt __SHIFTOUT(issp_vers, HW_SSP_VERSION_MINOR)); 179 1.2.2.2 yamt 180 1.2.2.2 yamt saa.saa_busname = "sdmmc"; 181 1.2.2.2 yamt saa.saa_sct = &issp_functions; 182 1.2.2.2 yamt saa.saa_spi_sct = NULL; 183 1.2.2.2 yamt saa.saa_sch = sc; 184 1.2.2.2 yamt saa.saa_dmat = aa->aa_dmat; 185 1.2.2.2 yamt saa.saa_clkmin = SSP_CLK_MIN; 186 1.2.2.2 yamt saa.saa_clkmax = SSP_CLK_MAX; 187 1.2.2.3 yamt /* Add SMC_CAPS_DMA capability when DMA funtionality is implemented. */ 188 1.2.2.3 yamt saa.saa_caps = SMC_CAPS_4BIT_MODE | SMC_CAPS_SINGLE_ONLY; 189 1.2.2.2 yamt 190 1.2.2.2 yamt sc->sc_sdmmc = config_found(sc->sc_dev, &saa, NULL); 191 1.2.2.2 yamt if (sc->sc_sdmmc == NULL) { 192 1.2.2.2 yamt aprint_error_dev(sc->sc_dev, "unable to attach sdmmc\n"); 193 1.2.2.2 yamt return; 194 1.2.2.2 yamt } 195 1.2.2.2 yamt 196 1.2.2.2 yamt issp_attached = 1; 197 1.2.2.2 yamt 198 1.2.2.2 yamt return; 199 1.2.2.2 yamt } 200 1.2.2.2 yamt 201 1.2.2.2 yamt static int 202 1.2.2.2 yamt issp_activate(device_t self, enum devact act) 203 1.2.2.2 yamt { 204 1.2.2.2 yamt return EOPNOTSUPP; 205 1.2.2.2 yamt } 206 1.2.2.2 yamt 207 1.2.2.2 yamt /* 208 1.2.2.2 yamt * sdmmc chip functions. 209 1.2.2.2 yamt */ 210 1.2.2.2 yamt static int 211 1.2.2.2 yamt issp_host_reset(sdmmc_chipset_handle_t sch) 212 1.2.2.2 yamt { 213 1.2.2.2 yamt struct issp_softc *sc = sch; 214 1.2.2.2 yamt 215 1.2.2.2 yamt issp_reset(sc); 216 1.2.2.2 yamt 217 1.2.2.2 yamt return 0; 218 1.2.2.2 yamt } 219 1.2.2.2 yamt 220 1.2.2.2 yamt static uint32_t 221 1.2.2.2 yamt issp_host_ocr(sdmmc_chipset_handle_t sch) 222 1.2.2.2 yamt { 223 1.2.2.2 yamt /* SSP supports at least 3.2-3.3v */ 224 1.2.2.2 yamt return MMC_OCR_3_2V_3_3V; 225 1.2.2.2 yamt } 226 1.2.2.2 yamt 227 1.2.2.2 yamt static int 228 1.2.2.2 yamt issp_host_maxblklen(sdmmc_chipset_handle_t sch) 229 1.2.2.2 yamt { 230 1.2.2.2 yamt return 512; 231 1.2.2.2 yamt } 232 1.2.2.2 yamt 233 1.2.2.2 yamt /* 234 1.2.2.2 yamt * Called at the beginning of sdmmc_task_thread to detect the presence 235 1.2.2.2 yamt * of the SD card. 236 1.2.2.2 yamt */ 237 1.2.2.2 yamt static int 238 1.2.2.2 yamt issp_card_detect(sdmmc_chipset_handle_t sch) 239 1.2.2.2 yamt { 240 1.2.2.2 yamt /* struct issp_softc *sc = sch; 241 1.2.2.2 yamt * 242 1.2.2.2 yamt * In the perfect world I'll just: 243 1.2.2.3 yamt * return SSP_RD(sc, HW_SSP_STATUS) & HW_SSP_STATUS_CARD_DETECT; 244 1.2.2.2 yamt * and call it a day. 245 1.2.2.2 yamt * 246 1.2.2.3 yamt * But on i.MX23 OLinuXino MAXI, SSP1_DETECT is not used for the SD 247 1.2.2.2 yamt * card detection but SSP1_DATA3 is, as Tsvetan put it: 248 1.2.2.2 yamt * 249 1.2.2.2 yamt * < Tsvetan> if you want to know if SD card is inserted watch 250 1.2.2.2 yamt * CD/DAT3/CS port 251 1.2.2.2 yamt * < Tsvetan> without card there is R20 weak pulldown 252 1.2.2.2 yamt * < Tsvetan> all cards have 40K pullup to this pin 253 1.2.2.2 yamt * < Tsvetan> so when card is inserted you will read it high 254 1.2.2.2 yamt * 255 1.2.2.2 yamt * Which means I should to do something like this: 256 1.2.2.2 yamt * #if BOARDTYPE == MAXI (Possibly MINI & MICRO) 257 1.2.2.2 yamt * return GPIO_READ(PIN_125) & PIN_125 258 1.2.2.2 yamt * #else 259 1.2.2.3 yamt * return SSP_RD(sc, STATUS) & CARD_DETECT; 260 1.2.2.2 yamt * #endif 261 1.2.2.2 yamt * Until GPIO functionality is not present I am just going to */ 262 1.2.2.2 yamt 263 1.2.2.2 yamt return 1; 264 1.2.2.2 yamt } 265 1.2.2.2 yamt 266 1.2.2.2 yamt static int 267 1.2.2.2 yamt issp_write_protect(sdmmc_chipset_handle_t sch) 268 1.2.2.2 yamt { 269 1.2.2.2 yamt /* The device is not write protected. */ 270 1.2.2.2 yamt return 0; 271 1.2.2.2 yamt } 272 1.2.2.2 yamt 273 1.2.2.2 yamt static int 274 1.2.2.3 yamt issp_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 275 1.2.2.2 yamt { 276 1.2.2.3 yamt /* i.MX23 SSP does not support setting bus power. */ 277 1.2.2.2 yamt return 0; 278 1.2.2.2 yamt } 279 1.2.2.2 yamt 280 1.2.2.2 yamt static int 281 1.2.2.2 yamt issp_bus_clock(sdmmc_chipset_handle_t sch, int clock) 282 1.2.2.2 yamt { 283 1.2.2.2 yamt struct issp_softc *sc = sch; 284 1.2.2.2 yamt uint32_t sck; 285 1.2.2.2 yamt 286 1.2.2.2 yamt sck = issp_set_sck(sc, clock * 1000); 287 1.2.2.3 yamt 288 1.2.2.3 yamt /* Notify user if we didn't get exact clock rate from SSP that was 289 1.2.2.3 yamt * requested. */ 290 1.2.2.3 yamt if (sck != clock * 1000) 291 1.2.2.3 yamt aprint_normal_dev(sc->sc_dev, "requested clock %dHz, " 292 1.2.2.3 yamt "but got %dHz\n", clock * 1000, sck); 293 1.2.2.2 yamt 294 1.2.2.2 yamt return 0; 295 1.2.2.2 yamt } 296 1.2.2.2 yamt 297 1.2.2.2 yamt static int 298 1.2.2.2 yamt issp_bus_width(sdmmc_chipset_handle_t sch, int width) 299 1.2.2.2 yamt { 300 1.2.2.3 yamt struct issp_softc *sc = sch; 301 1.2.2.3 yamt uint32_t reg; 302 1.2.2.3 yamt 303 1.2.2.3 yamt reg = SSP_RD(sc, HW_SSP_CTRL0); 304 1.2.2.3 yamt reg &= ~(HW_SSP_CTRL0_BUS_WIDTH); 305 1.2.2.3 yamt 306 1.2.2.3 yamt switch(width) { 307 1.2.2.3 yamt case(1): 308 1.2.2.3 yamt reg |= __SHIFTIN(BUS_WIDTH_1_BIT, HW_SSP_CTRL0_BUS_WIDTH); 309 1.2.2.3 yamt break; 310 1.2.2.3 yamt case(4): 311 1.2.2.3 yamt reg |= __SHIFTIN(BUS_WIDTH_4_BIT, HW_SSP_CTRL0_BUS_WIDTH); 312 1.2.2.3 yamt break; 313 1.2.2.3 yamt case(8): 314 1.2.2.3 yamt reg |= __SHIFTIN(BUS_WIDTH_8_BIT, HW_SSP_CTRL0_BUS_WIDTH); 315 1.2.2.3 yamt break; 316 1.2.2.3 yamt default: 317 1.2.2.3 yamt return 1; 318 1.2.2.3 yamt } 319 1.2.2.3 yamt 320 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0, reg); 321 1.2.2.3 yamt 322 1.2.2.3 yamt return 0; 323 1.2.2.2 yamt } 324 1.2.2.2 yamt 325 1.2.2.2 yamt static int 326 1.2.2.2 yamt issp_bus_rod(sdmmc_chipset_handle_t sch, int rod) 327 1.2.2.2 yamt { 328 1.2.2.2 yamt /* Go to data transfer mode. */ 329 1.2.2.2 yamt return 0; 330 1.2.2.2 yamt } 331 1.2.2.2 yamt 332 1.2.2.2 yamt static void 333 1.2.2.2 yamt issp_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 334 1.2.2.2 yamt { 335 1.2.2.2 yamt struct issp_softc *sc = sch; 336 1.2.2.2 yamt uint32_t reg; 337 1.2.2.3 yamt uint32_t do_blkio; 338 1.2.2.3 yamt uint32_t i; 339 1.2.2.3 yamt 340 1.2.2.3 yamt do_blkio = 0; 341 1.2.2.2 yamt 342 1.2.2.3 yamt /* Wait until SSP done. (data I/O error + retry...) */ 343 1.2.2.3 yamt while (SSP_RD(sc, HW_SSP_STATUS) & SSP_BUSY) 344 1.2.2.3 yamt ; 345 1.2.2.3 yamt 346 1.2.2.3 yamt /* Set expected response type. */ 347 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0_CLR, 348 1.2.2.2 yamt HW_SSP_CTRL0_GET_RESP | HW_SSP_CTRL0_LONG_RESP); 349 1.2.2.2 yamt 350 1.2.2.2 yamt if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 351 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_GET_RESP); 352 1.2.2.2 yamt if (ISSET(cmd->c_flags, SCF_RSP_136)) 353 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_LONG_RESP); 354 1.2.2.2 yamt } 355 1.2.2.2 yamt 356 1.2.2.2 yamt /* If CMD does not need CRC validation, tell it to SSP. */ 357 1.2.2.2 yamt if (ISSET(cmd->c_flags, SCF_RSP_CRC)) 358 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_IGNORE_CRC); 359 1.2.2.2 yamt else 360 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_IGNORE_CRC); 361 1.2.2.2 yamt 362 1.2.2.2 yamt /* Set command. */ 363 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CMD0_CLR, HW_SSP_CMD0_CMD); 364 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CMD0_SET, 365 1.2.2.2 yamt __SHIFTIN(cmd->c_opcode, HW_SSP_CMD0_CMD)); 366 1.2.2.2 yamt 367 1.2.2.2 yamt /* Set command argument. */ 368 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CMD1, cmd->c_arg); 369 1.2.2.3 yamt 370 1.2.2.3 yamt /* Is data to be transferred? */ 371 1.2.2.3 yamt if (cmd->c_datalen > 0 && cmd->c_data != NULL) { 372 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_DATA_XFER); 373 1.2.2.3 yamt /* Transfer XFER_COUNT of 8-bit words. */ 374 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_XFER_COUNT); 375 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0_SET, 376 1.2.2.3 yamt __SHIFTIN(cmd->c_datalen, HW_SSP_CTRL0_XFER_COUNT)); 377 1.2.2.3 yamt 378 1.2.2.3 yamt /* XXX: why 8CYC? Bit is never cleaned. */ 379 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CMD0_SET, HW_SSP_CMD0_APPEND_8CYC); 380 1.2.2.3 yamt 381 1.2.2.3 yamt if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 382 1.2.2.3 yamt /* Read mode. */ 383 1.2.2.3 yamt do_blkio |= BLKIO_RD; 384 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_READ); 385 1.2.2.3 yamt } else { 386 1.2.2.3 yamt /* Write mode. */ 387 1.2.2.3 yamt do_blkio |= BLKIO_WR; 388 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_READ); 389 1.2.2.3 yamt } 390 1.2.2.3 yamt } else { 391 1.2.2.3 yamt /* No data to be transferred. */ 392 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_DATA_XFER); 393 1.2.2.3 yamt } 394 1.2.2.2 yamt 395 1.2.2.2 yamt /* Run the command. */ 396 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_RUN); 397 1.2.2.2 yamt 398 1.2.2.3 yamt if (ISSET(do_blkio, BLKIO_RD)) { 399 1.2.2.3 yamt for (i = 0; i < cmd->c_datalen / 4; i++) { 400 1.2.2.3 yamt /* Wait until data arrives to FIFO. */ 401 1.2.2.3 yamt while (SSP_RD(sc, HW_SSP_STATUS) 402 1.2.2.3 yamt & HW_SSP_STATUS_FIFO_EMPTY) { 403 1.2.2.3 yamt /* Abort if error while waiting. */ 404 1.2.2.3 yamt if (SSP_RD(sc, HW_SSP_STATUS) & SSP_RUN_ERR) { 405 1.2.2.3 yamt aprint_normal_dev(sc->sc_dev, 406 1.2.2.3 yamt "RD_ERR: %x\n", 407 1.2.2.3 yamt SSP_RD(sc, HW_SSP_STATUS)); 408 1.2.2.3 yamt cmd->c_error = 1; 409 1.2.2.3 yamt goto pioerr; 410 1.2.2.3 yamt } 411 1.2.2.3 yamt } 412 1.2.2.3 yamt *((uint32_t *)cmd->c_data+i) = SSP_RD(sc, HW_SSP_DATA); 413 1.2.2.3 yamt } 414 1.2.2.3 yamt } else if (ISSET(do_blkio, BLKIO_WR)) { 415 1.2.2.3 yamt for (i = 0; i < (cmd->c_datalen / 4); i++) { 416 1.2.2.3 yamt while (SSP_RD(sc, HW_SSP_STATUS) 417 1.2.2.3 yamt & HW_SSP_STATUS_FIFO_FULL) { 418 1.2.2.3 yamt /* Abort if error while waiting. */ 419 1.2.2.3 yamt if (SSP_RD(sc, HW_SSP_STATUS) & SSP_RUN_ERR) { 420 1.2.2.3 yamt aprint_normal_dev(sc->sc_dev, 421 1.2.2.3 yamt "WR_ERR: %x\n", 422 1.2.2.3 yamt SSP_RD(sc, HW_SSP_STATUS)); 423 1.2.2.3 yamt cmd->c_error = 1; 424 1.2.2.3 yamt goto pioerr; 425 1.2.2.3 yamt } 426 1.2.2.3 yamt } 427 1.2.2.3 yamt SSP_WR(sc, HW_SSP_DATA, *((uint32_t *)cmd->c_data+i)); 428 1.2.2.3 yamt } 429 1.2.2.3 yamt } 430 1.2.2.3 yamt 431 1.2.2.3 yamt /* Wait until SSP is done. */ 432 1.2.2.3 yamt while (SSP_RD(sc, HW_SSP_STATUS) & SSP_BUSY) 433 1.2.2.3 yamt ; 434 1.2.2.3 yamt 435 1.2.2.3 yamt /* Check if the command ran successfully. */ 436 1.2.2.3 yamt reg = SSP_RD(sc, HW_SSP_STATUS); 437 1.2.2.3 yamt if (reg & SSP_RUN_ERR) 438 1.2.2.3 yamt cmd->c_error = reg & SSP_RUN_ERR; 439 1.2.2.2 yamt 440 1.2.2.2 yamt /* Read response if such was requested. */ 441 1.2.2.2 yamt if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 442 1.2.2.3 yamt cmd->c_resp[0] = SSP_RD(sc, HW_SSP_SDRESP0); 443 1.2.2.2 yamt if (ISSET(cmd->c_flags, SCF_RSP_136)) { 444 1.2.2.3 yamt cmd->c_resp[1] = SSP_RD(sc, HW_SSP_SDRESP1); 445 1.2.2.3 yamt cmd->c_resp[2] = SSP_RD(sc, HW_SSP_SDRESP2); 446 1.2.2.3 yamt cmd->c_resp[3] = SSP_RD(sc, HW_SSP_SDRESP3); 447 1.2.2.3 yamt /* 448 1.2.2.3 yamt * Remove CRC7 + LSB by rotating all bits right by 8 to 449 1.2.2.3 yamt * make sdmmc __bitfield() happy. 450 1.2.2.3 yamt */ 451 1.2.2.3 yamt cmd->c_resp[0] >>= 8; /* Remove CRC7 + LSB. */ 452 1.2.2.3 yamt cmd->c_resp[0] |= (0x000000FF & cmd->c_resp[1]) << 24; 453 1.2.2.3 yamt cmd->c_resp[1] >>= 8; 454 1.2.2.3 yamt cmd->c_resp[1] |= (0x000000FF & cmd->c_resp[2]) << 24; 455 1.2.2.3 yamt cmd->c_resp[2] >>= 8; 456 1.2.2.3 yamt cmd->c_resp[2] |= (0x000000FF & cmd->c_resp[3]) << 24; 457 1.2.2.3 yamt cmd->c_resp[3] >>= 8; 458 1.2.2.2 yamt } 459 1.2.2.2 yamt } 460 1.2.2.3 yamt pioerr: 461 1.2.2.2 yamt return; 462 1.2.2.2 yamt } 463 1.2.2.2 yamt 464 1.2.2.2 yamt static void 465 1.2.2.2 yamt issp_card_enable_intr(sdmmc_chipset_handle_t sch, int irq) 466 1.2.2.2 yamt { 467 1.2.2.2 yamt struct issp_softc *sc = sch; 468 1.2.2.2 yamt 469 1.2.2.2 yamt aprint_normal_dev(sc->sc_dev, 470 1.2.2.3 yamt "issp_card_enable_intr NOT IMPLEMENTED!\n"); 471 1.2.2.2 yamt 472 1.2.2.2 yamt return; 473 1.2.2.2 yamt } 474 1.2.2.2 yamt 475 1.2.2.2 yamt static void 476 1.2.2.2 yamt issp_card_intr_ack(sdmmc_chipset_handle_t sch) 477 1.2.2.2 yamt { 478 1.2.2.2 yamt struct issp_softc *sc = sch; 479 1.2.2.2 yamt 480 1.2.2.2 yamt aprint_normal_dev(sc->sc_dev, "issp_card_intr_ack NOT IMPLEMENTED!\n"); 481 1.2.2.2 yamt 482 1.2.2.2 yamt return; 483 1.2.2.2 yamt } 484 1.2.2.2 yamt 485 1.2.2.2 yamt /* 486 1.2.2.2 yamt * Reset the SSP block. 487 1.2.2.2 yamt * 488 1.2.2.3 yamt * Inspired by i.MX23 RM "39.3.10 Correct Way to Soft Reset a Block" 489 1.2.2.2 yamt */ 490 1.2.2.2 yamt static void 491 1.2.2.2 yamt issp_reset(struct issp_softc *sc) 492 1.2.2.2 yamt { 493 1.2.2.2 yamt unsigned int loop; 494 1.2.2.2 yamt 495 1.2.2.2 yamt /* Prepare for soft-reset by making sure that SFTRST is not currently 496 1.2.2.2 yamt * asserted. Also clear CLKGATE so we can wait for its assertion below. 497 1.2.2.2 yamt */ 498 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_SFTRST); 499 1.2.2.2 yamt 500 1.2.2.2 yamt /* Wait at least a microsecond for SFTRST to deassert. */ 501 1.2.2.2 yamt loop = 0; 502 1.2.2.3 yamt while ((SSP_RD(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_SFTRST) || 503 1.2.2.2 yamt (loop < SSP_SOFT_RST_LOOP)) 504 1.2.2.2 yamt loop++; 505 1.2.2.2 yamt 506 1.2.2.2 yamt /* Clear CLKGATE so we can wait for its assertion below. */ 507 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_CLKGATE); 508 1.2.2.2 yamt 509 1.2.2.2 yamt /* Soft-reset the block. */ 510 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_SFTRST); 511 1.2.2.2 yamt 512 1.2.2.2 yamt /* Wait until clock is in the gated state. */ 513 1.2.2.3 yamt while (!(SSP_RD(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_CLKGATE)); 514 1.2.2.2 yamt 515 1.2.2.2 yamt /* Bring block out of reset. */ 516 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_SFTRST); 517 1.2.2.2 yamt 518 1.2.2.2 yamt loop = 0; 519 1.2.2.3 yamt while ((SSP_RD(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_SFTRST) || 520 1.2.2.2 yamt (loop < SSP_SOFT_RST_LOOP)) 521 1.2.2.2 yamt loop++; 522 1.2.2.2 yamt 523 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_CLKGATE); 524 1.2.2.3 yamt 525 1.2.2.2 yamt /* Wait until clock is in the NON-gated state. */ 526 1.2.2.3 yamt while (SSP_RD(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_CLKGATE); 527 1.2.2.2 yamt 528 1.2.2.2 yamt return; 529 1.2.2.2 yamt } 530 1.2.2.2 yamt 531 1.2.2.3 yamt 532 1.2.2.2 yamt /* 533 1.2.2.3 yamt * DATA_TIMEOUT is calculated as: 534 1.2.2.3 yamt * (1 / SSP_CLK) * (DATA_TIMEOUT * 4096) 535 1.2.2.3 yamt */ 536 1.2.2.3 yamt #define DATA_TIMEOUT 0x4240 /* 723ms */ 537 1.2.2.3 yamt 538 1.2.2.3 yamt /* 539 1.2.2.3 yamt * Initialize SSP controller to SD/MMC mode. 540 1.2.2.2 yamt */ 541 1.2.2.2 yamt static void 542 1.2.2.2 yamt issp_init(struct issp_softc *sc) 543 1.2.2.2 yamt { 544 1.2.2.2 yamt uint32_t reg; 545 1.2.2.2 yamt 546 1.2.2.3 yamt /* Initial data bus width is 1-bit. */ 547 1.2.2.3 yamt reg = SSP_RD(sc, HW_SSP_CTRL0); 548 1.2.2.2 yamt reg &= ~(HW_SSP_CTRL0_BUS_WIDTH); 549 1.2.2.3 yamt reg |= __SHIFTIN(BUS_WIDTH_1_BIT, HW_SSP_CTRL0_BUS_WIDTH) | 550 1.2.2.3 yamt HW_SSP_CTRL0_WAIT_FOR_IRQ | HW_SSP_CTRL0_ENABLE; 551 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL0, reg); 552 1.2.2.2 yamt 553 1.2.2.3 yamt /* Set data timeout. */ 554 1.2.2.3 yamt reg = SSP_RD(sc, HW_SSP_TIMING); 555 1.2.2.3 yamt reg &= ~(HW_SSP_TIMING_TIMEOUT); 556 1.2.2.3 yamt reg |= __SHIFTIN(DATA_TIMEOUT, HW_SSP_TIMING_TIMEOUT); 557 1.2.2.3 yamt 558 1.2.2.3 yamt /* Set initial clock rate to minimum. */ 559 1.2.2.3 yamt issp_set_sck(sc, SSP_CLK_MIN * 1000); 560 1.2.2.3 yamt 561 1.2.2.3 yamt SSP_WR(sc, HW_SSP_TIMING, reg); 562 1.2.2.3 yamt /* Enable SD/MMC mode and use use 8-bits per word. */ 563 1.2.2.3 yamt reg = SSP_RD(sc, HW_SSP_CTRL1); 564 1.2.2.2 yamt reg &= ~(HW_SSP_CTRL1_WORD_LENGTH | HW_SSP_CTRL1_SSP_MODE); 565 1.2.2.2 yamt reg |= HW_SSP_CTRL1_POLARITY | 566 1.2.2.2 yamt __SHIFTIN(0x7, HW_SSP_CTRL1_WORD_LENGTH) | 567 1.2.2.2 yamt __SHIFTIN(0x3, HW_SSP_CTRL1_SSP_MODE); 568 1.2.2.3 yamt SSP_WR(sc, HW_SSP_CTRL1, reg); 569 1.2.2.2 yamt 570 1.2.2.2 yamt return; 571 1.2.2.2 yamt } 572 1.2.2.2 yamt 573 1.2.2.2 yamt /* 574 1.2.2.2 yamt * Set SSP_SCK clock rate to the value specified in target. 575 1.2.2.2 yamt * 576 1.2.2.2 yamt * SSP_SCK is calculated as: SSP_CLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)) 577 1.2.2.2 yamt * 578 1.2.2.2 yamt * issp_set_sck find the most suitable CLOCK_DIVIDE and CLOCK_RATE register 579 1.2.2.2 yamt * values for the target clock rate by iterating through all possible register 580 1.2.2.2 yamt * values. 581 1.2.2.2 yamt */ 582 1.2.2.2 yamt static uint32_t 583 1.2.2.2 yamt issp_set_sck(struct issp_softc *sc, uint32_t target) 584 1.2.2.2 yamt { 585 1.2.2.2 yamt uint32_t newclk, found, reg; 586 1.2.2.2 yamt uint8_t div, rate, d, r; 587 1.2.2.2 yamt 588 1.2.2.2 yamt found = div = rate = 0; 589 1.2.2.2 yamt 590 1.2.2.2 yamt for (d = 2; d < 254; d++) { 591 1.2.2.2 yamt for (r = 0; r < 255; r++) { 592 1.2.2.2 yamt newclk = SSP_CLK / (d * (1 + r)); 593 1.2.2.2 yamt if (newclk == target) { 594 1.2.2.2 yamt found = newclk; 595 1.2.2.2 yamt div = d; 596 1.2.2.2 yamt rate = r; 597 1.2.2.2 yamt goto out; 598 1.2.2.2 yamt } 599 1.2.2.2 yamt if (newclk < target && newclk > found) { 600 1.2.2.2 yamt found = newclk; 601 1.2.2.2 yamt div = d; 602 1.2.2.2 yamt rate = r; 603 1.2.2.2 yamt } 604 1.2.2.2 yamt } 605 1.2.2.2 yamt } 606 1.2.2.2 yamt out: 607 1.2.2.3 yamt reg = SSP_RD(sc, HW_SSP_TIMING); 608 1.2.2.2 yamt reg &= ~(HW_SSP_TIMING_CLOCK_DIVIDE | HW_SSP_TIMING_CLOCK_RATE); 609 1.2.2.2 yamt reg |= __SHIFTIN(div, HW_SSP_TIMING_CLOCK_DIVIDE) | 610 1.2.2.2 yamt __SHIFTIN(rate, HW_SSP_TIMING_CLOCK_RATE); 611 1.2.2.3 yamt SSP_WR(sc, HW_SSP_TIMING, reg); 612 1.2.2.2 yamt 613 1.2.2.3 yamt return SSP_CLK / (div * (1 + rate)); 614 1.2.2.2 yamt } 615
Indexes created Mon Oct 27 20:09:55 GMT 2025