imx23_ssp.c revision 1.3
1 /* $Id: imx23_ssp.c,v 1.3 2013/03/03 10:33:56 jkunz Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/types.h> 34 #include <sys/bus.h> 35 #include <sys/cdefs.h> 36 #include <sys/condvar.h> 37 #include <sys/device.h> 38 #include <sys/errno.h> 39 #include <sys/mutex.h> 40 #include <sys/systm.h> 41 42 #include <arm/pic/picvar.h> 43 44 #include <arm/imx/imx23_apbdmavar.h> 45 #include <arm/imx/imx23_icollreg.h> 46 #include <arm/imx/imx23_sspreg.h> 47 #include <arm/imx/imx23var.h> 48 49 #include <dev/sdmmc/sdmmcchip.h> 50 #include <dev/sdmmc/sdmmcreg.h> 51 #include <dev/sdmmc/sdmmcvar.h> 52 53 /* 54 * SD/MMC host controller driver for i.MX23. 55 * 56 * TODO: 57 * 58 * - Add support for SMC_CAPS_AUTO_STOP. 59 */ 60 61 #define DMA_MAXNSEGS ((MAXPHYS / PAGE_SIZE) + 1) 62 63 typedef struct issp_softc { 64 device_t sc_dev; 65 apbdma_softc_t sc_dmac; 66 bus_dma_tag_t sc_dmat; 67 bus_dmamap_t sc_dmamp; 68 bus_size_t sc_chnsiz; 69 bus_dma_segment_t sc_ds[1]; 70 int sc_rseg; 71 bus_space_handle_t sc_hdl; 72 bus_space_tag_t sc_iot; 73 device_t sc_sdmmc; 74 kmutex_t sc_lock; 75 struct kcondvar sc_intr_cv; 76 unsigned int dma_channel; 77 uint32_t sc_dma_error; 78 uint32_t sc_irq_error; 79 uint8_t sc_state; 80 uint8_t sc_bus_width; 81 } *issp_softc_t; 82 83 static int issp_match(device_t, cfdata_t, void *); 84 static void issp_attach(device_t, device_t, void *); 85 static int issp_activate(device_t, enum devact); 86 87 static void issp_reset(struct issp_softc *); 88 static void issp_init(struct issp_softc *); 89 static uint32_t issp_set_sck(struct issp_softc *, uint32_t); 90 static int issp_dma_intr(void *); 91 static int issp_error_intr(void *); 92 static void issp_ack_intr(struct issp_softc *); 93 static void issp_create_dma_cmd_list_multi(issp_softc_t, void *, 94 struct sdmmc_command *); 95 static void issp_create_dma_cmd_list_single(issp_softc_t, void *, 96 struct sdmmc_command *); 97 static void issp_create_dma_cmd_list(issp_softc_t, void *, 98 struct sdmmc_command *); 99 100 /* sdmmc(4) driver chip function prototypes. */ 101 static int issp_host_reset(sdmmc_chipset_handle_t); 102 static uint32_t issp_host_ocr(sdmmc_chipset_handle_t); 103 static int issp_host_maxblklen(sdmmc_chipset_handle_t); 104 static int issp_card_detect(sdmmc_chipset_handle_t); 105 static int issp_write_protect(sdmmc_chipset_handle_t); 106 static int issp_bus_power(sdmmc_chipset_handle_t, uint32_t); 107 static int issp_bus_clock(sdmmc_chipset_handle_t, int); 108 static int issp_bus_width(sdmmc_chipset_handle_t, int); 109 static int issp_bus_rod(sdmmc_chipset_handle_t, int); 110 static void issp_exec_command(sdmmc_chipset_handle_t, 111 struct sdmmc_command *); 112 static void issp_card_enable_intr(sdmmc_chipset_handle_t, int); 113 static void issp_card_intr_ack(sdmmc_chipset_handle_t); 114 115 static struct sdmmc_chip_functions issp_functions = { 116 .host_reset = issp_host_reset, 117 .host_ocr = issp_host_ocr, 118 .host_maxblklen = issp_host_maxblklen, 119 .card_detect = issp_card_detect, 120 .write_protect = issp_write_protect, 121 .bus_power = issp_bus_power, 122 .bus_clock = issp_bus_clock, 123 .bus_width = issp_bus_width, 124 .bus_rod = issp_bus_rod, 125 .exec_command = issp_exec_command, 126 .card_enable_intr = issp_card_enable_intr, 127 .card_intr_ack = issp_card_intr_ack 128 }; 129 130 CFATTACH_DECL3_NEW(ssp, 131 sizeof(struct issp_softc), 132 issp_match, 133 issp_attach, 134 NULL, 135 issp_activate, 136 NULL, 137 NULL, 138 0 139 ); 140 141 #define SSP_SOFT_RST_LOOP 455 /* At least 1 us ... */ 142 143 #define SSP_RD(sc, reg) \ 144 bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg)) 145 #define SSP_WR(sc, reg, val) \ 146 bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val)) 147 148 #define SSP_CLK 96000000 /* CLK_SSP from PLL is 96 MHz */ 149 #define SSP_CLK_MIN 400 /* 400 kHz */ 150 #define SSP_CLK_MAX 48000 /* 48 MHz */ 151 152 /* DATA_TIMEOUT is calculated as: * (1 / SSP_CLK) * (DATA_TIMEOUT * 4096) */ 153 #define DATA_TIMEOUT 0x4240 /* 723ms */ 154 155 #define BUS_WIDTH_1_BIT 0x0 156 #define BUS_WIDTH_4_BIT 0x1 157 #define BUS_WIDTH_8_BIT 0x2 158 159 #define SSP1_ATTACHED 1 160 #define SSP2_ATTACHED 2 161 162 /* Flags for sc_state. */ 163 #define SSP_STATE_IDLE 0 164 #define SSP_STATE_DMA 1 165 166 #define PIO_WORD_CTRL0 0 167 #define PIO_WORD_CMD0 1 168 #define PIO_WORD_CMD1 2 169 170 #define HW_SSP_CTRL1_IRQ_MASK ( \ 171 HW_SSP_CTRL1_SDIO_IRQ | \ 172 HW_SSP_CTRL1_RESP_ERR_IRQ | \ 173 HW_SSP_CTRL1_RESP_TIMEOUT_IRQ | \ 174 HW_SSP_CTRL1_DATA_TIMEOUT_IRQ | \ 175 HW_SSP_CTRL1_DATA_CRC_IRQ | \ 176 HW_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \ 177 HW_SSP_CTRL1_RECV_TIMEOUT_IRQ | \ 178 HW_SSP_CTRL1_FIFO_OVERRUN_IRQ) 179 180 /* SSP does not support over 64k transfer size. */ 181 #define MAX_TRANSFER_SIZE 65536 182 183 static int 184 issp_match(device_t parent, cfdata_t match, void *aux) 185 { 186 struct apb_attach_args *aa = aux; 187 188 if ((aa->aa_addr == HW_SSP1_BASE) && (aa->aa_size == HW_SSP1_SIZE)) 189 return 1; 190 191 if ((aa->aa_addr == HW_SSP2_BASE) && (aa->aa_size == HW_SSP2_SIZE)) 192 return 1; 193 194 return 0; 195 } 196 197 static void 198 issp_attach(device_t parent, device_t self, void *aux) 199 { 200 struct issp_softc *sc = device_private(self); 201 struct apb_softc *sc_parent = device_private(parent); 202 struct apb_attach_args *aa = aux; 203 struct sdmmcbus_attach_args saa; 204 static int ssp_attached = 0; 205 int error; 206 void *intr; 207 208 sc->sc_dev = self; 209 sc->sc_iot = aa->aa_iot; 210 sc->sc_dmat = aa->aa_dmat; 211 212 /* Test if device instance is already attached. */ 213 if (aa->aa_addr == HW_SSP1_BASE && ISSET(ssp_attached, SSP1_ATTACHED)) { 214 aprint_error_dev(sc->sc_dev, "SSP1 already attached\n"); 215 return; 216 } 217 if (aa->aa_addr == HW_SSP2_BASE && ISSET(ssp_attached, SSP2_ATTACHED)) { 218 aprint_error_dev(sc->sc_dev, "SSP2 already attached\n"); 219 return; 220 } 221 222 if (aa->aa_addr == HW_SSP1_BASE) { 223 sc->dma_channel = APBH_DMA_CHANNEL_SSP1; 224 } 225 if (aa->aa_addr == HW_SSP2_BASE) { 226 sc->dma_channel = APBH_DMA_CHANNEL_SSP2; 227 } 228 229 /* This driver requires DMA functionality from the bus. 230 * Parent bus passes handle to the DMA controller instance. */ 231 if (sc_parent->dmac == NULL) { 232 aprint_error_dev(sc->sc_dev, "DMA functionality missing\n"); 233 return; 234 } 235 sc->sc_dmac = device_private(sc_parent->dmac); 236 237 /* Initialize lock. */ 238 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SDMMC); 239 240 /* Condvar to wait interrupt complete. */ 241 cv_init(&sc->sc_intr_cv, "ssp_intr"); 242 243 /* Establish interrupt handlers for SSP errors and SSP DMA. */ 244 if (aa->aa_addr == HW_SSP1_BASE) { 245 intr = intr_establish(IRQ_SSP1_DMA, IPL_SDMMC, IST_LEVEL, 246 issp_dma_intr, sc); 247 if (intr == NULL) { 248 aprint_error_dev(sc->sc_dev, "Unable to establish " 249 "interrupt for SSP1 DMA\n"); 250 return; 251 } 252 intr = intr_establish(IRQ_SSP1_ERROR, IPL_SDMMC, IST_LEVEL, 253 issp_error_intr, sc); 254 if (intr == NULL) { 255 aprint_error_dev(sc->sc_dev, "Unable to establish " 256 "interrupt for SSP1 ERROR\n"); 257 return; 258 } 259 } 260 261 if (aa->aa_addr == HW_SSP2_BASE) { 262 intr = intr_establish(IRQ_SSP2_DMA, IPL_SDMMC, IST_LEVEL, 263 issp_dma_intr, sc); 264 if (intr == NULL) { 265 aprint_error_dev(sc->sc_dev, "Unable to establish " 266 "interrupt for SSP2 DMA\n"); 267 return; 268 } 269 intr = intr_establish(IRQ_SSP2_ERROR, IPL_SDMMC, IST_LEVEL, 270 issp_error_intr, sc); 271 if (intr == NULL) { 272 aprint_error_dev(sc->sc_dev, "Unable to establish " 273 "interrupt for SSP2 ERROR\n"); 274 return; 275 } 276 } 277 278 /* Allocate DMA handle. */ 279 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 1, MAXPHYS, 280 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, &sc->sc_dmamp); 281 if (error) { 282 aprint_error_dev(sc->sc_dev, 283 "Unable to allocate DMA handle\n"); 284 return; 285 } 286 287 /* Allocate memory for DMA command chain. */ 288 sc->sc_chnsiz = sizeof(struct apbdma_command) * 289 (MAX_TRANSFER_SIZE / SDMMC_SECTOR_SIZE); 290 291 error = bus_dmamem_alloc(sc->sc_dmat, sc->sc_chnsiz, PAGE_SIZE, 0, 292 sc->sc_ds, 1, &sc->sc_rseg, BUS_DMA_NOWAIT); 293 if (error) { 294 aprint_error_dev(sc->sc_dev, 295 "Unable to allocate DMA memory\n"); 296 return; 297 } 298 299 /* Initialize DMA channel. */ 300 apbdma_chan_init(sc->sc_dmac, sc->dma_channel); 301 302 /* Map SSP bus space. */ 303 if (bus_space_map(sc->sc_iot, aa->aa_addr, aa->aa_size, 0, 304 &sc->sc_hdl)) { 305 aprint_error_dev(sc->sc_dev, "Unable to map SSP bus space\n"); 306 return; 307 } 308 309 issp_reset(sc); 310 issp_init(sc); 311 312 uint32_t issp_vers = SSP_RD(sc, HW_SSP_VERSION); 313 aprint_normal(": SSP Block v%" __PRIuBIT ".%" __PRIuBIT "\n", 314 __SHIFTOUT(issp_vers, HW_SSP_VERSION_MAJOR), 315 __SHIFTOUT(issp_vers, HW_SSP_VERSION_MINOR)); 316 317 /* Attach sdmmc to ssp bus. */ 318 saa.saa_busname = "sdmmc"; 319 saa.saa_sct = &issp_functions; 320 saa.saa_spi_sct = NULL; 321 saa.saa_sch = sc; 322 saa.saa_dmat = aa->aa_dmat; 323 saa.saa_clkmin = SSP_CLK_MIN; 324 saa.saa_clkmax = SSP_CLK_MAX; 325 saa.saa_caps = SMC_CAPS_DMA | SMC_CAPS_4BIT_MODE | 326 SMC_CAPS_MULTI_SEG_DMA; 327 328 sc->sc_sdmmc = config_found(sc->sc_dev, &saa, NULL); 329 if (sc->sc_sdmmc == NULL) { 330 aprint_error_dev(sc->sc_dev, "unable to attach sdmmc\n"); 331 return; 332 } 333 334 /* Device instance was succesfully attached. */ 335 if (aa->aa_addr == HW_SSP1_BASE) 336 ssp_attached |= SSP1_ATTACHED; 337 if (aa->aa_addr == HW_SSP2_BASE) 338 ssp_attached |= SSP2_ATTACHED; 339 340 return; 341 } 342 343 static int 344 issp_activate(device_t self, enum devact act) 345 { 346 return EOPNOTSUPP; 347 } 348 349 /* 350 * sdmmc chip functions. 351 */ 352 static int 353 issp_host_reset(sdmmc_chipset_handle_t sch) 354 { 355 struct issp_softc *sc = sch; 356 issp_reset(sc); 357 return 0; 358 } 359 360 static uint32_t 361 issp_host_ocr(sdmmc_chipset_handle_t sch) 362 { 363 /* SSP supports at least 3.2 - 3.3v */ 364 return MMC_OCR_3_2V_3_3V; 365 } 366 367 static int 368 issp_host_maxblklen(sdmmc_chipset_handle_t sch) 369 { 370 return 512; 371 } 372 373 /* 374 * Called at the beginning of sdmmc_task_thread to detect the presence 375 * of the SD card. 376 */ 377 static int 378 issp_card_detect(sdmmc_chipset_handle_t sch) 379 { 380 return 1; 381 } 382 383 static int 384 issp_write_protect(sdmmc_chipset_handle_t sch) 385 { 386 /* The device is not write protected. */ 387 return 0; 388 } 389 390 static int 391 issp_bus_power(sdmmc_chipset_handle_t sch, uint32_t ocr) 392 { 393 /* i.MX23 SSP does not support setting bus power. */ 394 return 0; 395 } 396 397 static int 398 issp_bus_clock(sdmmc_chipset_handle_t sch, int clock) 399 { 400 struct issp_softc *sc = sch; 401 uint32_t sck; 402 403 if (clock < SSP_CLK_MIN) 404 sck = issp_set_sck(sc, SSP_CLK_MIN * 1000); 405 else 406 sck = issp_set_sck(sc, clock * 1000); 407 408 /* Notify user if we didn't get the exact clock rate from SSP that was 409 * requested from the SDMMC subsystem. */ 410 if (sck != clock * 1000) { 411 sck = sck / 1000; 412 if (((sck) / 1000) != 0) 413 aprint_normal_dev(sc->sc_dev, "bus clock @ %u.%03u " 414 "MHz\n", sck / 1000, sck % 1000); 415 else 416 aprint_normal_dev(sc->sc_dev, "bus clock @ %u KHz\n", 417 sck % 1000); 418 } 419 420 return 0; 421 } 422 423 static int 424 issp_bus_width(sdmmc_chipset_handle_t sch, int width) 425 { 426 struct issp_softc *sc = sch; 427 428 switch(width) { 429 case(1): 430 sc->sc_bus_width = BUS_WIDTH_1_BIT; 431 break; 432 case(4): 433 sc->sc_bus_width = BUS_WIDTH_4_BIT; 434 break; 435 case(8): 436 sc->sc_bus_width = BUS_WIDTH_8_BIT; 437 break; 438 default: 439 return 1; 440 } 441 442 return 0; 443 } 444 445 static int 446 issp_bus_rod(sdmmc_chipset_handle_t sch, int rod) 447 { 448 /* Go to data transfer mode. */ 449 return 0; 450 } 451 452 static void 453 issp_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd) 454 { 455 issp_softc_t sc = sch; 456 void *dma_chain; 457 int error; 458 459 /* SSP does not support over 64k transfer size. */ 460 if (cmd->c_data != NULL && cmd->c_datalen > MAX_TRANSFER_SIZE) { 461 aprint_error_dev(sc->sc_dev, "transfer size over %d: %d\n", 462 MAX_TRANSFER_SIZE, cmd->c_datalen); 463 cmd->c_error = ENODEV; 464 return; 465 } 466 467 /* Map dma_chain to point allocated previously allocated DMA chain. */ 468 error = bus_dmamem_map(sc->sc_dmat, sc->sc_ds, 1, sc->sc_chnsiz, 469 &dma_chain, BUS_DMA_NOWAIT); 470 if (error) { 471 aprint_error_dev(sc->sc_dev, "bus_dmamem_map: %d\n", error); 472 cmd->c_error = error; 473 goto out; 474 } 475 476 error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamp, dma_chain, 477 sc->sc_chnsiz, NULL, BUS_DMA_NOWAIT|BUS_DMA_WRITE); 478 if (error) { 479 aprint_error_dev(sc->sc_dev, "bus_dmamap_load: %d\n", error); 480 cmd->c_error = error; 481 goto dmamem_unmap; 482 } 483 484 memset(dma_chain, 0, sc->sc_chnsiz); 485 486 /* Setup DMA command chain.*/ 487 if (cmd->c_data != NULL && (cmd->c_datalen / cmd->c_blklen) > 1) { 488 /* Multi block transfer. */ 489 issp_create_dma_cmd_list_multi(sc, dma_chain, cmd); 490 } else if (cmd->c_data != NULL && cmd->c_datalen) { 491 /* Single block transfer. */ 492 issp_create_dma_cmd_list_single(sc, dma_chain, cmd); 493 } else { 494 /* Only command, no data. */ 495 issp_create_dma_cmd_list(sc, dma_chain, cmd); 496 } 497 498 /* Tell DMA controller where it can find just initialized DMA chain. */ 499 apbdma_chan_set_chain(sc->sc_dmac, sc->dma_channel, sc->sc_dmamp); 500 501 /* Synchronize command chain before DMA controller accesses it. */ 502 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamp, 0, sc->sc_chnsiz, 503 BUS_DMASYNC_PREWRITE); 504 505 sc->sc_state = SSP_STATE_DMA; 506 sc->sc_irq_error = 0; 507 sc->sc_dma_error = 0; 508 cmd->c_error = 0; 509 510 mutex_enter(&sc->sc_lock); 511 512 /* Run DMA command chain. */ 513 apbdma_run(sc->sc_dmac, sc->dma_channel); 514 515 /* Wait DMA to complete. */ 516 while (sc->sc_state == SSP_STATE_DMA) 517 cv_wait(&sc->sc_intr_cv, &sc->sc_lock); 518 519 mutex_exit(&sc->sc_lock); 520 521 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamp, 0, sc->sc_chnsiz, 522 BUS_DMASYNC_POSTWRITE); 523 524 if (sc->sc_dma_error) { 525 if (sc->sc_dma_error == DMA_IRQ_TERM) { 526 apbdma_chan_reset(sc->sc_dmac, sc->dma_channel); 527 cmd->c_error = sc->sc_dma_error; 528 } 529 else if (sc->sc_dma_error == DMA_IRQ_BUS_ERROR) { 530 aprint_error_dev(sc->sc_dev, "DMA_IRQ_BUS_ERROR: %d\n", 531 sc->sc_irq_error); 532 cmd->c_error = sc->sc_dma_error; 533 } 534 } 535 536 if (sc->sc_irq_error) { 537 /* Do not log RESP_TIMEOUT_IRQ error if bus width is 0 as it is 538 * expected during SD card initialization phase. */ 539 if (sc->sc_bus_width) { 540 aprint_error_dev(sc->sc_dev, "SSP_ERROR_IRQ: %d\n", 541 sc->sc_irq_error); 542 } 543 else if(!(sc->sc_irq_error & HW_SSP_CTRL1_RESP_TIMEOUT_IRQ)) { 544 aprint_error_dev(sc->sc_dev, "SSP_ERROR_IRQ: %d\n", 545 sc->sc_irq_error); 546 } 547 548 /* Shift unsigned error code so it fits nicely to signed int. */ 549 cmd->c_error = sc->sc_irq_error >> 8; 550 } 551 552 /* Check reponse from the card if such was requested. */ 553 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 554 cmd->c_resp[0] = SSP_RD(sc, HW_SSP_SDRESP0); 555 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 556 cmd->c_resp[1] = SSP_RD(sc, HW_SSP_SDRESP1); 557 cmd->c_resp[2] = SSP_RD(sc, HW_SSP_SDRESP2); 558 cmd->c_resp[3] = SSP_RD(sc, HW_SSP_SDRESP3); 559 /* 560 * Remove CRC7 + LSB by rotating all bits right by 8 to 561 * make sdmmc __bitfield() happy. 562 */ 563 cmd->c_resp[0] >>= 8; /* Remove CRC7 + LSB. */ 564 cmd->c_resp[0] |= (0x000000FF & cmd->c_resp[1]) << 24; 565 cmd->c_resp[1] >>= 8; 566 cmd->c_resp[1] |= (0x000000FF & cmd->c_resp[2]) << 24; 567 cmd->c_resp[2] >>= 8; 568 cmd->c_resp[2] |= (0x000000FF & cmd->c_resp[3]) << 24; 569 cmd->c_resp[3] >>= 8; 570 } 571 } 572 573 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamp); 574 dmamem_unmap: 575 bus_dmamem_unmap(sc->sc_dmat, dma_chain, sc->sc_chnsiz); 576 out: 577 578 return; 579 } 580 581 static void 582 issp_card_enable_intr(sdmmc_chipset_handle_t sch, int irq) 583 { 584 struct issp_softc *sc = sch; 585 aprint_error_dev(sc->sc_dev, "issp_card_enable_intr not implemented\n"); 586 return; 587 } 588 589 static void 590 issp_card_intr_ack(sdmmc_chipset_handle_t sch) 591 { 592 struct issp_softc *sc = sch; 593 aprint_error_dev(sc->sc_dev, "issp_card_intr_ack not implemented\n"); 594 return; 595 } 596 597 /* 598 * Reset the SSP block. 599 * 600 * Inspired by i.MX23 RM "39.3.10 Correct Way to Soft Reset a Block" 601 */ 602 static void 603 issp_reset(struct issp_softc *sc) 604 { 605 unsigned int loop; 606 607 /* Prepare for soft-reset by making sure that SFTRST is not currently 608 * asserted. Also clear CLKGATE so we can wait for its assertion below. 609 */ 610 SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_SFTRST); 611 612 /* Wait at least a microsecond for SFTRST to deassert. */ 613 loop = 0; 614 while ((SSP_RD(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_SFTRST) || 615 (loop < SSP_SOFT_RST_LOOP)) 616 loop++; 617 618 /* Clear CLKGATE so we can wait for its assertion below. */ 619 SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_CLKGATE); 620 621 /* Soft-reset the block. */ 622 SSP_WR(sc, HW_SSP_CTRL0_SET, HW_SSP_CTRL0_SFTRST); 623 624 /* Wait until clock is in the gated state. */ 625 while (!(SSP_RD(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_CLKGATE)); 626 627 /* Bring block out of reset. */ 628 SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_SFTRST); 629 630 loop = 0; 631 while ((SSP_RD(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_SFTRST) || 632 (loop < SSP_SOFT_RST_LOOP)) 633 loop++; 634 635 SSP_WR(sc, HW_SSP_CTRL0_CLR, HW_SSP_CTRL0_CLKGATE); 636 637 /* Wait until clock is in the NON-gated state. */ 638 while (SSP_RD(sc, HW_SSP_CTRL0) & HW_SSP_CTRL0_CLKGATE); 639 640 return; 641 } 642 643 /* 644 * Initialize SSP controller to SD/MMC mode. 645 */ 646 static void 647 issp_init(struct issp_softc *sc) 648 { 649 uint32_t reg; 650 651 reg = SSP_RD(sc, HW_SSP_CTRL0); 652 reg |= HW_SSP_CTRL0_ENABLE; 653 654 /* Initial data bus width is 1-bit. */ 655 reg &= ~(HW_SSP_CTRL0_BUS_WIDTH); 656 reg |= __SHIFTIN(BUS_WIDTH_1_BIT, HW_SSP_CTRL0_BUS_WIDTH) | 657 HW_SSP_CTRL0_WAIT_FOR_IRQ | HW_SSP_CTRL0_ENABLE; 658 SSP_WR(sc, HW_SSP_CTRL0, reg); 659 sc->sc_bus_width = BUS_WIDTH_1_BIT; 660 661 /* Set data timeout. */ 662 reg = SSP_RD(sc, HW_SSP_TIMING); 663 reg &= ~(HW_SSP_TIMING_TIMEOUT); 664 reg |= __SHIFTIN(DATA_TIMEOUT, HW_SSP_TIMING_TIMEOUT); 665 SSP_WR(sc, HW_SSP_TIMING, reg); 666 667 /* Set initial clock rate to minimum. */ 668 issp_set_sck(sc, SSP_CLK_MIN * 1000); 669 670 reg = SSP_RD(sc, HW_SSP_CTRL1); 671 /* Enable all but SDIO IRQ's. */ 672 reg |= HW_SSP_CTRL1_RESP_ERR_IRQ_EN | 673 HW_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN | 674 HW_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN | 675 HW_SSP_CTRL1_DATA_CRC_IRQ_EN | 676 HW_SSP_CTRL1_FIFO_UNDERRUN_EN | 677 HW_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN | 678 HW_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN; 679 reg |= HW_SSP_CTRL1_DMA_ENABLE; 680 reg |= HW_SSP_CTRL1_POLARITY; 681 /* Set SD/MMC mode and use use 8-bits per word. */ 682 reg &= ~(HW_SSP_CTRL1_WORD_LENGTH | HW_SSP_CTRL1_SSP_MODE); 683 reg |= __SHIFTIN(0x7, HW_SSP_CTRL1_WORD_LENGTH) | 684 __SHIFTIN(0x3, HW_SSP_CTRL1_SSP_MODE); 685 SSP_WR(sc, HW_SSP_CTRL1, reg); 686 687 return; 688 } 689 690 /* 691 * Set SSP_SCK clock rate to the value specified in target. 692 * 693 * SSP_SCK is calculated as: SSP_CLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)) 694 * 695 * issp_set_sck finds the most suitable CLOCK_DIVIDE and CLOCK_RATE register 696 * values for the target clock rate by iterating through all possible register 697 * values. 698 */ 699 static uint32_t 700 issp_set_sck(struct issp_softc *sc, uint32_t target) 701 { 702 uint32_t newclk, found, reg; 703 uint8_t div, rate, d, r; 704 705 found = div = rate = 0; 706 707 for (d = 2; d < 254; d++) { 708 for (r = 0; r < 255; r++) { 709 newclk = SSP_CLK / (d * (1 + r)); 710 if (newclk == target) { 711 found = newclk; 712 div = d; 713 rate = r; 714 goto out; 715 } 716 if (newclk < target && newclk > found) { 717 found = newclk; 718 div = d; 719 rate = r; 720 } 721 } 722 } 723 out: 724 reg = SSP_RD(sc, HW_SSP_TIMING); 725 reg &= ~(HW_SSP_TIMING_CLOCK_DIVIDE | HW_SSP_TIMING_CLOCK_RATE); 726 reg |= __SHIFTIN(div, HW_SSP_TIMING_CLOCK_DIVIDE) | 727 __SHIFTIN(rate, HW_SSP_TIMING_CLOCK_RATE); 728 SSP_WR(sc, HW_SSP_TIMING, reg); 729 730 return SSP_CLK / (div * (1 + rate)); 731 } 732 733 /* 734 * IRQ from DMA. 735 */ 736 static int 737 issp_dma_intr(void *arg) 738 { 739 issp_softc_t sc = arg; 740 unsigned int dma_err; 741 742 dma_err = apbdma_intr_status(sc->sc_dmac, sc->dma_channel); 743 744 if (dma_err) { 745 apbdma_ack_error_intr(sc->sc_dmac, sc->dma_channel); 746 } else { 747 apbdma_ack_intr(sc->sc_dmac, sc->dma_channel); 748 } 749 750 mutex_enter(&sc->sc_lock); 751 752 sc->sc_dma_error = dma_err; 753 sc->sc_state = SSP_STATE_IDLE; 754 755 /* Signal thread that interrupt was handled. */ 756 cv_signal(&sc->sc_intr_cv); 757 758 mutex_exit(&sc->sc_lock); 759 760 /* Return 1 to acknowledge IRQ. */ 761 return 1; 762 } 763 764 /* 765 * IRQ from SSP block. 766 * 767 * When SSP receives IRQ it terminates ongoing DMA transfer by issuing DMATERM 768 * signal to DMA block. 769 */ 770 static int 771 issp_error_intr(void *arg) 772 { 773 issp_softc_t sc = arg; 774 775 mutex_enter(&sc->sc_lock); 776 777 sc->sc_irq_error = 778 SSP_RD(sc, HW_SSP_CTRL1) & HW_SSP_CTRL1_IRQ_MASK; 779 780 issp_ack_intr(sc); 781 782 mutex_exit(&sc->sc_lock); 783 784 /* Return 1 to acknowledge IRQ. */ 785 return 1; 786 } 787 788 /* 789 * Acknowledge SSP error IRQ. 790 */ 791 static void 792 issp_ack_intr(struct issp_softc *sc) 793 { 794 795 /* Acknowledge all IRQ's. */ 796 SSP_WR(sc, HW_SSP_CTRL1_CLR, HW_SSP_CTRL1_IRQ_MASK); 797 798 return; 799 } 800 801 /* 802 * Set up multi block DMA transfer. 803 */ 804 static void 805 issp_create_dma_cmd_list_multi(issp_softc_t sc, void *dma_chain, 806 struct sdmmc_command *cmd) 807 { 808 apbdma_command_t dma_cmd; 809 int blocks; 810 int nblk; 811 812 blocks = cmd->c_datalen / cmd->c_blklen; 813 nblk = 0; 814 dma_cmd = dma_chain; 815 816 /* HEAD */ 817 apbdma_cmd_buf(&dma_cmd[nblk], cmd->c_blklen * nblk, cmd->c_dmamap); 818 apbdma_cmd_chain(&dma_cmd[nblk], &dma_cmd[nblk+1], dma_chain, 819 sc->sc_dmamp); 820 821 dma_cmd[nblk].control = 822 __SHIFTIN(cmd->c_blklen, APBDMA_CMD_XFER_COUNT) | 823 __SHIFTIN(3, APBDMA_CMD_CMDPIOWORDS) | APBDMA_CMD_HALTONTERMINATE | 824 APBDMA_CMD_CHAIN; 825 826 if (!ISSET(cmd->c_flags, SCF_RSP_CRC)) { 827 dma_cmd[nblk].pio_words[PIO_WORD_CTRL0] |= 828 HW_SSP_CTRL0_IGNORE_CRC; 829 } 830 831 dma_cmd[nblk].pio_words[PIO_WORD_CTRL0] |= HW_SSP_CTRL0_DATA_XFER | 832 __SHIFTIN(sc->sc_bus_width, HW_SSP_CTRL0_BUS_WIDTH) | 833 HW_SSP_CTRL0_WAIT_FOR_IRQ | 834 __SHIFTIN(cmd->c_datalen, HW_SSP_CTRL0_XFER_COUNT); 835 836 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 837 dma_cmd[nblk].pio_words[PIO_WORD_CTRL0] |= 838 HW_SSP_CTRL0_GET_RESP; 839 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 840 dma_cmd[nblk].pio_words[PIO_WORD_CTRL0] |= 841 HW_SSP_CTRL0_LONG_RESP; 842 } 843 } 844 845 dma_cmd[nblk].pio_words[PIO_WORD_CTRL0] |= HW_SSP_CTRL0_ENABLE; 846 847 dma_cmd[nblk].pio_words[PIO_WORD_CMD0] = 848 __SHIFTIN(ffs(cmd->c_blklen) - 1, HW_SSP_CMD0_BLOCK_SIZE) | 849 __SHIFTIN(blocks - 1, HW_SSP_CMD0_BLOCK_COUNT) | 850 __SHIFTIN(cmd->c_opcode, HW_SSP_CMD0_CMD); 851 852 dma_cmd[nblk].pio_words[PIO_WORD_CMD1] = cmd->c_arg; 853 854 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 855 dma_cmd[nblk].control |= 856 __SHIFTIN(APBDMA_CMD_DMA_WRITE, APBDMA_CMD_COMMAND); 857 dma_cmd[nblk].pio_words[PIO_WORD_CTRL0] |= HW_SSP_CTRL0_READ; 858 } else { 859 dma_cmd[nblk].control |= 860 __SHIFTIN(APBDMA_CMD_DMA_READ, APBDMA_CMD_COMMAND); 861 } 862 863 nblk++; 864 865 /* BODY: Build commands for blocks between head and tail, if any. */ 866 for (; nblk < blocks - 1; nblk++) { 867 868 apbdma_cmd_buf(&dma_cmd[nblk], cmd->c_blklen * nblk, 869 cmd->c_dmamap); 870 871 apbdma_cmd_chain(&dma_cmd[nblk], &dma_cmd[nblk+1], dma_chain, 872 sc->sc_dmamp); 873 874 dma_cmd[nblk].control = 875 __SHIFTIN(cmd->c_blklen, APBDMA_CMD_XFER_COUNT) | 876 APBDMA_CMD_HALTONTERMINATE | APBDMA_CMD_CHAIN; 877 878 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 879 dma_cmd[nblk].control |= 880 __SHIFTIN(APBDMA_CMD_DMA_WRITE, 881 APBDMA_CMD_COMMAND); 882 } else { 883 dma_cmd[nblk].control |= 884 __SHIFTIN(APBDMA_CMD_DMA_READ, APBDMA_CMD_COMMAND); 885 } 886 } 887 888 /* TAIL 889 * 890 * TODO: Send CMD12/STOP with last DMA command to support 891 * SMC_CAPS_AUTO_STOP. 892 */ 893 apbdma_cmd_buf(&dma_cmd[nblk], cmd->c_blklen * nblk, cmd->c_dmamap); 894 /* next = NULL */ 895 dma_cmd[nblk].control = 896 __SHIFTIN(cmd->c_blklen, APBDMA_CMD_XFER_COUNT) | 897 APBDMA_CMD_HALTONTERMINATE | APBDMA_CMD_WAIT4ENDCMD | 898 APBDMA_CMD_SEMAPHORE | APBDMA_CMD_IRQONCMPLT; 899 900 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 901 dma_cmd[nblk].control |= __SHIFTIN(APBDMA_CMD_DMA_WRITE, 902 APBDMA_CMD_COMMAND); 903 } else { 904 dma_cmd[nblk].control |= __SHIFTIN(APBDMA_CMD_DMA_READ, 905 APBDMA_CMD_COMMAND); 906 } 907 908 return; 909 } 910 911 /* 912 * Set up single block DMA transfer. 913 */ 914 static void 915 issp_create_dma_cmd_list_single(issp_softc_t sc, void *dma_chain, 916 struct sdmmc_command *cmd) 917 { 918 apbdma_command_t dma_cmd; 919 920 dma_cmd = dma_chain; 921 922 dma_cmd[0].control = __SHIFTIN(cmd->c_datalen, APBDMA_CMD_XFER_COUNT) | 923 __SHIFTIN(3, APBDMA_CMD_CMDPIOWORDS) | 924 APBDMA_CMD_HALTONTERMINATE | APBDMA_CMD_WAIT4ENDCMD | 925 APBDMA_CMD_SEMAPHORE | APBDMA_CMD_IRQONCMPLT; 926 927 /* Transfer single block to the beginning of the DMA buffer. */ 928 apbdma_cmd_buf(&dma_cmd[0], 0, cmd->c_dmamap); 929 930 if (!ISSET(cmd->c_flags, SCF_RSP_CRC)) { 931 dma_cmd[0].pio_words[PIO_WORD_CTRL0] |= 932 HW_SSP_CTRL0_IGNORE_CRC; 933 } 934 935 dma_cmd[0].pio_words[PIO_WORD_CTRL0] |= 936 HW_SSP_CTRL0_DATA_XFER | 937 __SHIFTIN(sc->sc_bus_width, HW_SSP_CTRL0_BUS_WIDTH) | 938 HW_SSP_CTRL0_WAIT_FOR_IRQ | 939 __SHIFTIN(cmd->c_datalen, HW_SSP_CTRL0_XFER_COUNT); 940 941 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 942 dma_cmd[0].pio_words[PIO_WORD_CTRL0] |= HW_SSP_CTRL0_GET_RESP; 943 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 944 dma_cmd[0].pio_words[PIO_WORD_CTRL0] |= 945 HW_SSP_CTRL0_LONG_RESP; 946 } 947 } 948 949 dma_cmd[0].pio_words[PIO_WORD_CTRL0] |= HW_SSP_CTRL0_ENABLE; 950 951 dma_cmd[0].pio_words[PIO_WORD_CMD0] = 952 HW_SSP_CMD0_APPEND_8CYC | 953 __SHIFTIN(cmd->c_opcode, HW_SSP_CMD0_CMD); 954 dma_cmd[0].pio_words[PIO_WORD_CMD1] = cmd->c_arg; 955 956 if (ISSET(cmd->c_flags, SCF_CMD_READ)) { 957 dma_cmd[0].control |= 958 __SHIFTIN(APBDMA_CMD_DMA_WRITE, APBDMA_CMD_COMMAND); 959 dma_cmd[0].pio_words[PIO_WORD_CTRL0] |= HW_SSP_CTRL0_READ; 960 } else { 961 dma_cmd[0].control |= 962 __SHIFTIN(APBDMA_CMD_DMA_READ, APBDMA_CMD_COMMAND); 963 } 964 965 return; 966 } 967 968 /* 969 * Do DMA PIO (issue CMD). No block transfers. 970 */ 971 static void 972 issp_create_dma_cmd_list(issp_softc_t sc, void *dma_chain, 973 struct sdmmc_command *cmd) 974 { 975 apbdma_command_t dma_cmd; 976 977 dma_cmd = dma_chain; 978 979 dma_cmd[0].control = __SHIFTIN(3, APBDMA_CMD_CMDPIOWORDS) | 980 APBDMA_CMD_HALTONTERMINATE | APBDMA_CMD_WAIT4ENDCMD | 981 APBDMA_CMD_SEMAPHORE | APBDMA_CMD_IRQONCMPLT | 982 __SHIFTIN(APBDMA_CMD_NO_DMA_XFER, APBDMA_CMD_COMMAND); 983 984 if (!ISSET(cmd->c_flags, SCF_RSP_CRC)) { 985 dma_cmd[0].pio_words[PIO_WORD_CTRL0] |= 986 HW_SSP_CTRL0_IGNORE_CRC; 987 } 988 989 dma_cmd[0].pio_words[PIO_WORD_CTRL0] |= 990 __SHIFTIN(sc->sc_bus_width, HW_SSP_CTRL0_BUS_WIDTH) | 991 HW_SSP_CTRL0_WAIT_FOR_IRQ; 992 993 if (ISSET(cmd->c_flags, SCF_RSP_PRESENT)) { 994 dma_cmd[0].pio_words[PIO_WORD_CTRL0] |= HW_SSP_CTRL0_GET_RESP; 995 if (ISSET(cmd->c_flags, SCF_RSP_136)) { 996 dma_cmd[0].pio_words[PIO_WORD_CTRL0] |= 997 HW_SSP_CTRL0_LONG_RESP; 998 } 999 } 1000 1001 dma_cmd[0].pio_words[PIO_WORD_CTRL0] |= HW_SSP_CTRL0_ENABLE; 1002 1003 dma_cmd[0].pio_words[PIO_WORD_CMD0] = 1004 __SHIFTIN(cmd->c_opcode, HW_SSP_CMD0_CMD); 1005 dma_cmd[0].pio_words[PIO_WORD_CMD1] = cmd->c_arg; 1006 1007 return; 1008 } 1009
Indexes created Tue Sep 30 20:09:53 GMT 2025