imx23_timrot.c revision 1.2.2.4
1 1.2.2.4 yamt /* $Id: imx23_timrot.c,v 1.2.2.4 2014/05/22 11:39:32 yamt Exp $ */ 2 1.2.2.2 yamt 3 1.2.2.2 yamt /* 4 1.2.2.2 yamt * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 1.2.2.2 yamt * All rights reserved. 6 1.2.2.2 yamt * 7 1.2.2.2 yamt * This code is derived from software contributed to The NetBSD Foundation 8 1.2.2.2 yamt * by Petri Laakso. 9 1.2.2.2 yamt * 10 1.2.2.2 yamt * Redistribution and use in source and binary forms, with or without 11 1.2.2.2 yamt * modification, are permitted provided that the following conditions 12 1.2.2.2 yamt * are met: 13 1.2.2.2 yamt * 1. Redistributions of source code must retain the above copyright 14 1.2.2.2 yamt * notice, this list of conditions and the following disclaimer. 15 1.2.2.2 yamt * 2. Redistributions in binary form must reproduce the above copyright 16 1.2.2.2 yamt * notice, this list of conditions and the following disclaimer in the 17 1.2.2.2 yamt * documentation and/or other materials provided with the distribution. 18 1.2.2.2 yamt * 19 1.2.2.2 yamt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.2.2.2 yamt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.2.2.2 yamt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.2.2.2 yamt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.2.2.2 yamt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.2.2.2 yamt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.2.2.2 yamt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.2.2.2 yamt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.2.2.2 yamt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.2.2.2 yamt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.2.2.2 yamt * POSSIBILITY OF SUCH DAMAGE. 30 1.2.2.2 yamt */ 31 1.2.2.2 yamt 32 1.2.2.2 yamt #include <sys/param.h> 33 1.2.2.2 yamt #include <sys/bus.h> 34 1.2.2.2 yamt #include <sys/device.h> 35 1.2.2.2 yamt #include <sys/errno.h> 36 1.2.2.2 yamt #include <sys/systm.h> 37 1.2.2.2 yamt 38 1.2.2.2 yamt #include <arm/pic/picvar.h> 39 1.2.2.2 yamt 40 1.2.2.2 yamt #include <arm/imx/imx23_icollreg.h> 41 1.2.2.2 yamt #include <arm/imx/imx23_timrotreg.h> 42 1.2.2.2 yamt #include <arm/imx/imx23var.h> 43 1.2.2.2 yamt 44 1.2.2.2 yamt extern int hz; 45 1.2.2.2 yamt extern int stathz; 46 1.2.2.2 yamt 47 1.2.2.2 yamt static int timrot_match(device_t, cfdata_t, void *); 48 1.2.2.2 yamt static void timrot_attach(device_t, device_t, void *); 49 1.2.2.2 yamt static int timrot_activate(device_t, enum devact); 50 1.2.2.2 yamt 51 1.2.2.2 yamt static void timrot_reset(void); 52 1.2.2.2 yamt 53 1.2.2.2 yamt /* 54 1.2.2.2 yamt * Timer IRQ handler definitions. 55 1.2.2.2 yamt */ 56 1.2.2.2 yamt static int systimer_irq(void *); 57 1.2.2.2 yamt static int stattimer_irq(void *); 58 1.2.2.2 yamt 59 1.2.2.2 yamt void cpu_initclocks(void); 60 1.2.2.2 yamt void setstatclockrate(int); 61 1.2.2.2 yamt 62 1.2.2.2 yamt /* Allocated for each timer instance. */ 63 1.2.2.2 yamt struct timrot_softc { 64 1.2.2.2 yamt device_t sc_dev; 65 1.2.2.2 yamt bus_space_tag_t sc_iot; 66 1.2.2.2 yamt bus_space_handle_t sc_hdl; 67 1.2.2.2 yamt int8_t sc_irq; 68 1.2.2.2 yamt int (*irq_handler)(void *); 69 1.2.2.2 yamt int freq; 70 1.2.2.2 yamt }; 71 1.2.2.2 yamt 72 1.2.2.2 yamt static bus_space_tag_t timrot_iot; 73 1.2.2.2 yamt static bus_space_handle_t timrot_hdl; 74 1.2.2.2 yamt 75 1.2.2.2 yamt CFATTACH_DECL3_NEW(timrot, 76 1.2.2.2 yamt sizeof(struct timrot_softc), 77 1.2.2.2 yamt timrot_match, 78 1.2.2.2 yamt timrot_attach, 79 1.2.2.2 yamt NULL, 80 1.2.2.2 yamt timrot_activate, 81 1.2.2.2 yamt NULL, 82 1.2.2.2 yamt NULL, 83 1.2.2.2 yamt 0); 84 1.2.2.2 yamt 85 1.2.2.2 yamt #define MAX_TIMERS 4 86 1.2.2.2 yamt #define SYS_TIMER 0 87 1.2.2.2 yamt #define STAT_TIMER 1 88 1.2.2.2 yamt #define SCHED_TIMER 2 89 1.2.2.2 yamt 90 1.2.2.2 yamt struct timrot_softc *timer_sc[MAX_TIMERS]; 91 1.2.2.2 yamt 92 1.2.2.2 yamt static void timer_init(struct timrot_softc *); 93 1.2.2.2 yamt 94 1.2.2.2 yamt #define TIMROT_SOFT_RST_LOOP 455 /* At least 1 us ... */ 95 1.2.2.2 yamt #define TIMROT_READ(reg) \ 96 1.2.2.2 yamt bus_space_read_4(timrot_iot, timrot_hdl, (reg)) 97 1.2.2.2 yamt #define TIMROT_WRITE(reg, val) \ 98 1.2.2.2 yamt bus_space_write_4(timrot_iot, timrot_hdl, (reg), (val)) 99 1.2.2.2 yamt 100 1.2.2.2 yamt #define TIMER_REGS_SIZE 0x20 101 1.2.2.2 yamt 102 1.2.2.2 yamt #define TIMER_CTRL 0x00 103 1.2.2.2 yamt #define TIMER_CTRL_SET 0x04 104 1.2.2.2 yamt #define TIMER_CTRL_CLR 0x08 105 1.2.2.2 yamt #define TIMER_CTRL_TOG 0x0C 106 1.2.2.2 yamt #define TIMER_COUNT 0x10 107 1.2.2.2 yamt 108 1.2.2.2 yamt #define TIMER_READ(sc, reg) \ 109 1.2.2.2 yamt bus_space_read_4(sc->sc_iot, sc->sc_hdl, (reg)) 110 1.2.2.2 yamt #define TIMER_WRITE(sc, reg, val) \ 111 1.2.2.2 yamt bus_space_write_4(sc->sc_iot, sc->sc_hdl, (reg), (val)) 112 1.2.2.2 yamt #define TIMER_WRITE_2(sc, reg, val) \ 113 1.2.2.2 yamt bus_space_write_2(sc->sc_iot, sc->sc_hdl, (reg), (val)) 114 1.2.2.2 yamt 115 1.2.2.2 yamt #define SELECT_32KHZ 0x8 /* Use 32kHz clock source. */ 116 1.2.2.2 yamt #define SOURCE_32KHZ_HZ 32000 /* Above source in Hz. */ 117 1.2.2.2 yamt 118 1.2.2.2 yamt #define IRQ HW_TIMROT_TIMCTRL0_IRQ 119 1.2.2.2 yamt #define IRQ_EN HW_TIMROT_TIMCTRL0_IRQ_EN 120 1.2.2.2 yamt #define UPDATE HW_TIMROT_TIMCTRL0_UPDATE 121 1.2.2.2 yamt #define RELOAD HW_TIMROT_TIMCTRL0_RELOAD 122 1.2.2.2 yamt 123 1.2.2.2 yamt static int 124 1.2.2.2 yamt timrot_match(device_t parent, cfdata_t match, void *aux) 125 1.2.2.2 yamt { 126 1.2.2.2 yamt struct apb_attach_args *aa = aux; 127 1.2.2.2 yamt 128 1.2.2.2 yamt if ((aa->aa_addr == HW_TIMROT_BASE + HW_TIMROT_TIMCTRL0 129 1.2.2.2 yamt && aa->aa_size == TIMER_REGS_SIZE)) 130 1.2.2.2 yamt return 1; 131 1.2.2.2 yamt 132 1.2.2.2 yamt if ((aa->aa_addr == HW_TIMROT_BASE + HW_TIMROT_TIMCTRL1 133 1.2.2.2 yamt && aa->aa_size == TIMER_REGS_SIZE)) 134 1.2.2.2 yamt return 1; 135 1.2.2.2 yamt 136 1.2.2.2 yamt #if 0 137 1.2.2.2 yamt if ((aa->aa_addr == HW_TIMROT_BASE + HW_TIMROT_TIMCTRL2 138 1.2.2.2 yamt && aa->aa_size == TIMER_REGS_SIZE)) 139 1.2.2.2 yamt return 1; 140 1.2.2.2 yamt 141 1.2.2.2 yamt if ((aa->aa_addr == HW_TIMROT_BASE + HW_TIMROT_TIMCTRL3 142 1.2.2.2 yamt && aa->aa_size == TIMER_REGS_SIZE)) 143 1.2.2.2 yamt return 1; 144 1.2.2.2 yamt #endif 145 1.2.2.2 yamt return 0; 146 1.2.2.2 yamt } 147 1.2.2.2 yamt 148 1.2.2.2 yamt static void 149 1.2.2.2 yamt timrot_attach(device_t parent, device_t self, void *aux) 150 1.2.2.2 yamt { 151 1.2.2.2 yamt struct apb_attach_args *aa = aux; 152 1.2.2.2 yamt struct timrot_softc *sc = device_private(self); 153 1.2.2.2 yamt static int timrot_attached = 0; 154 1.2.2.2 yamt 155 1.2.2.2 yamt if (!timrot_attached) { 156 1.2.2.2 yamt timrot_iot = aa->aa_iot; 157 1.2.2.2 yamt if (bus_space_map(timrot_iot, HW_TIMROT_BASE, HW_TIMROT_SIZE, 158 1.2.2.2 yamt 0, &timrot_hdl)) { 159 1.2.2.2 yamt aprint_error_dev(sc->sc_dev, 160 1.2.2.2 yamt "unable to map bus space\n"); 161 1.2.2.2 yamt return; 162 1.2.2.2 yamt } 163 1.2.2.2 yamt timrot_reset(); 164 1.2.2.2 yamt timrot_attached = 1; 165 1.2.2.2 yamt } 166 1.2.2.2 yamt 167 1.2.2.2 yamt if (aa->aa_addr == HW_TIMROT_BASE + HW_TIMROT_TIMCTRL0 168 1.2.2.2 yamt && aa->aa_size == TIMER_REGS_SIZE 169 1.2.2.2 yamt && timer_sc[SYS_TIMER] == NULL) { 170 1.2.2.2 yamt if (bus_space_subregion(timrot_iot, timrot_hdl, 171 1.2.2.2 yamt HW_TIMROT_TIMCTRL0, TIMER_REGS_SIZE, 172 1.2.2.2 yamt &sc->sc_hdl)) { 173 1.2.2.2 yamt aprint_error_dev(sc->sc_dev, 174 1.2.2.2 yamt "unable to map subregion\n"); 175 1.2.2.2 yamt return; 176 1.2.2.2 yamt } 177 1.2.2.2 yamt 178 1.2.2.2 yamt sc->sc_iot = aa->aa_iot; 179 1.2.2.2 yamt sc->sc_irq = aa->aa_irq; 180 1.2.2.2 yamt sc->irq_handler = &systimer_irq; 181 1.2.2.2 yamt sc->freq = hz; 182 1.2.2.2 yamt 183 1.2.2.2 yamt timer_sc[SYS_TIMER] = sc; 184 1.2.2.2 yamt 185 1.2.2.2 yamt aprint_normal("\n"); 186 1.2.2.2 yamt 187 1.2.2.2 yamt } else if (aa->aa_addr == HW_TIMROT_BASE + HW_TIMROT_TIMCTRL1 188 1.2.2.2 yamt && aa->aa_size == TIMER_REGS_SIZE 189 1.2.2.2 yamt && timer_sc[STAT_TIMER] == NULL) { 190 1.2.2.2 yamt if (bus_space_subregion(timrot_iot, timrot_hdl, 191 1.2.2.2 yamt HW_TIMROT_TIMCTRL1, TIMER_REGS_SIZE, &sc->sc_hdl)) { 192 1.2.2.2 yamt aprint_error_dev(sc->sc_dev, 193 1.2.2.2 yamt "unable to map subregion\n"); 194 1.2.2.2 yamt return; 195 1.2.2.2 yamt } 196 1.2.2.2 yamt 197 1.2.2.2 yamt sc->sc_iot = aa->aa_iot; 198 1.2.2.2 yamt sc->sc_irq = aa->aa_irq; 199 1.2.2.2 yamt sc->irq_handler = &stattimer_irq; 200 1.2.2.2 yamt stathz = (hz>>1); 201 1.2.2.2 yamt sc->freq = stathz; 202 1.2.2.2 yamt 203 1.2.2.2 yamt timer_sc[STAT_TIMER] = sc; 204 1.2.2.2 yamt 205 1.2.2.2 yamt aprint_normal("\n"); 206 1.2.2.2 yamt } 207 1.2.2.2 yamt 208 1.2.2.2 yamt return; 209 1.2.2.2 yamt } 210 1.2.2.2 yamt 211 1.2.2.2 yamt static int 212 1.2.2.2 yamt timrot_activate(device_t self, enum devact act) 213 1.2.2.2 yamt { 214 1.2.2.2 yamt return EOPNOTSUPP; 215 1.2.2.2 yamt } 216 1.2.2.2 yamt 217 1.2.2.2 yamt /* 218 1.2.2.2 yamt * cpu_initclock is called once at the boot time. 219 1.2.2.2 yamt */ 220 1.2.2.2 yamt void 221 1.2.2.2 yamt cpu_initclocks(void) 222 1.2.2.2 yamt { 223 1.2.2.2 yamt if (timer_sc[SYS_TIMER] != NULL) 224 1.2.2.2 yamt timer_init(timer_sc[SYS_TIMER]); 225 1.2.2.2 yamt 226 1.2.2.2 yamt if (timer_sc[STAT_TIMER] != NULL) 227 1.2.2.2 yamt timer_init(timer_sc[STAT_TIMER]); 228 1.2.2.2 yamt 229 1.2.2.2 yamt return; 230 1.2.2.2 yamt } 231 1.2.2.2 yamt 232 1.2.2.2 yamt /* 233 1.2.2.2 yamt * Change statclock rate when profiling takes place. 234 1.2.2.2 yamt */ 235 1.2.2.2 yamt void 236 1.2.2.2 yamt setstatclockrate(int newhz) 237 1.2.2.2 yamt { 238 1.2.2.2 yamt struct timrot_softc *sc = timer_sc[STAT_TIMER]; 239 1.2.2.2 yamt sc->freq = newhz; 240 1.2.2.2 yamt 241 1.2.2.2 yamt TIMER_WRITE_2(sc, TIMER_COUNT, 242 1.2.2.4 yamt __SHIFTIN(SOURCE_32KHZ_HZ / sc->freq - 1, 243 1.2.2.2 yamt HW_TIMROT_TIMCOUNT0_FIXED_COUNT)); 244 1.2.2.2 yamt 245 1.2.2.2 yamt return; 246 1.2.2.2 yamt } 247 1.2.2.2 yamt 248 1.2.2.2 yamt /* 249 1.2.2.2 yamt * Generic timer initialization function. 250 1.2.2.2 yamt */ 251 1.2.2.2 yamt static void 252 1.2.2.2 yamt timer_init(struct timrot_softc *sc) 253 1.2.2.2 yamt { 254 1.2.2.2 yamt uint32_t ctrl; 255 1.2.2.2 yamt 256 1.2.2.2 yamt TIMER_WRITE_2(sc, TIMER_COUNT, 257 1.2.2.4 yamt __SHIFTIN(SOURCE_32KHZ_HZ / sc->freq - 1, 258 1.2.2.2 yamt HW_TIMROT_TIMCOUNT0_FIXED_COUNT)); 259 1.2.2.2 yamt ctrl = IRQ_EN | UPDATE | RELOAD | SELECT_32KHZ; 260 1.2.2.2 yamt TIMER_WRITE(sc, TIMER_CTRL, ctrl); 261 1.2.2.2 yamt 262 1.2.2.2 yamt intr_establish(sc->sc_irq, IPL_SCHED, IST_LEVEL, sc->irq_handler, NULL); 263 1.2.2.2 yamt 264 1.2.2.2 yamt return; 265 1.2.2.2 yamt } 266 1.2.2.2 yamt 267 1.2.2.2 yamt /* 268 1.2.2.2 yamt * Timer IRQ handlers. 269 1.2.2.2 yamt */ 270 1.2.2.2 yamt static int 271 1.2.2.2 yamt systimer_irq(void *frame) 272 1.2.2.2 yamt { 273 1.2.2.2 yamt hardclock(frame); 274 1.2.2.2 yamt 275 1.2.2.2 yamt TIMER_WRITE(timer_sc[SYS_TIMER], TIMER_CTRL_CLR, IRQ); 276 1.2.2.2 yamt 277 1.2.2.2 yamt return 1; 278 1.2.2.2 yamt } 279 1.2.2.2 yamt 280 1.2.2.2 yamt static int 281 1.2.2.2 yamt stattimer_irq(void *frame) 282 1.2.2.2 yamt { 283 1.2.2.2 yamt statclock(frame); 284 1.2.2.2 yamt 285 1.2.2.2 yamt TIMER_WRITE(timer_sc[STAT_TIMER], TIMER_CTRL_CLR, IRQ); 286 1.2.2.2 yamt 287 1.2.2.2 yamt return 1; 288 1.2.2.2 yamt } 289 1.2.2.2 yamt 290 1.2.2.2 yamt /* 291 1.2.2.2 yamt * Reset the TIMROT block. 292 1.2.2.2 yamt * 293 1.2.2.3 yamt * Inspired by i.MX23 RM "39.3.10 Correct Way to Soft Reset a Block" 294 1.2.2.2 yamt */ 295 1.2.2.2 yamt static void 296 1.2.2.2 yamt timrot_reset(void) 297 1.2.2.2 yamt { 298 1.2.2.2 yamt unsigned int loop; 299 1.2.2.2 yamt 300 1.2.2.2 yamt /* Prepare for soft-reset by making sure that SFTRST is not currently 301 1.2.2.2 yamt * asserted. Also clear CLKGATE so we can wait for its assertion below. 302 1.2.2.2 yamt */ 303 1.2.2.2 yamt TIMROT_WRITE(HW_TIMROT_ROTCTRL_CLR, HW_TIMROT_ROTCTRL_SFTRST); 304 1.2.2.2 yamt 305 1.2.2.2 yamt /* Wait at least a microsecond for SFTRST to deassert. */ 306 1.2.2.2 yamt loop = 0; 307 1.2.2.2 yamt while ((TIMROT_READ(HW_TIMROT_ROTCTRL) & HW_TIMROT_ROTCTRL_SFTRST) || 308 1.2.2.2 yamt (loop < TIMROT_SOFT_RST_LOOP)) 309 1.2.2.2 yamt loop++; 310 1.2.2.2 yamt 311 1.2.2.2 yamt /* Clear CLKGATE so we can wait for its assertion below. */ 312 1.2.2.2 yamt TIMROT_WRITE(HW_TIMROT_ROTCTRL_CLR, HW_TIMROT_ROTCTRL_CLKGATE); 313 1.2.2.2 yamt 314 1.2.2.2 yamt /* Soft-reset the block. */ 315 1.2.2.2 yamt TIMROT_WRITE(HW_TIMROT_ROTCTRL_SET, HW_TIMROT_ROTCTRL_SFTRST); 316 1.2.2.2 yamt 317 1.2.2.2 yamt /* Wait until clock is in the gated state. */ 318 1.2.2.2 yamt while (!(TIMROT_READ(HW_TIMROT_ROTCTRL) & HW_TIMROT_ROTCTRL_CLKGATE)); 319 1.2.2.2 yamt 320 1.2.2.2 yamt /* Bring block out of reset. */ 321 1.2.2.2 yamt TIMROT_WRITE(HW_TIMROT_ROTCTRL_CLR, HW_TIMROT_ROTCTRL_SFTRST); 322 1.2.2.2 yamt 323 1.2.2.2 yamt loop = 0; 324 1.2.2.2 yamt while ((TIMROT_READ(HW_TIMROT_ROTCTRL) & HW_TIMROT_ROTCTRL_SFTRST) || 325 1.2.2.2 yamt (loop < TIMROT_SOFT_RST_LOOP)) 326 1.2.2.2 yamt loop++; 327 1.2.2.2 yamt 328 1.2.2.2 yamt TIMROT_WRITE(HW_TIMROT_ROTCTRL_CLR, HW_TIMROT_ROTCTRL_CLKGATE); 329 1.2.2.2 yamt /* Wait until clock is in the NON-gated state. */ 330 1.2.2.2 yamt while (TIMROT_READ(HW_TIMROT_ROTCTRL) & HW_TIMROT_ROTCTRL_CLKGATE); 331 1.2.2.2 yamt 332 1.2.2.2 yamt return; 333 1.2.2.2 yamt } 334
Indexes created Sat Oct 25 16:10:12 GMT 2025