imx31_clock.c revision 1.1 1 /* $NetBSD: imx31_clock.c,v 1.1 2010/11/13 06:51:37 bsh Exp $ */
2 /*
3 * Copyright (c) 2009,2010 Genetec corp. All rights reserved.
4 * Written by Hashimoto Kenichi for Genetec corp.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
31 #include <sys/evcnt.h>
32 #include <sys/atomic.h>
33 #include <sys/time.h>
34 #include <sys/timetc.h>
35
36 #include <sys/types.h>
37 #include <sys/device.h>
38
39 #include <machine/intr.h>
40 #include <machine/bus.h>
41
42 #include <arm/cpu.h>
43 #include <arm/armreg.h>
44 #include <arm/cpufunc.h>
45
46 #include <arm/imx/imx31reg.h>
47 #include <arm/imx/imx31var.h>
48 #include <arm/imx/imx31_ccmvar.h>
49 #include <arm/imx/imxclockvar.h>
50
51 static int imxclock_match(device_t, struct cfdata *, void *);
52 static void imxclock_attach(device_t, device_t, void *);
53
54 struct imxclock_softc *epit1_sc = NULL;
55 struct imxclock_softc *epit2_sc = NULL;
56
57 CFATTACH_DECL_NEW(imxclock, sizeof(struct imxclock_softc),
58 imxclock_match, imxclock_attach, NULL, NULL);
59
60 static int
61 imxclock_match(device_t parent, struct cfdata *match, void *aux)
62 {
63 struct aips_attach_args *aipsa = aux;
64
65 if ( (aipsa->aipsa_addr != EPIT1_BASE) &&
66 (aipsa->aipsa_addr != EPIT2_BASE) ) {
67 return 0;
68 }
69
70 return 2;
71 }
72
73 static void
74 imxclock_attach(device_t parent, device_t self, void *aux)
75 {
76 struct imxclock_softc *sc = device_private(self);
77 struct aips_attach_args *aipsa = aux;
78
79 aprint_normal("\n");
80
81 sc->sc_dev = self;
82 sc->sc_iot = aipsa->aipsa_memt;
83 sc->sc_intr = aipsa->aipsa_intr;
84
85 KASSERT((sc->sc_intr == IRQ_EPIT1) || (sc->sc_intr == IRQ_EPIT2));
86
87 switch ( aipsa->aipsa_addr ) {
88 case EPIT1_BASE:
89 epit1_sc = sc;
90 break;
91 case EPIT2_BASE:
92 epit2_sc = sc;
93 break;
94 default:
95 panic("%s: invalid address %p", self->dv_xname, (void *)aipsa->aipsa_addr);
96 break;
97 }
98
99 if (bus_space_map(aipsa->aipsa_memt, aipsa->aipsa_addr,
100 aipsa->aipsa_size, 0, &sc->sc_ioh)) {
101 panic("%s: Cannot map registers", device_xname(self));
102 }
103 }
104
105 int
106 imxclock_get_timerfreq(struct imxclock_softc *sc)
107 {
108 struct imx31_clocks clk;
109 imx31_get_clocks(&clk);
110
111 return clk.ipg_clk;
112 }
113
114
115