imx31_icu.c revision 1.1.2.1
1 /*- 2 * Copyright (c) 2007 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the NetBSD 19 * Foundation, Inc. and its contributors. 20 * 4. Neither the name of The NetBSD Foundation nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: imx31_icu.c,v 1.1.2.1 2007/08/29 05:24:23 matt Exp $"); 38 39 #define _INTR_PRIVATE 40 41 #include <sys/param.h> 42 #include <sys/evcnt.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <machine/intr.h> 47 48 #include <arm/cpu.h> 49 #include <arm/armreg.h> 50 #include <arm/cpufunc.h> 51 52 #include <machine/atomic.h> 53 #include <machine/bus.h> 54 55 #include <arm/imx/imx31_intrreg.h> 56 57 static void avic_enable_irq(struct pic_softc *, irq); 58 static void avic_disable_irq(struct pic_softc *, irq); 59 static int avic_get_irq(struct pic_softc *); 60 static void avic_establish_irq(struct pic_softc *, int, int, int); 61 static void avic_source_name(struct pic_softc *, int); 62 63 const struct pic_ops avic_pic_ops = { 64 .pic_enable_irq = avic_enable_irq, 65 .pic_reeable_irq = avic_enable_irq, 66 .pic_disable_irq = avic_disable_irq, 67 .pic_establish_irq = avic_establish_irq, 68 .pic_source_name = avic_source_name 69 }; 70 71 struct avic_softc { 72 struct pic_softc avic_pic; 73 bus_space_tag_t avic_memt; 74 bus_space_handle_t avic_memh; 75 } avic_pic = { 76 .avic_pic = { 77 .pic_ops = &avic_pic_ops, 78 .pic_numintrs = 64, 79 .pic_name = "avic", 80 }, 81 }; 82 83 void 84 avic_enable_irq(struct pic_softc *pic, int irq) 85 { 86 struct avic_softc * const avic = (void *) pic; 87 INTC_WRITE(&avic_softc, INTR_ENNUM, irq); 88 } 89 90 void 91 avic_disable_irq(struct pic_softc *pic, int irq) 92 { 93 struct avic_softc * const avic = (void *) pic; 94 INTC_WRITE(&avic_softc, INTR_DISNUM, irq); 95 } 96 97 void 98 avic_establish(struct pic_softc *pic, int irq, int ipl, int type) 99 { 100 struct avic_softc * const avic = (void *) pic; 101 bus_addr_t priority_reg; 102 int priority_shift; 103 uint32_t v; 104 105 KASSERT(irq < 64); 106 KASSERT(ipl < 16); 107 108 priority_reg = INTR_NIPRIORITY0 - (irq >> 3); 109 priority_shift = (irq & 7) * 4; 110 v = INTC_READ(avic, priority_reg); 111 v &= ~(0x0f << priority_shift); 112 v |= SW_TO_HW_IPL(ipl) << priority_shift; 113 INTC_WRITE(avic, priority_reg, v); 114 115 KASSERT(type == IST_LEVEL); 116 } 117 118 static const char * const avic_intr_source_names[] = AVIC_INTR_SOURCE_NAMES; 119 120 void 121 avic_source_name(struct pic_softc *pic, int irq, char *buf, size_t len) 122 { 123 strlcpy(buf, avic_intr_source_names[irq], len); 124 } 125 126 void 127 imx31_irq_handler(void *frame) 128 { 129 struct avic_softc * const avic = &avic_softc; 130 struct pic_softc * const pic = &avic->avic_pic; 131 int32_t saved_nimask; 132 int32_t vec; 133 int ipl; 134 135 saved_nimask = INTC_READ(avic, INTR_NIMASK); 136 for (;;) { 137 irq = INTC_READ(avic, INTR_NIVECSR); 138 if (irq < 0) 139 break; 140 ipl = (int16_t) irq; 141 KASSERT(ipl >= 0); 142 irq >>= 16; 143 KASSERT(irq < 64); 144 KASSERT(pic->pic_sources[irq] != NULL); 145 146 /* 147 * If this interrupt is not above the current spl, 148 * mark it as pending and try again. 149 */ 150 newipl = HW_TO_SW_IPL(ipl); 151 if (newipl <= current_spl_level) { 152 pic_mark_pending(pic, irq); 153 continue; 154 } 155 156 /* 157 * Before enabling interrupts, mask out lower priority 158 * interrupts and raise SPL to its equivalent. 159 */ 160 161 INTC_WRITE(avic, INTR_NIMASK, ipl); 162 oldipl = _splraise(newipl); 163 cpsie(I32_bit); 164 165 pic_dispatch(pic->pic_sources[irq], frame); 166 167 /* 168 * Disable interrupts again. Drop SPL. Restore saved 169 * HW interrupt level. 170 */ 171 cpsid(I32_bit); 172 splx(oldipl); 173 INTC_WRITE(avic, INTR_NIMASK, saved_nimask); 174 } 175 } 176 177 avic_init(void) 178 { 179 pic_add(&avic_softc.pic); 180 } 181
Indexes created Wed Oct 01 19:09:53 GMT 2025